JPH03129921A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To equalize the rise delay time and the fall delay time of an output signal by adding parallel MOSFETs brought to turn-on state simultaneously to MOSFETs brought to sequential form, and enlarging its substantial gate width. CONSTITUTION:With respect to two pieces of MOSFETs Q11, Q12 which are brought to sequential form, and also, determined substantially a logical condition of a logical gate circuit, MOSFETs Q13, Q14 brought to turn-on state under the same condition are provided in a parallel form, respectively. In such a way, substantial gate width of the MOSFETs Q11, Q12 is enlarged to two folds, respectively, and its substantial turn-on resistance become small to 1/2, respectively. As a result, the rise delay time and the fall delay time of each NAND gate circuit to an input clock signal are set to almost the same value.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, for example, a CM
The present invention relates to a technique that is particularly effective for use in CMO3 logic gate circuits mounted on O3 (complementary MO3) gate array integrated circuits and the like.

[Conventional technology]

There is a CMO8 logic gate circuit formed by combining MISFETs (insulated gate field effect transistors) such as MOSFETs (metal oxide semiconductor field effect transistors). Furthermore, there is a CMOS gate array integrated circuit that mounts such a CMO3 logic gate circuit.

For CMOS gate array integrated circuits, e.g.
November 1985, “Electronic Technology 11” published by Nikkan Kogyo Shimbun
It is described on pages 32 to 39 of Monthly Issue J.

[Problem to be solved by the invention]

FIG. 12 exemplifies a circuit diagram of a two-person CMOS Nant gate circuit (hereinafter simply referred to as a Nant gate circuit) mounted on a CMOS gate array integrated circuit. In FIG. 12, the Nant gate circuit includes two P-channel MO3FETs QI and Q2 that are provided in parallel between the circuit's power supply voltage VOO and the output node O and receive input signals 11 and 12 corresponding to their respective gates. , a Nant gate circuit comprising two N-channel MO3FETs QII and Q12 which are arranged in series between the output node 0 and the ground potential of the circuit and receive the input signals 11 and 12 corresponding to their respective gates. Output signal 0 is
When either the input signal i1 or 12 is set to a low level such as the ground potential of the circuit, the power supply voltage va of the circuit
When the input signals 11 and 12 are both set at a high level such as n, the input signals are set at a low level such as the ground potential of the circuit, and the logical condition o-1f-t2 is established.

FIG. 9 shows an example of a circuit diagram of a clock system circuit using the Nant gate circuit. In FIG. 9, the clock system circuit consists of three CMOS transistors connected in series.
These Nant gate circuits, including the Nant gate circuits NAG 1 to NAG3 and the inverter circuits N1 to N3, convert a predetermined clock signal CPO supplied from a pre-stage circuit (not shown) into corresponding enable signals ENI to EN.
3 to form internal clock signals CPI to CP3.

However, as systems become faster and the frequency of the transmitted clock signal becomes higher, the following problems arise in the above-mentioned CMOS Ml logic gate circuits and clock system circuits. has been revealed by the inventors of the present application. That is, in the CMOS gate array integrated circuit, the P-channel type and N-channel type MOSFETs constituting each logic gate circuit are standardized and designed to have almost the same electrical characteristics. In addition, the load capacitance CL coupled to the output terminal of each Nant gate circuit is connected to the corresponding enable signal ENI~EN.
3 is at a low level and the output signal of each Nant gate circuit is at a high level, as illustrated in FIG. When the corresponding enable signal ENI-EN3 is set to high level and the output signal of each Nant gate circuit is set to low level, as illustrated in FIG. It is discharged through the on-resistance of the N-channel MO3FET, that is, 2×r. Therefore, the fall delay time tpdL of the output signal of each Nant gate circuit with respect to the input clock signal becomes larger than its rise delay time t9dH, as illustrated in FIG. C
The duty of P3 is gradually reduced as illustrated in FIG. As a result, the operation of the system including the clock circuit becomes unstable, and the speeding up of the system is limited.

An object of the present invention is to provide a CMO3 logic gate circuit in which rise delay time and fall delay time of output signals are made uniform. Other objects of this invention are:
The object of the present invention is to stabilize the operation of a CMOS gate array integrated circuit equipped with a CMO3 logic gate circuit and a system constituted by such a CMOS gate array integrated circuit, and to promote speeding up of the operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of M constituting the CMO3 logic gate circuit
Among OSFETs, certain MOSFEs are in series form.
A parallel MOSFET that is turned on at the same time with respect to T is added to increase its effective gate width, and a series MOSFET that is turned on at the same time is added to a predetermined parallel MOSFET. This increases the actual gate length.

[For production]

According to the above means, the on-resistance when charging the load capacitance coupled to the output terminal of the logic gate circuit and the on-resistance when discharging the load capacitance are set to approximately the same value, and the output of the logic gate circuit in response to a predetermined input signal The rise delay time and fall delay time of the signal can be made almost uniform. Thereby, the duty of the clock signal transmitted through the clock system circuit including the CMO3 logic gate circuit can be maintained without being reduced or expanded. As a result, the operation of a CMOS gate array integrated circuit equipped with a CMO3 logic gate circuit and a system constituted by such a CMOS gate array integrated circuit can be stabilized and its speed can be increased.

[Embodiment 1] FIG. 1 shows a circuit diagram of a first embodiment of a CMOS Nant gate circuit (hereinafter simply referred to as a Nant gate circuit) to which the present invention is applied. 2 and 3 respectively show an equivalent circuit diagram and a signal waveform diagram of the Nant gate circuit of FIG. 1, and FIG. 9 and 10 show the Nant gate circuit of FIG. 1. A circuit diagram and a signal waveform diagram of an embodiment of a matching clock system circuit are shown, respectively. Based on these figures, an overview of the configuration and operation of the Nant gate circuit and clock system circuit of this embodiment, as well as their characteristics, will be explained. Note that the Nant gate circuit of this embodiment is mounted on a CMOS gate array integrated circuit together with a large number of CMOS logic gate circuits, although this is not particularly limited.
By selectively combining them according to user specifications, the above blacks can be combined.

Construct a circuit and a digital system that incorporates it. The circuit elements shown in FIGS. 1 and 9, along with other circuit elements not shown, are formed on a single semiconductor substrate, such as, but not limited to, single crystal silicon. Further, in the following figures, a MOSFET whose channel (back gate) part is marked with an arrow is a P-channel MO3FET, and is shown to be distinguished from an N-channel MOSFET which is not marked with an arrow.

In FIG. 1, the Nant gate circuit combines two P-channel MO3FETs QI and Q2 that are provided in parallel between the power supply voltage Vno (first power supply voltage) of the circuit and the output node 0, although this is not particularly limited. Hmm, of these, MO
The gate of 3FETQI is coupled to the first input terminal 11 of the Nant gate circuit, and the gate of MISFETQ2 is
It is coupled to a second input terminal I2.

Although not particularly limited, the Nant gate circuit further includes two sets of parallel MO3FETQ provided in series between the output node O and the ground potential (second power supply voltage) of the circuit.
I 1 and Q13 (first MISFET) and Q
12 and Q14 (first MISFET), the gates of MISFETQll and Q13 are commonly coupled to the first input terminal 11, and the gates of MISFETQll and Q13 are commonly coupled to the first input terminal 11,
The gates of Q2 and Q14 are commonly coupled to the second input terminal 12.

In this embodiment, the MO3FETs QI and Q2 and Qll to Q14 are stacked so that they have approximately the same electrical characteristics, such as their on-resistance, although this is not particularly limited.

When either the input signal 11 or 12 is set to a low level such as the ground potential of the circuit, in the Nant gate circuit,
The corresponding P-channel MO3FETQI or Q2 is turned on, and the corresponding N-channel MO3FETQI
Both Q1 and Q13 or Q12 and Q14 are turned off. Therefore, the load capacitance CL coupled to the output terminal 0 is
It is charged via TQ1 or Q2, and thereby the output signal O of the Nant gate circuit is set to a high level like the power supply voltage Voo of the circuit.

On the other hand, when the input signals 11 and 12 are both set to high level, the Nant gate circuit outputs the P-channel MO3FE.
Both TQI and Q2 are turned off, and MO3FET
QI 1 and Ql3 as well as Ql2 and Ql4 are turned on all at once. Therefore, the load capacitance cL coupled to output terminal 0 is
The output signal 0 of the Nant gate circuit is discharged through the gate l4, thereby making the output signal 0 of the Nant gate circuit low. As a result, the logic gate circuit of FIG. 1 functions as a two-man NAND gate circuit with the logic condition o-i 1.12.

Next, the clock system circuit shown in FIG. 9 is composed of three Nant gate circuits N which are substantially connected in series, although this is not particularly limited.
The Nant gate circuit shown in FIG. 1 is used as is for the Nant gate circuits NAG1 to NAG3, which include AGI to NAG3 and CMOS inverter circuits (hereinafter simply referred to as inverter circuits) N1 to N3.

Although not particularly limited, the gJl input terminal of the Nant gate circuit NAGl is supplied with a clock signal CPO from a pre-stage circuit (not shown), and its second input terminal is supplied with a predetermined enable signal ENI. Here, Kuro 7
As illustrated in the tenth example, the signal CPO is a pulse signal having a relatively high frequency, and its duty is approximately 50%, although it is not particularly limited. In addition, the enable signal ENI may be used as another enable signal E, which will be described later.
Like N2 and EN3, it is selectively set to high level under predetermined conditions.

The output signal of the Nandts gate circuit NAG1 is inverted by the inverter circuit N1, and then supplied as the internal clock signal CPI to a subsequent stage circuit (not shown) and to the first input terminal of the Nandts gate circuit NAG2. A predetermined enable signal EN2 is supplied to the second input terminal of the Nant gate circuit NAG2.

Similarly, the output signal of the Nant gate circuit NAG2 is inverted by the inverter circuit N2, and then supplied as the internal clock signal CP2 to a subsequent stage circuit (not shown), and also to the first input terminal of the Nant gate circuit NAG3. Ru. A predetermined enable signal EN3 is supplied to the second input terminal of the Nant gate circuit NAG3. The output signal of the Nant gate circuit NAG3 is the inverter circuit N
After being inverted by 3, it is supplied to a subsequent stage circuit (not shown) as an internal clock signal CP3.

For these reasons, when the enable signal ENI is set to a high level, the clock signal CPO is transmitted via the Nant gate circuit NAO1 and the inverter circuit N1, and becomes the internal clock signal CP1. Then, when the enable signals EN2 and EN3 are set to high level, they are transmitted via the Nant gate circuit NAG2 and the inverter circuit N2, and the internal clock signal C
They become P2 and CF2.

By the way, when the corresponding enable signals ENI to EN3 are set to high level, the Nant gate circuit NAGl-N
In AG3, as shown in FIG. 2<a> and (b), P channel MO3 receives these enable signals.
FETQ2 is turned off and N-channel MO8FE
TQI 1 and Ql3 are turned on.

At this time, when the corresponding clock signals are at low level, the P-channel MOSFET Q1 receiving these clock signals is turned on, and the N-channel MOSFETs Q12 and Ql4 are turned off, as shown in FIG. 2(a). Ru. Therefore, the load capacitance Ct coupled to the output terminal 0 of each Nant gate circuit is MO3FETQ
It is charged via the on-resistance r of I. As a result, as shown in FIG. 3, the output signal 0 of each Nant gate circuit has a predetermined rise delay time tp determined by the time constant rHMMrXcL with respect to the corresponding clock signal, that is, the input signal 11.
d is considered to be a high level.

On the other hand, if the enable signals EN 1 to EN 3 remain at high level and the corresponding clock signal is set to high level,
As shown in FIG. 2(b), both P-channel MO3FETs QI and Q2 of each Nant gate circuit are turned off, and N-channel MO3FETs QI and Ql
3, Ql2, and Ql4 are turned on all at once. Therefore, the load capacitance CL coupled to the output terminal 0 of each Nant gate circuit has four MOSs in series-parallel configuration.
The output signal 0 of each Nant gate circuit is discharged through the four on-resistances of the FETs. As a result, the output signal 0 of each Nant gate circuit is r+r Predetermined fall delay time tp determined by the time constant r+r = r x CL = τH
dL is set to low level. Needless to say, this fall delay time tpdt has approximately the same value as the rise delay time tPdH.

Therefore, the internal clock signals CPI to CP3 in FIG. 9 are changed to the corresponding clock signals CPI to CP3 as shown in FIG.
The data of PO or internal clock signals CP1 and CF2 is inherited as is. That is, in the Nant gate circuit of this embodiment, two MOS transistors are connected in series and substantially determine the logic conditions of the logic gate circuit.
MOSFETQI3 and Ql4, which are turned on under the same conditions, are provided in parallel to FETQI1 and Ql2.
The effective gate widths of and Ql2 are each doubled, and their effective on-resistances are reduced by half. As a result, the rise delay time tpdH and fall delay time t1)dL of each Nant's gate circuit with respect to the input clock signal have almost the same value. This stabilizes the operation of the clock system circuit that incorporates the Nant gate circuit and the digital system that incorporates it, and promotes higher speeds.

[Embodiment 2] FIG. 4 shows a second example of a Nant gate circuit to which the present invention is applied! A circuit diagram of an example h is shown. 5 and 6 show an equivalent circuit diagram and a signal waveform diagram of the Nant gate circuit of FIG. 4, respectively. The Nant gate circuit of this embodiment basically follows the first embodiment, and MOSFETs QI and Q2 and Qll and Ql2 correspond to MOSFETs QI and Q2 and Qll and Ql2 in FIG. 1, respectively. do. Hereinafter, regarding the different parts from the above first embodiment,
Add a description.

In FIG. 4, the Nant gate circuit includes, but is not particularly limited to, a P-channel MO3FETQ3 (second MISFET) provided in series-parallel form between the circuit's power supply voltage Van (first power supply voltage) and the output node 0. and Ql and Q2, of which MO3FETQ3 is:
The gates of the MOSFETs QI and Q2 are connected to the ground potential of the circuit to keep them in a steady on state, and the gates of the MOSFETs QI and Q2 are connected to the first input terminal 11 and the second
are respectively coupled to input terminals 12 of the .

The Nant gate circuit further includes two N-channel MO5FETs QII and Ql that are connected in series between the output node 0 and the ground potential (second power supply voltage) of the circuit.
Add 2. The gates of these MOSFETs are commonly coupled to the input terminals 11 and 12, respectively.

For these reasons, MOSFETs QI and Q2 and Qll and Ql2 operate in correspondence with MOSFETs QI and Q2 and Qll-Ql3 and Ql2-Ql4 in FIG. 1, and are selectively turned on according to input signals 11 and 12. Ru.

As a result, the logic gate circuit in FIG.
It functions as a two-man NAND gate circuit with the logical condition of 2. At this time, since the MO3FETQ3 is kept in the ON state constantly, it does not affect the logic conditions of the logic gate circuit.Needless to say, the Nant gate circuit of FIG.
As the NAND gate circuit NAGI-NAG3 in Fig. 9,
Similarly, a lock system circuit can be constructed.

By the way, the ninth circuit using the Nant gate circuit of this example
In the clock system circuit shown in the figure, when the corresponding enable signals ENI to EN3 are set to high level, each Nant gate circuit receives these enable signals as shown in FIGS. 5(a) and 5(b). P channel MO
S F ETQ 2 is turned off and N channel M
O3FETQ11 is turned on.

At this time, if the corresponding clock signal is at low level, the P-channel MO3FETQ1 that receives these clock signals is turned on, and the N-channel MO3FETQ12 is turned off, as shown in FIG. 5(a). Ru. As described above, MO3FETQ3 is kept in the on state constantly. Therefore, the load capacitance CL coupled to the output terminal O of each Nant gate circuit is charged via the two on-resistances r corresponding to the two MO3FETs Q3 and Ql connected in series. As a result, the output signal 0 of each Nant gate circuit is as shown in FIG.
With respect to the corresponding clock signal, that is, the input signal 11, a predetermined rise delay time tp determined by a time constant of τH" 2X r X CL
dH is considered to be a high level.

On the other hand, if the enable signals ENI to EN3 remain at high level and the corresponding clock signal is set to high level, the fifth
As shown in Figure (b), P-channel MO3FETs QI and Q2 of each Nant gate circuit are both turned off, and both N-channel MO3FETs QI1 and Ql2 are turned on. Therefore, the load capacitance CL coupled to the output terminal 0 of each Nant gate circuit is discharged via the two on-resistances r corresponding to the two MO3FETs QI1 and Ql2 connected in series.

As a result, as shown in FIG. 6, the output signal 0 of each Nant gate circuit has a predetermined value determined by the time constant τL = 'l Falling delay time Lp
dL is set to low level. Needless to say,
This fall delay time L1)dL has the same value as the rise delay time tpdH. Therefore, the internal clock signals CPI to CP3 in FIG.
No. 216 CPO or internal clock signals CPI and C
It will take over the duty of F2 as it is. In other words, in the Nant gate circuit of this embodiment, two
MO3FETQ3, which is turned on at the same time as these MOSFETs, is provided in series for each MO3FETQI and Q2, in other words, MO3FETQ3, which is turned on at the same time as these MOSFETs, doubles the effective gate length of MO3FETQI and Q2. Its effective on-resistance is doubled. As a result, the rise delay time tpdH and fall delay time tpdt of each Nant gate circuit with respect to the input black signal have almost the same value. This stabilizes the operation of the clock system circuit that incorporates the Nant gate circuit and the digital system that incorporates it, and promotes higher speeds.

[Embodiment 3] FIG. 7 shows a circuit diagram of a third embodiment of a Nant gate circuit to which the present invention is applied, and FIG. 8 shows an equivalent circuit diagram of the Nant gate circuit of FIG. It is shown. Note that the Nant gate circuit of this embodiment is basically the same as that of the second embodiment described above. MO3FETQI and Q2
and Qll and Ql2 are MO3FETQ in FIG.
They correspond directly to I and Q2 and Qll and Ql2, respectively. Hereinafter, explanations will be added regarding parts that are different from the second embodiment. The signal waveform of the Nant gate circuit of this embodiment is almost the same as the signal waveform diagram of FIG. 6 above.

In FIG. 7, the Nant gate circuit includes two series P-channel MO3FETQ4 (second MISFET) and Ql and Q5 (second MISFET) and Q2
Of these, the gates of MO3FETs Q4 and Ql are commonly coupled and further coupled to the first input terminal 11 of the Nandt gate circuit. Similarly, the gates of MISFETs Q5 and Q2 are commonly coupled and further coupled to the second input terminal 12 of the Nant gate circuit.

The Nant gate circuit further includes two N-channel MO3FETs QII and Ql that are connected in series between the output node 0 and the ground potential (second power supply voltage) of the circuit.
2, the gates of these MOSFETs are commonly coupled to the input terminals 11 and 12, respectively.

From these things, MO3FETQ4・Ql and Q5・
Q2, Qli and Ql2 are MO3 in Fig. 4 above.
It operates in correspondence with FETs QI and Q2 and Qll and Ql2, and is selectively turned on according to input signals 11 and 12. As a result, the logic gate circuit shown in Figure @7 functions as a two-man NAND gate circuit having the logic condition o-il.12. Needless to say, the Nant gate circuit of FIG. 7 can constitute a similar circuit as the Nant gate circuits NAG1 to NAG3 of FIG. 9.

By the way, the ninth circuit using the Nant gate circuit of this example
In the clock system circuit shown in the figure, when the corresponding enable signals ENI to EN3 are set to high level, each Nant gate circuit receives these enable signals as shown in FIGS. 8(a) and (b). P channel MO
3FETQ5 and Q2 are turned off, and N-channel MO3FETQII is turned on.

At this time, if the corresponding clock signal is at a low level, the P-channel MO3FETQ4 and Ql receiving these clock signals are turned on, and the N-channel MO3FETQ12 is turned off, as shown in FIG. 8(a). Ru. Therefore, the load capacitance cL coupled to the output terminal 0 of each Nant gate circuit is 2
MOS FET Q 4 and 2 corresponding to Ql
It is charged through on-resistances r. As a result, as shown in FIG. 6, the output signal 0 of each Nant gate circuit has a predetermined rise delay time Lp determined by the time constant rH-2XrXCL with respect to the corresponding clock signal, that is, the input signal i1.
dH is considered to be a high level.

On the other hand, if the enable signals ENI to EN3 remain at high level and the corresponding clock signal is set to high level, the eighth
As shown in figure (b), the P-channel MO3FETs Q4 and Ql and Q5 and Q of each Nant gate circuit
2 are turned off all at once, and the N-channel MO3FET
Both QII and Ql2 are turned on. Therefore, the load capacitance CL coupled to the output terminal 0 of each Nant gate circuit is connected to the two MISFETs Qll in series.
and is discharged via two on-resistances r corresponding to Ql2. As a result, as shown in FIG. 6, the output signal 0 of each Nant gate circuit has a predetermined value determined by the time constant τL!!2×rxCL = rH with respect to the corresponding clock f', that is, the input signal 11. Falling delay time tp
dL is set to low level. Needless to say, this fall delay time tpat has the same value as the rise delay time tpdH. Therefore, the internal clock signals CPI to CP3 in FIG. 9 inherit the duty of the corresponding input white ivy signal, that is, the clock signal CPO or the internal clock signals CP1 and CF2, as shown in FIG. 10. . In other words, in the Nant gate circuit of this embodiment, two M
MO3FETs Q4 and Q5, which are turned on under the same logic conditions, are provided in series with O3FETs QI and Q2, respectively, thereby doubling the effective gate lengths of MO3FETs QI and Q2, and increasing the effective On-resistance is doubled. As a result, the rise delay time t9dH and fall delay time tpdt of each Nant gate circuit with respect to the input clock signal are as follows.
are assumed to be the same value. This stabilizes the operation of the clock system circuit that incorporates the Nant gate circuit and the digital system that incorporates it, and promotes higher speeds.

As shown in the above three embodiments, this invention can be applied to CM
CMOS installed in OS gate array integrated circuit
By applying the present invention to a 26 logic gate circuit, the following effects can be obtained. That is, (among the plurality of MOSFETs constituting the 11CM OS logic gate circuit, a parallel MOSFET that is turned on at the same time is added to a predetermined series MOSFET to increase its substantial gate width, Predetermined MOS FETs in parallel configuration
By adding a series MO3FET that is turned on simultaneously to increase its effective gate length, the on-resistance for charging and discharging the load capacitance coupled to the output terminal of the logic gate circuit can be reduced. The effect is that the on-resistances of the two transistors can be made almost the same value.

(2) According to the above (11), it is possible to obtain the effect that the rise delay time and the fall delay time of the output signal of the logic gate circuit with respect to a predetermined input signal can be made almost uniform.

(3) The above +11 term and (2) term provide the effect that the duty of the clock signal transmitted through the clock system circuit made of the CMOS logic gate circuit can be maintained without being reduced or expanded.

(4) Items (11 to (3)) above stabilize the operation of CMOS gate array integrated circuits equipped with CMO3 logic gate circuits and systems configured with such CMOS gate array integrated circuits, and increase their speed. This has the effect of being able to promote the project.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, two sets of parallel MO3FETQI 1 are connected in series.
and Q13 and Q12 and Q14 can be replaced by two sets of series MO3FETs QI 1 and Q12 in parallel configuration and commonly coupled 13 and Q14. In FIG. 4, MISFETQ3 is a parallel MO5
In FIG. 7, MISFETs Q4 and Q5 may be provided between the corresponding MISFETs QI and Q2 and the output node 0. Further, if it is fixed that MISFETQ2 does not affect the delay time of the logic gate circuit, MISFETQ5 can be omitted. In each embodiment, the number of input terminals is arbitrary, and arbitrary logical conditions can be adopted. In addition, the MOSFETs constituting the logic gate circuit may be other types of MISFETs.
The gate array integrated circuit may also include multiple types of MOS FETs with stepwise different sizes. In this case, the logic gate circuit can be The delay time and fall delay time can be made uniform.

Furthermore, various embodiments can be adopted, such as the specific circuit configuration of each embodiment, the combination of MOSFET conductivity types, and power supply voltages.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to a Nant gate circuit of a CMOS gate array integrated circuit, which is the background application field, but the invention is not limited to this, for example,
The present invention can be applied to other types of CMOS3 and logic gate circuits, and can also be applied to various digital integrated circuits that are formed as a single CMO3 logic gate circuit or are combined with similar CMOS logic gate circuits. is at least commercial
It can be widely used in semiconductor integrated circuit devices including O3 logic gate circuits and CMO3 logic gate circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, among a plurality of MISFETs constituting a CM OS logic gate circuit, a predetermined M
Parallel MIS that is turned on at the same time as ISFET
By adding an FET to increase its effective gate width, and by adding a series MISFET that is turned on at the same time to a predetermined parallel MISFET, increasing its effective gate length, It is possible to substantially equalize the rise delay time and fall delay time of the output signal of the logic gate circuit with respect to a predetermined input signal. This makes it possible to stabilize the operation of a CMOS gate array integrated circuit equipped with three CMO3 logic gates and a system constituted by such a CMOS gate array integrated circuit, and to promote speeding up of the operation.

[Brief Description of the Drawings] Fig. 1 is a CMOS Nant equalization circuit diagram to which the present invention is applied, Fig. 3 is a signal waveform diagram of the CMOS Nant gate circuit of Fig. 1, and Fig. 4 is a diagram of this CMOS Nant gate circuit. An equalization circuit diagram of a CMOS NAN to which the invention is applied, FIG. 6 is a signal waveform diagram of the CMOS NAN gate circuit No. 1, and FIG. 7 is an equalization circuit diagram of a CMOS NAN to which the invention is applied. 9 is a circuit diagram showing an embodiment of a clock system circuit that combines the Nant gate circuit of FIG. 1, 4, or 7; FIG. 10 is an embodiment of the clock system circuit of FIG. 9. A signal waveform diagram showing an example; FIG. 11 is a signal waveform diagram showing an example of a clock system circuit including a conventional CMOS Nantes gate circuit; FIG. 12 is a circuit diagram showing an example of a conventional CMOS Nantes gate circuit; Equalization circuit diagram of the circuit. FIG. 14 is a signal waveform diagram of the CMOS Nant gate circuit of FIG. 12. Q1~Q5...P channel MO5FET, Qll-
Q14...N-channel MO5FET. CL: Load capacity, r: On-resistance. NAGI ~NAG3-- ・0MO3syF gate circuit, N1-N3...CMOS inverter circuit. Figure 1 Figure 2 Figure 3 Collection 4 Figure Figure Figure Figure 10 Figure 11 Figure P3 , r , , ' Figure Figure 12 Figure 13 Figure 14

Claims (1)

[Claims] 1. In series and/or between the first power supply voltage and the output node and between the output node and the second power supply voltage, respectively.
Alternatively, a logic gate circuit including a plurality of MISFETs arranged in parallel and receiving input signals corresponding to respective gates is provided, and the rise delay time and fall delay time of the output signal of the logic gate circuit with respect to a predetermined input signal are provided. 1. A semiconductor integrated circuit device characterized in that the characteristics of the semiconductor integrated circuit device are substantially the same. 2. Multiple MISFETs forming the above logic gate circuit
Among them, the gate width of the predetermined MISFETs in the series configuration is substantially increased by providing the first MISFET that is turned on at the same time in the parallel configuration, and the predetermined MISFETs in the parallel configuration are , the semiconductor integrated circuit device according to claim 1, wherein the second MISFET which is turned on at the same time is provided in series so that its gate length is substantially increased. . 3. The semiconductor integrated circuit device is a CMOS gate array integrated circuit, and the logic gate circuit constitutes a clock system circuit. semiconductor integrated circuit devices.