KR920001911B1 - Output circuit for ic - Google Patents

Abstract

The circuit prevents the turning on of PMOS and NMOS transistor at the same time by separating the input level of the transistors using transmission gate so that the dynamic current on switching on is reduced. The circut comprises a first PMOS transistor whose gate is connected to an input terminal and source to VCC, a first NMOS transistor whose source is connected to VCC and gate connected to an input terminal, a transmisstion gate comprising a PMOS transistor and a NMOS transistor, a second PMOS transistor having a source connected to VCC and a gate connected to a drain of the first PMOS transistor, and a second NMOS transistor having a source connected to a reference voltage, a drain connected to an output terminal and a gate connected to a drain of the first NMOS transistor.

Description

Instant power consumption elimination circuit

1 is a conventional circuit diagram.

2 is a voltage characteristic diagram during operation of FIG.

3 is a current characteristic diagram in operation of FIG.

4 is a circuit diagram according to the present invention.

5 is a voltage characteristic diagram during operation of FIG.

6 is a current characteristic diagram in operation of FIG.

The present invention relates to an instantaneous power consumption removal circuit of a semiconductor device, and more particularly, to an instantaneous power consumption removal circuit capable of reducing power consumption by removing dynamic current generated during switching in a CMOS transistor. . CMOS transistors are transistors having a structure in which P and N MOS transistors are complementary, and have advantages of low power consumption and large noise margin.

1 shows a conventional general output circuit for use in a semiconductor device. Referring to FIG. 1, a PMOS transistor TP1 having a source-drain path connected between a power supply voltage VCC and a node 12 is connected, and a drain-source is connected between the node 12 and the ground. N-MOS transistor TN1 to which a passage is connected is connected. The gates of the P and N-MOS transistors TP1 and TN1 are connected to the input terminal 10. The + node 12 is connected to the gates of the P and N-MOS transistors TP2 and TN2, and the P-MOS transistors having a source-drain path connected between the power supply voltage VCC and the node 14 TP2 is connected, and the N-MOS transistor TN2 to which the drain-source path is connected is connected between the node 14 and the ground. The node 14 is also connected to the output terminal 16.

이 될때까지 P모스 트랜지스터(TP1)는 리니어 상태이고 N모스 트랜지스터(TN1)는 ″포화″상태이며, 상기 입력이

이며 P 및 N모스 트랜지스터(TP1)(TN1)는 모두 포화상태이며, 상기 P모스 트랜지스터(TP1)의 드레쉬홀드 전압이 V_TP1일때 입력이 VCC/2에서 VCC-V_TP1이 될때까지 상기 P모스 트랜지스터(TP1)가 포화상태이고, N모스 트랜지스터(TN1)가 리니어 상태이다. 계속해서, 상기 입력이 VCC-V_TP1에서 VCC가 될때까지 P모스 트랜지스터(TP1)가 ″오프″상태이고 N모스 트랜지스터(TN1)가 리니어 상태가 된다. 따라서 입력단(10)을 통해(A1)와 같은 입력신호가 입력되면 노드(12)에서 (B1)와 같은 신호를 출력한다.FIG. 2 is a diagram showing voltage characteristics during operation of FIG. 1, and FIG. 3 is a diagram showing current characteristics. The operation of FIG. 1 will be described with reference to FIGS. 2 and 3. A signal that increases linearly from 0V to VCC is input through the input terminal 10 together with A1 of FIG. 2. The drain Threshold voltage (Treshold) (Voltage) until when the (V _TN1) the P MOS transistor (TP1) is the linear state of an N-MOS transistor (TN1) of the input are N MOS transistor (TN1) from 0V is "Off State. Input is at V _TN

Until the P-MOS transistor TP1 is in a linear state and the N-MOS transistor TN1 is in a ″ saturation ″ state.

P and N-MOS transistors TP1 and TN1 are both saturated, and when the threshold voltage of the P-MOS transistor TP1 is V _TP1 , the P-MOS is input until the input becomes VCC / 2 to VCC-V _TP1. Transistor TP1 is saturated and NMOS transistor TN1 is linear. Subsequently, the P-MOS transistor TP1 is in the " off " state and the N-MOS transistor TN1 is in the linear state until the input becomes VCC-V _TP1 to VCC. Therefore, when an input signal such as A1 is input through the input terminal 10, the node 12 outputs a signal such as (B1).

When the signal of (B1) is input to the gates of the P and N-MOS transistors TP2 and TN2, the P and N-MOS transistors TP2 and TN2 are opposite to the upper P and N-MOS transistors TP1 and TN1. The node 14 outputs a signal such as (C1) having a potential opposite to that of the (B1) signal. Except when the input is less than V _TN1 or greater than VCC-V _TP1 , the P and N-MOS transistors TP1 (TN1) are simultaneously ″ on ″ to create a current path between the power supply voltage terminal VCC and ground. Dynamic current flows. In particular, when both the P and NMOS transistors TP1 and TN1 are saturated, the dynamic current increases as shown in FIG. In addition, similar to the P and N-MOS transistors TP1 and TN1, the P and N-MOS transistors TP2 and TN2 generate a current path between the power supply voltage terminal VCC and the ground, and the dynamic current flows. The general CMOS output circuit has a problem in that the PMOS transistor and the NMOS transistor are turned on at the same time when the logic state is changed, so that a DC current flows between the power supply voltage terminal and the ground, thereby increasing power consumption.

Accordingly, an object of the present invention is to provide an instantaneous power consumption elimination circuit that separates input points of a P-MOS transistor and an N-MOS transistor, thereby reducing power consumption by preventing simultaneous ″ on ″ during switching of logic states. . In order to achieve the above object, the present invention provides a first PMOS transistor having an input terminal, a source connected to a drain and a power voltage, and a gate connected to the input terminal, a source connected to a drain and a reference voltage, and a source connected to the input terminal. A first N-MOS transistor having a gate, a P-MOS transistor having a gate connected to a reference voltage, and an N-MOS transistor having a gate connected to a power supply voltage are connected in parallel and connected between a drain of the first P-MOS transistor and a drain of the first N-MOS transistor. A second P-MOS transistor having a transmission gate, a source and a drain connected to a power supply voltage and an output terminal, and a gate connected to a drain of the first MOS transistor, a source and a drain connected to a reference voltage and an output terminal, respectively, The gay connected to the drain of the first N-MOS transistor It is composed of a second PMOS transistor.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

4 is a circuit diagram of an instantaneous power consumption elimination circuit according to the present invention. Referring to FIG. 4, a PMOS transistor TP11 having a source-drain passage connected between the power supply voltage terminal VCC and the node 22 is connected, and a drain source passage between the node 24 and ground. N-MOS transistor TN11 to which is connected is connected. The input terminal 20 is connected to the gates of the P and N-MOS transistors TP1 and TN1. Between the node 22 and the node 24, a P-MOS transistor having a gate grounded and a source-drain passage connected thereto, and an N-MOS transistor having a gate connected to the power supply voltage terminal VCC and a drain-source passage connected thereto. Transmission gates connected in parallel are connected. A gate of the PMOS transistor TP12 is connected to the node 22, and a gate of the NMOS transistor TN12 is connected to the node 24. The P-MOS transistor TP12 has a source connected to a power supply voltage terminal VCC, and a drain connected to the node 26. The N-MOS transistor TN12 has a drain connected to a node 26 and a source connected to ground. . The node 26 is also connected to the output terminal 28.

이 된다. 상기에서 V22는 노드(22)의 전위, R_TN11(S)는 N모스 트랜지스터(TN11)의 포화저항, R_TP11(L)는 P모스 트랜지스터(TP11)의 리니어 저항, RT는 트랜스미션 게이트(T)의 저항을 나타낸다. 또한 노드(24)의 전위는

가 된다. 상기에서 V24는 노드(24)의 전위이다.FIG. 5 shows voltage characteristics in the operation of FIG. 4 and FIG. 6 shows current characteristics in the operation of FIG. The operation of FIG. 4 will be described in detail with reference to FIGS. 5 and 6. A signal that linearly increases from 0V to VCC is input through the input terminal 20 as shown in FIG. 5 (A2). At this time, the P-MOS transistor TP11 is in a linear state and the N-MOS transistor TN11 is in the ″ off ″ state until the _NMOS transistor TN11 becomes the threshold hold voltage V _TN11 at 0V. 22) and the potential of the node 24 maintain the potential voltage VCC. Then, when the input becomes larger than V _TN11 , the PMOS transistor TP11 is in a linear state and the PMOS transistor TN11 is in an ″ off ″ state. At that time, the potential of the node 22

Becomes Where V22 is the potential of the node 22, R _TN11 (S) is the saturation resistance of the NMOS transistor TN11, R _TP11 (L) is the linear resistance of the PMOS transistor TP11, and RT is the transmission gate (T). Indicates resistance. In addition, the potential of the node 24

Becomes In the above, V24 is the potential of the node 24.

가 되며, 노드(24)의 전위는

가 된다. 상기 R_TP11(S)는 P모스 트랜지스터(TP11)의 포화저항이다. 그후 상기한 입력이 VCC-V_TP11될때가지 상기 P모스 트랜지스터(TP11)는 포화상태이고, N모스 트랜지스터(TN11)는 리니어 상태가 된다. 그때 노드(22)의 전위는

가 되며, 노드(24)의 전위는

가 된다. 상기에서 R_TN11(L)는 N모스 트랜지스터(TN11)의 리니어 저항을 나타낸다.The voltage difference between the node 22 and the node 24 is determined by the resistance value of the transmission gate (T). Thereafter, when the threshold hold voltage of the P-MOS transistor _TP11 is V _TP11 , both the P and N-MOS transistors TP11 (TN11) are saturated before the input becomes VCC-V _TP11 . At that time, the potential of the node 22

Where the potential of node 24 is

Becomes R _TP11 (S) is a saturation resistance of the PMOS transistor TP11. Thereafter, the P-MOS transistor TP11 is saturated and the N-MOS transistor TN11 is in a linear state until the input becomes VCC-V _TP11 . At that time, the potential of the node 22

Where the potential of node 24 is

Becomes In the above, R _TN11 (L) represents the linear resistance of the NMOS transistor TN11.

Subsequently, when the input is from VCC-V _TP11 to VCC, the P-MOS transistor TP11 is ″ off ″, and since the N-MOS transistor TN11 is in a linear state, the potentials of the nodes 22 and 24 are It becomes the ground potential (0V). Therefore, when a signal such as the fifth (A2) is input through the input terminal 20, the node 22 outputs a signal such as (B2), and the node 24 outputs a signal such as (C2).

The signals of (B2) and (C2) are input to the gates of the P and N-MOS transistors TP12 and TN12, respectively. At this time, when the (C2) signal has the level of the power supply voltage VCC, the N-MOS transistor TN12 is ″ on ″, and when the (C2) signal has the level of the ground voltage 0V, the N-MOS transistor TN12 is ″ off ″. . In addition, the (B2) signal maintains the level of the power supply voltage VCC, and the (C2) signal has a level of the ground voltage (0V) after a predetermined time after the signal (C2) is converted to the level of the ground voltage (0V). Accordingly, the P-MOS transistor TP12 is ″ off ″ while the N-MOS transistor TN12 is sufficiently ″ off ″ while maintaining the ″ off ″ state, and is ″ turned on ″ after a predetermined delay time td. A signal as shown in (D2) of FIG. The predetermined delay time td may vary depending on the 'on' resistance value of the transmission gate.

Therefore, since the P-MOS transistor TP12 and the N-MOS transistor TN12 are not ″ ON ″ at the same time, the PMOS transistor TP12 and the N-MOS transistor TN12 are blocked by blocking the current path between the power supply voltage terminal VCC and the ground. This eliminates the dynamic current between), as shown in FIG.

As described above, the present invention has the advantage of greatly reducing power consumption by eliminating the dynamic current generated during switching by separating the input potential of the CMOS transistor using a transmission gate.

Claims (3)

In the instantaneous power consumption elimination circuit, a first PMOS transistor having an input terminal, a source connected to the drain and the power supply voltage, a gate connected to the input terminal, a source connected to the drain and the reference voltage, and a gate connected to the input terminal. A transmission gate connected between the first NMOS transistor, the PMOS transistor having a gate connected to a reference voltage, and the NMOS transistor having a gate connected to a power supply voltage in parallel, and connected between the drain of the first PMOS transistor and the drain of the first NMOS transistor; A second PMOS transistor having a source and a drain connected to a power supply voltage and an output terminal, and a gate connected to the drain of the first MOS transistor, and a source and a drain connected to a reference voltage and an output terminal, respectively, and the first NMOS. 2P having a gate connected to the drain of the transistor Moment, characterized in that the transistor constituting the switch the power consumption control circuitry. 2. The instantaneous power consumption control circuit according to claim 1, wherein the reference voltage is a ground potential. 2. The instantaneous power consumption control circuit according to claim 1, wherein the transmission gate is used as a resistance means.

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