KR910005449A - Instant power consumption elimination circuit - Google Patents

Instant power consumption elimination circuit Download PDF

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Publication number
KR910005449A
KR910005449A KR1019890011388A KR890011388A KR910005449A KR 910005449 A KR910005449 A KR 910005449A KR 1019890011388 A KR1019890011388 A KR 1019890011388A KR 890011388 A KR890011388 A KR 890011388A KR 910005449 A KR910005449 A KR 910005449A
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KR
South Korea
Prior art keywords
drain
power consumption
transistor
gate connected
reference voltage
Prior art date
Application number
KR1019890011388A
Other languages
Korean (ko)
Other versions
KR920001911B1 (en
Inventor
허찬
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890011388A priority Critical patent/KR920001911B1/en
Publication of KR910005449A publication Critical patent/KR910005449A/en
Application granted granted Critical
Publication of KR920001911B1 publication Critical patent/KR920001911B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음.No content.

Description

순간 전력소모 제거회로Instant power consumption elimination circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 따른 회로도.4 is a circuit diagram according to the present invention.

제5도는 제4도의 동작시 전압특성도.5 is a voltage characteristic diagram during operation of FIG.

제6도는 제4도의 동작시 전류특성도.6 is a current characteristic diagram in operation of FIG.

Claims (3)

순간 전력소모 제거회로에 있어서, 입력단자와, 드레인과 전원전압에 연결된 소오스와 상기 입력단자에 연결된 게이트를 가지는 제1P모스 트랜지스터와, 드레인과 기준전압과 연결된 소오스와 상기 입력단자에 연결된 게이트를 가지는 제1N모스 트랜지스터와, 게이트가 기준전압에 연결된 P모스 트랜지스터와 게이트가 전원전압에 연결된 N모스 트랜지스터가 병렬로 연결되어 상기 제1P모스 트랜지스터의 드레인과 제1N모스 트랜지스터의 드레인 사이에 연결된 트랜스미션 게이트와, 전원전압 및 출력단자에 각각 접속된 소오스 및 드레인과 상기 제1모스 트랜지스터의 드레인에 접속되 게이트를 가지는 제2P모스트랜지스터와, 기준전압과 출력단자에 각각 접속된 소오스 및 드레인과 상기 제1N모스 트랜지스터의 드레인에 접속된 게이트를 가지는 제2P모스 트랜지스터를 구성함을 특징으로 하는 순간 전력소모 제어회로.In the instantaneous power consumption elimination circuit, a first PMOS transistor having an input terminal, a source connected to the drain and the power supply voltage, a gate connected to the input terminal, a source connected to the drain and the reference voltage, and a gate connected to the input terminal. A transmission gate connected between the first NMOS transistor, the PMOS transistor having a gate connected to a reference voltage, and the NMOS transistor having a gate connected to a power supply voltage in parallel, and connected between the drain of the first PMOS transistor and the drain of the first NMOS transistor; A second P MOS transistor having a source and a drain connected to a power supply voltage and an output terminal and a gate connected to the drain of the first MOS transistor, and a source and a drain connected to a reference voltage and an output terminal, respectively, and the first N-MOS. A second P module having a gate connected to the drain of the transistor An instantaneous power consumption control circuit comprising a switch transistor. 제1항에 있어서, 상기 기준전압이 접지전위임을 특징으로 하는 순간 전력소모 제어회로.2. The instantaneous power consumption control circuit according to claim 1, wherein the reference voltage is a ground potential. 제1항에 있어서, 상기 트랜스미션 게이트가 저항 수단으로 이용됨을 특징으로 하는 순간 전력소모 제어회로.2. The instantaneous power consumption control circuit according to claim 1, wherein the transmission gate is used as a resistance means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890011388A 1989-08-10 1989-08-10 Output circuit for ic KR920001911B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890011388A KR920001911B1 (en) 1989-08-10 1989-08-10 Output circuit for ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890011388A KR920001911B1 (en) 1989-08-10 1989-08-10 Output circuit for ic

Publications (2)

Publication Number Publication Date
KR910005449A true KR910005449A (en) 1991-03-30
KR920001911B1 KR920001911B1 (en) 1992-03-06

Family

ID=19288815

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890011388A KR920001911B1 (en) 1989-08-10 1989-08-10 Output circuit for ic

Country Status (1)

Country Link
KR (1) KR920001911B1 (en)

Also Published As

Publication number Publication date
KR920001911B1 (en) 1992-03-06

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