JPH02252315A - Input buffer circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for the conversion of an input level with one kind of an input buffer circuit by providing the transmission gate of an N- channel MOS transistor(TR) on the pre-stage of an input buffer circuit for semiconductor integrated circuit. CONSTITUTION:Let the source level of an N-channel MOS TR(NMOS TR) 2 be Vin, a gate level be Vg, a drain level be Vo, and a threshold voltage be Vth, then the relation of Vo=Vin exists in the operation at the linear region of the TR 2, and the relation of Vo=Vg-Vth exists in the operation at the saturation region of the TR 2. When the signal of a CMOS level is inputted from an input terminal 1, a signal with a level nearly equal to a TTL level signal is outputted from the drain electrode of the TR 2. When the signal of a TTL level is inputted from the input terminal 1, since the TR 2 is operated at a linear region, a signal whose level is nearly equal to the input level is outputted from the drain. Thus, even when an input signal with a different level is inputted from an external input terminal, the signal with a nearly equal level is outputted from the drain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to an input buffer circuit.

[Conventional technology]

Conventionally, in this type of input buffer circuit, the input of the input buffer 6 was simply connected to the external input terminal 5 of the semiconductor integrated circuit, as shown in FIG.

[Problem to be solved by the invention]

The above-described conventional input buffer circuit has the drawback that when the potential levels of the input signals differ, the input potential level must be converted, and a different type of input buffer circuit must be used.

An object of the present invention is to provide a buffer circuit for a semiconductor integrated circuit that solves the above problems.

[Failure to solve the problem]

In order to achieve the above object, an input buffer circuit for a semiconductor integrated circuit according to the present invention includes an N-channel MO3! - It has a transistor transmission gate 1.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In the figure, the source electrode of an N-channel MO transistor 2 is connected to an external input terminal 1, and the gate electrode is connected to a power supply electrode 4. Furthermore, the drain electrode is connected to the input terminal of the input buffer 3.

If the source electrode potential of N-channel MOS transistor 2 is Vin, the gate I-electrode potential is Vg, the drain ts potential is vO5, and the threshold voltage is vth, then N-channel MOS transistor 2 operates in the linear region. Ha, Vo
=Vin, and the operation in the saturation region is Vo =Vg
-Vth. When a CMOS level signal is input from input terminal 1, N-channel MOS transistor 2 operates in the saturation region, so from the drain electrode,
A signal with approximately the same amplitude as the TTL level signal is output.

Furthermore, when a TTL level signal is input from the input terminal 1, the N-channel MOS transistor 2 operates in a linear region, so that a signal with approximately the same amplitude as the input is output from the drain electrode. Therefore, even if signals with different input levels are input from the external input terminal, the signals from the drain electrode are
Signals with approximately equal potential levels are output.

〔Effect of the invention〕

As described above, the present invention has the advantage that it is possible to realize one type of input buffer circuit instead of the conventional two types of input buffer circuits depending on the input level.

Furthermore, even if an overvoltage is applied to the input, only a voltage lower than the power supply voltage is applied to the gate electrode of the input buffer, which has the effect of protecting the input buffer circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional input buffer circuit. 1.5...External input terminal 2...N channel MO8) transistor 3.6...Input buffer 4...Power supply voltage Patent applicant NEC Corporation

Claims (1)

[Claims] (1) An input buffer circuit for a semiconductor integrated circuit, comprising a transmission gate of an N-channel MOS transistor at the front stage of the input buffer circuit for a semiconductor integrated circuit.