JPS6030166A - Mos integrated circuit device - Google Patents
Mos integrated circuit deviceInfo
- Publication number
- JPS6030166A JPS6030166A JP13797483A JP13797483A JPS6030166A JP S6030166 A JPS6030166 A JP S6030166A JP 13797483 A JP13797483 A JP 13797483A JP 13797483 A JP13797483 A JP 13797483A JP S6030166 A JPS6030166 A JP S6030166A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- well
- wells
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 8
- 230000006378 damage Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000003068 static effect Effects 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 abstract description 2
- -1 arsenic ions Chemical class 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 3
- 239000004575 stone Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000000126 in silico method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明にＭＯ８型集積回路装置に関し、特に異常電圧に
よる破壊を防止する入力保護回路の入力部金儲えたＭＯ
８型集積回路装置に関する。[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to an MO8 type integrated circuit device, and in particular to an input section of an input protection circuit for preventing destruction due to abnormal voltage.
The present invention relates to an 8-type integrated circuit device.
ＭＯ８型トランジスタのゲート絶縁膜はきわめて薄い為
、ゲート電極に印加される電圧が過大になると破壊され
易い欠点金有している。特に装置に組み込まれる前に゛
人体等に帯電した静電気により破壊される頻度が高い。Since the gate insulating film of the MO8 type transistor is extremely thin, it has the drawback that it is easily destroyed if the voltage applied to the gate electrode becomes excessive. In particular, there is a high frequency of destruction due to static electricity charged on the human body, etc., before being incorporated into equipment.
つまシ、酸化膜の耐圧は５０〜１００Ｖでめシ、普通に
誘起される静屯戒圧数ＫＶ〜十数ＩＣＶの静電気放電に
より・簡単に破壊されるか、又破壊に至らないまでも耐
圧劣化を引き起す。The withstand voltage of the oxide film is 50 to 100 V, but it is easily destroyed by electrostatic discharge of normally induced static pressure of several KV to several dozen ICV, or even if it does not lead to destruction, the withstand voltage is low. cause deterioration.
このような問題を解決する為に、種々の入力。In order to solve such problems, various inputs are required.
出力保護回路が報告されている。Output protection circuits have been reported.
二股に、保護回路は基板とは逆導電型の不純物合金む拡
散層と、放電の機能を有した回路との組会せにより構成
される。又これらの保護回路はボンディングバッドと保
護されるべきトランジスタ間に設置される設計手法が採
用されておシ、ボンディングパッドから延在するアルミ
ニウム（Ａ＃）と拡散層を開口部を通して接続しなけれ
ばならない。The protection circuit has two parts: a diffusion layer containing an impurity alloy having a conductivity type opposite to that of the substrate, and a circuit having a discharge function. In addition, these protection circuits are designed to be installed between the bonding pad and the transistor to be protected, and the aluminum (A#) extending from the bonding pad and the diffusion layer must be connected through an opening. No.
一方、近年の集積回路の高密度化、高速化の進行に伴な
い拡散層は浅くなってきている。すなわち、接合容量を
小さくでき、短チヤネルトランジスタが可能となること
から高速化が、又拡散層及びチャネル長が小さくなるこ
とから高集積化が可能となる。On the other hand, as integrated circuits have become denser and faster in recent years, the diffusion layer has become shallower. That is, since the junction capacitance can be reduced and short channel transistors can be formed, higher speeds can be achieved, and since the diffusion layer and channel length can be reduced, higher integration can be achieved.
しかしながら、保護回路を構成している拡散層とＡ４の
接続部においては入力端子に印加された高電圧が直接拡
散層にかかる為に、拡散層が極めて浅いと局所的な発熱
が起る。Ａ石が直接拡散層と接している場合、この発熱
により合金反応が起り、接合は破壊される。However, since the high voltage applied to the input terminal is applied directly to the diffusion layer at the connection between the diffusion layer and A4 constituting the protection circuit, local heat generation occurs if the diffusion layer is extremely shallow. When the A stone is in direct contact with the diffusion layer, this heat generation causes an alloy reaction and the bond is destroyed.
すなわち、境界部を介してＡ、Ｉ３がシリコｙ（Ｓｔ）
の中へ、又逆にＳＩがＡ石の中へ置換する形で反応が起
こるために発熱量が大きく、”ｔｌが接合位してしまう
。すなわち突き抜は現像が起る。That is, A and I3 are in silico y (St) through the boundary part.
Because a reaction occurs in which SI is substituted into A stone, or conversely, the amount of heat generated is large, and tl is bonded. In other words, development occurs in punching.
これを避ける為に、純粋なｈ−ｅだけでな（Ｓ＋入〕の
Ａ、Ｉ３ヲ用いたシＡ看配線の下に自己整合型にポリシ
リコン配線を設ける方法が考案されているが、上記の発
熱がかなりの温既になる為に、拡散層中の８１も置換さ
れることが実際に報告されている。In order to avoid this, a method has been devised in which a polysilicon wiring is provided in a self-aligned manner under the SiA wiring using not only pure h-e (S+ input) A and I3, but the method described above It has actually been reported that 81 in the diffusion layer is also replaced because the heat generated by the molecule becomes considerably warm.
この為、第１図に示すように、Ａ！配線１０９と拡散層
１０６の間に拡散１４の導電型と同一の不純物をドープ
したポリシリコン１０５ 全介在させ拡散層光面から見
掛上人看を遠ざけると共に、上記ドーピングした不純物
ｋｐ型Ｓｉ基板１０１中に拡散させ接合を深くする方法
が用いられている。For this reason, as shown in Figure 1, A! A polysilicon 105 doped with the same conductivity type as the diffusion layer 14 is completely interposed between the wiring 109 and the diffusion layer 106 to keep the apparent conductivity away from the optical surface of the diffusion layer, and the doped impurity kp type Si substrate 101 A method is used to make the bond deeper by diffusing it into the inside.
１０２は接合が深く形成された拡散層である。102 is a diffusion layer in which a junction is formed deeply.
また１０３はフィールド酸化膜、１０７，１０８は絶縁
膜で通常絶縁膜１０７にはＣＶＤ−３ｉＯ２゜絶縁膜１
０Ｂとしてはリンガラス（ＰＳＧ）膜などが用いられる
。Further, 103 is a field oxide film, 107 and 108 are insulating films, and the normal insulating film 107 is a CVD-3iO2° insulating film 1.
As the 0B, a phosphorus glass (PSG) film or the like is used.
しかしながら、上記の構成とするためにはポリシリコン
の成長工程、および該ポリシリコンのパターニング工程
が必要になる。たとえこのポリシリコンが他の目的にも
用いられ必要不可決な場合でも、上記ポリシリコンを拡
散層に選択的に接触せしめる開口部を設ける為の工程全
付加せねばならないという、何れも特別工程を付加する
という欠点金有していた。However, in order to obtain the above structure, a polysilicon growth process and a polysilicon patterning process are required. Even if this polysilicon is used for other purposes and is not necessary, a special process must be added in order to provide an opening that selectively brings the polysilicon into contact with the diffusion layer. It had the disadvantage of adding money.
本発明の目的は、上記欠点全除去し、耐静電気対策ｔ−
実施したＭＯ８型集積回路装置全提供することにある。The purpose of the present invention is to eliminate all the above-mentioned drawbacks and to take anti-static measures.
The purpose is to provide all the MO8 type integrated circuit devices implemented.
本発明のＭＯ８型集積回路装置は、−導電型の半導体基
板と、該半導体基板に設けられたＭＯＢ型内部回路と、
該ＭＯ８型内部回路が形成されている領域と入力端子と
の間の領域に設けられた逆導電型のウェルと、前記ウェ
ルに一部が重畳し。The MO8 type integrated circuit device of the present invention includes a -conductivity type semiconductor substrate, an MOB type internal circuit provided on the semiconductor substrate,
A well of an opposite conductivity type provided in a region between the region where the MO8 type internal circuit is formed and the input terminal partially overlaps the well.
かつ該ウェルよシも浅い逆導電型の領域と、前記ウェル
の上部に設けられた開口部と、該開口部に接し入力端子
に接続される少なくとも１つのアルミニウム配線とを含
んで構成される。The well also includes a shallow region of the opposite conductivity type, an opening provided in the upper part of the well, and at least one aluminum wire in contact with the opening and connected to an input terminal.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第２図（ａ）〜（Ｃ）は本発明の第１の実施例及びその
製造方法全説明するため工程順に示した断面図である。FIGS. 2(a) to 2(C) are sectional views shown in the order of steps to fully explain the first embodiment of the present invention and its manufacturing method.
この第１の実施例では本発明による入力部の保護をする
入力保護部と内部回路を構成するＭＯ８厖索子の代表と
してのｐチャンネルＭＯ８）ランジスタ（以下ｐ−ＭＯ
８ＦＥＴと記す）とを同時に製造する場合について説明
する。In this first embodiment, a p-channel MO8 transistor (hereinafter referred to as a p-MO8) transistor (hereinafter referred to as p-MO8) is representative of an input protection section and an internal circuit for protecting an input section according to the present invention.
8FET) will be manufactured at the same time.
まず、第２図（ａ）に示すように、ｐ型ＳＩ基板２０１
に二つのｎウェル２０２，２０２”ｅ形成する。ｎウェ
ル２０２は本発明の入力保護部を形成するためのｎウェ
ルであＬ”ウェル２０２′ は内部回路の代表としての
ｐ−ＭＯＳＦＥＴ用のｎウェルでるる。ｎウェル２０２
は内部回路用ｎウェル２０２′と同時に作られるから探
い接合金有する。First, as shown in FIG. 2(a), a p-type SI substrate 201
Two n-wells 202 and 202''e are formed in the n-well 202 and 202''e, respectively. Well de Ruru. n-well 202
The N-well 202' is fabricated at the same time as the internal circuit N-well 202' and has a probe bond.
ｎウェル２０２は入力端子と内部回路との間の領域に形
成する。次いで、通常の方法により、フィールド酸化膜
２０３．シリコン酸化膜２０４を形成する。The n-well 202 is formed in a region between the input terminal and the internal circuit. Next, a field oxide film 203. is formed using a conventional method. A silicon oxide film 204 is formed.
次に、第２図（ｂ）に示すように、ｐ−ＭＯ８Ｆ’Ｅ’
Ｉ’用のゲート電極２０５をｎウェル２０２′領域内の
シリコン酸化膜２０４の上の所定の位置に形成する。次
に、ヒ素（八８）全イオン注入して本発明の入力保護部
の浅いｎ型領域２０６を形成すると同時に内部回路のｎ
ウェル用コンタクト領域２０６′金形成する。ｎ型拡散
層２０６はｎウェル２０２′に重畳して設けられ、かつ
ｎウェル２０２′よシ浅いことが必要である。次に、ホ
ウ素（Ｂ）全イオン注入してｐ−ＭＯＳＦＥＴのｐ型ソ
ース・トンイン領域２０７ ｔ−形成する。Next, as shown in FIG. 2(b), p-MO8F'E'
A gate electrode 205 for I' is formed at a predetermined position on the silicon oxide film 204 in the n-well 202' region. Next, all ions of arsenic (88) are implanted to form the shallow n-type region 206 of the input protection part of the present invention, and at the same time, the n-type region 206 of the internal circuit is implanted.
Well contact region 206' is formed with gold. The n-type diffusion layer 206 is provided to overlap the n-well 202' and needs to be shallower than the n-well 202'. Next, all boron (B) ions are implanted to form a p-type source tunnel region 207t- of a p-MOSFET.
次に第２図（Ｃ）に示すように、絶縁膜２０８を設けて
開口し、Ａ石配線２０９，２１０，２１１ を形成する
。Ａ沼配線２１０はその一端が本発明の入力保護部の一
部をなすｎ型領域２０６に接触し、他端が入力端子（図
示せず）に接続する。ＡＡ配置渫２０ ’ｉは図示して
いないがその他端が入力保護回路または内部回路に接続
する。Ａｆｆｌ配線２１１は内部回路のｎウェルの引出
し電極とな、り、ＶＣＣ電源に接続される。Next, as shown in FIG. 2(C), an insulating film 208 is provided and opened to form A-stone wirings 209, 210, 211. One end of the A-swamp wiring 210 contacts the n-type region 206 that forms part of the input protection section of the present invention, and the other end connects to an input terminal (not shown). Although not shown, the other end of the AA arrangement 20'i is connected to an input protection circuit or an internal circuit. The Affl wiring 211 serves as an extraction electrode of the n-well of the internal circuit, and is connected to the VCC power supply.
この実施例では、浅いｎ型領域２０６全深いｎウェル２
０２に重畳させてあシ、Ａｐ配置２１０を直接に浅いｎ
型領域２０６に接触させている。In this embodiment, the shallow n-type region 206 is entirely deep n-well 2
02, and the Ap arrangement 210 is directly shallow n.
It is in contact with the mold area 206.
Ｋ１図に示した従来例と比ベポリシリコン１０５がない
ことが異っている。従って、入力端子に高電圧が印加さ
れて、ＡＡとｎ型領域２０６との接触部に発熱が起り、
そのためＡ２がＳＩ中へ拡散してｎ型領域２０６の接合
よシも深く侵入したとしても、即ちいわゆるＡｎの突き
抜けが起ったとしても深いｎ型ウェル２０２が存在する
から接合破壊は起らない。従来のポリシリコン１０５が
なくても静電破壊対策が達せられるのである。The difference from the conventional example shown in Figure K1 is that there is no polysilicon 105. Therefore, a high voltage is applied to the input terminal, and heat is generated at the contact portion between AA and the n-type region 206.
Therefore, even if A2 diffuses into the SI and penetrates deeply into the junction of the n-type region 206, that is, even if so-called penetration of An occurs, the junction will not be destroyed because the deep n-type well 202 exists. . Measures against electrostatic discharge damage can be achieved even without the conventional polysilicon 105.
第３図は本発明の第２の実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the invention.
ｐｆｉｓ１基板３０１にｎウェル３０２全設け、通常の
方法によ）フィールド酸化膜３０３．クリコン酸化膜３
０４を設けた後、ｎウェル３０２に重畳させてｎウェル
３０２よシ浅いｎ型領域３０６を形成する。絶縁膜３０
８ ｔ−設けた後、開口してＡ彫配鵡３０９，３１０を
形成する。図示していないがＡ、８配線３１０の他端は
入力端子に接続し、ＡＡ配線３０９の他端は入力保護回
路あるいは内部回路に接続する。ｎウェル３０２を入力
端子と内部回路との間の領域に形成することは第１の実
施例と同じである。また、浅いｎ型領域３０６の接合破
壊に対する保護効果も第１の実施例と同じである。N-well 302 is completely formed on pfis1 substrate 301, and field oxide film 303. Crycon oxide film 3
04, an n-type region 306 that is shallower than the n-well 302 is formed so as to overlap the n-well 302. Insulating film 30
8 After providing T-, it is opened to form A carvings 309 and 310. Although not shown, the other end of the A, 8 wiring 310 is connected to an input terminal, and the other end of the AA wiring 309 is connected to an input protection circuit or an internal circuit. Forming the n-well 302 in the region between the input terminal and the internal circuit is the same as in the first embodiment. Furthermore, the protective effect of the shallow n-type region 306 against junction breakdown is also the same as in the first embodiment.
第４図（ａ）、 （ｂ）は本発明の第３の実施例の断面
図及び等価回路図である。FIGS. 4(a) and 4(b) are a sectional view and an equivalent circuit diagram of a third embodiment of the present invention.
この実施例は本発明を入力保護回路に実施したものであ
る。In this embodiment, the present invention is implemented in an input protection circuit.
第１．第２の実施例と同様にｐ型Ｓ１基板４０１にｎウ
ェル４０２．フィールド酸化膜４０３．シリコン酸化膜
４°０４を設ける。シリコン酸化膜４０４の上にポリシ
コンでゲート電極４０５と抵抗４０６と全形成する。ゲ
ート電極４０５でマスクとしＡｓのイオン注入によｌｎ
型ソース・ドレイン領域４０７’ｌｒ形成する。ここで
ドレイン領域がつエル４０２と重畳して本発咀ｐ入力保
護部を形成する。即ち、この実施例は入力保護回路用の
ｎチャタネ９ＭＯ８ＦＥＴに本発明を実施したものであ
る。1st. As in the second embodiment, a p-type S1 substrate 401 and an n-well 402. Field oxide film 403. A silicon oxide film 4°04 is provided. A gate electrode 405 and a resistor 406 are entirely formed using polysilicon on the silicon oxide film 404. Using the gate electrode 405 as a mask, ln is implanted by As ion implantation.
Type source/drain regions 407'lr are formed. Here, the drain region overlaps the well 402 to form the main p-input protection section. That is, in this embodiment, the present invention is implemented in an n-channel 9MO8FET for an input protection circuit.
次に、絶縁膜３０８を設け、開口してへ！配線４０９．
４１０，４１１ ｔ”形成する。図示していないがＡ４
配！４１０の他端は入力端子に接続し、ＡＡ配線４０９
の他端は内部回路に接続する。Next, an insulating film 308 is provided and opened! Wiring 409.
410,411 t". Although not shown, A4
Delivery! The other end of 410 is connected to the input terminal, and the AA wiring 409
The other end is connected to the internal circuit.
ＡＡ配線４０９はゲート電極４０５とソース電極とを短
絡し、第３図（ｂ）に示すように接地される。The AA wiring 409 short-circuits the gate electrode 405 and the source electrode and is grounded as shown in FIG. 3(b).
入力は、入力端子からＡＡ配線４１０．抵抗４０６全通
ってＭＯＳＦＥＴのドレイン領域に入る。ここで、入力
が高電圧であった場合、第１の実施例で説明したような
ドレイン領域２０７の接合破壊が起ることがあるが、た
とえ接合破壊が起っても深いｎウェル４０２が存在する
のでＳｉ基板との短絡を生じない。The input is from the input terminal to the AA wiring 410. It passes through the entire resistor 406 and enters the drain region of the MOSFET. Here, if the input voltage is high, junction breakdown of the drain region 207 may occur as explained in the first embodiment, but even if junction breakdown occurs, the deep n-well 402 still exists. Therefore, no short circuit with the Si substrate occurs.
以上三つの実施例で説明したように、高電圧が印加され
る入力部の不純物導入領域に深いウェル全重畳して設け
たので、従来のようなポリシリコンを設ける必要がなく
、入力部の短絡を防ぐ仁とができる。しかもウェルは内
部回路のウェルと同時に形成できるので特別の工程を付
加する必要はない。As explained in the above three embodiments, since the deep well is provided completely overlapping the impurity doped region of the input section where high voltage is applied, there is no need to provide polysilicon as in the conventional case, and short-circuiting of the input section is avoided. You can prevent this from happening. Furthermore, since the well can be formed at the same time as the well of the internal circuit, there is no need to add a special process.
上記三つの実施例は、Ｓ＋基板がｐ型の場合で説明した
が、ｎ型であってもすべての導ｖＬ型を逆にすれば同様
に実施できることは明らかでらシ、同様の効果を得るこ
とができる。The above three embodiments have been explained in the case where the S+ substrate is p-type, but it is clear that even if the S+ substrate is p-type, it can be implemented in the same way by reversing all the conductive vL types, and the same effect can be obtained. be able to.
以上説明したとお勺、本発明によれば、特別な製造工程
全付加することなしに簡単な構造で耐静電気対策の施こ
されたＭＯ８型集積回路装置全容易に得ることができる
。As described above, according to the present invention, an MO8 type integrated circuit device having a simple structure and anti-static measures can be easily obtained without adding any special manufacturing steps.
第１図は従来のＣＭＯ８型集積画集積回路装置の断面図
、第２図（ａ）〜（Ｃ）は本発明の一実施例の構造並び
にその製造方法全説明する為の工程順に示した断面図、
第３図は本発明の第２の実施例の要部断面図、第４図（
ａ）（ｂ）は本発明の第３の実施例の断面図及び等価回
路図である。
の拡散層、１ｏ３・・・・・・フィールド酸化膜、１ｏ
５・・・・・・ポリシリコン、１ｏ６・・団・浅１い接
合の拡散層、１０７−＝ ・・・絶縁膜（ＣＶＤ−８１
０２）、１０８−”・・・リンガラス（Ｐ２Ｏ）膜、１
ｏ９・・・・・・ＡＪ配線、２０１°°゛・・・ｐ型Ｓ
ｉ基板、２０２． ２０２’ ・−・−・−ｎウェル、
２ｏ３・・団・フィールド酸化Ｌ ２０４・・・、・・
・シリコン酸化膜、２ｏ５・・・・・・ゲート電極、２
０６・・・・・・ｎ型領域、２０６′・旧・・ｎ型コン
タクト領域、２０７・・・・・・ソース・ドレイン領域
、２０８・・・・・・絶縁膜、２０９，２１０．２１１
・・団・Ａ看配線、３０１・・・・・・ｐ型ＳＩ基板、
３ｏ２・・・・・・ｎウェ／ｌ／、３０３・・川・フィ
ールド酸化ＨＬ ３ｏ４・・・・・・シリコン酸化膜、
３ｏ６・・・・・・ｎ型領域、３０９゜３１０・・・・
・・Ａｐ配線、４０１・・・・・・ｐ型Ｓｉ基板、４０
２・・・・・・ｎウェル、４ｏ３・・・・・・フィール
ド酸化膜、４０４・・・・・・シリコン酸化膜、４０５
・・・用ゲート４極、４０６・・・・・・抵抗、４ｏ７
・・・・・・ソース・ドレイン領域、４０８・・・・・
・絶縁膜、４０９，４１０゜４１１・・・・・・Ａ１配
ａ１４１４・・・・・・開口部。
第１ 回
第２回FIG. 1 is a cross-sectional view of a conventional CMO8 type integrated circuit device, and FIGS. 2(a) to (C) are cross-sectional views showing the structure of an embodiment of the present invention and its manufacturing method in the order of steps. figure,
FIG. 3 is a sectional view of the main part of the second embodiment of the present invention, and FIG. 4 (
a) and (b) are a sectional view and an equivalent circuit diagram of a third embodiment of the present invention. diffusion layer, 1o3... field oxide film, 1o
5...Polysilicon, 1o6...group/shallow junction diffusion layer, 107-=...insulating film (CVD-81
02), 108-”...Phosphorous glass (P2O) film, 1
o9...AJ wiring, 201°°゛...p type S
i-board, 202. 202' ・-・-・-n well,
2o3... group field oxidation L 204...,...
・Silicon oxide film, 2o5...Gate electrode, 2
06...n-type region, 206'-old...n-type contact region, 207...source/drain region, 208...insulating film, 209,210.211
... Group A wiring, 301 ... p-type SI board,
3o2...n wa/l/, 303...river/field oxidation HL 3o4...silicon oxide film,
3o6...N-type region, 309°310...
...Ap wiring, 401...P-type Si substrate, 40
2...N well, 4o3...Field oxide film, 404...Silicon oxide film, 405
4-pole gate for...406...Resistance, 4o7
...Source/drain region, 408...
- Insulating film, 409, 410° 411... A1 arrangement a1414... Opening. 1st 2nd
Claims (2)
れたＭＯ８型内部回路と、該ＭＯ８型内部回路が形成さ
れている領域と入力端子との間の領域に設けられた逆導
電型のウェルと、前記ウェルに一部が重畳し、かつ該ウ
ェルよりも浅い逆導電型の領域と、前記ウェルの上部に
設けられた開口部と、該開口部に接し前記入力端子に接
続される少なくとも１つのアルミニウム配線とを含むこ
とを特徴とするＭＯ８型集積回路装置。(1) - A conductive type semiconductor substrate, an MO8 type internal circuit provided on the semiconductor substrate, and an opposite conductive type provided in a region between the area where the MO8 type internal circuit is formed and the input terminal. a well, a region of the opposite conductivity type that partially overlaps the well and is shallower than the well, an opening provided at the top of the well, and a region in contact with the opening and connected to the input terminal. An MO8 type integrated circuit device, characterized in that it includes at least one aluminum wiring.
型で同一接合深さ會有する特許請求の範囲第（１）項記
載のＭｏ ８ ｍ集積回路装置。(2) The Mo 8 m integrated circuit device according to claim 1, wherein the well has the same conductivity type and the same junction depth as the well of the MO 8 internal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13797483A JPS6030166A (en) | 1983-07-28 | 1983-07-28 | Mos integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13797483A JPS6030166A (en) | 1983-07-28 | 1983-07-28 | Mos integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6030166A true JPS6030166A (en) | 1985-02-15 |
Family
ID=15211088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13797483A Pending JPS6030166A (en) | 1983-07-28 | 1983-07-28 | Mos integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6030166A (en) |
-
1983
- 1983-07-28 JP JP13797483A patent/JPS6030166A/en active Pending
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