JPH01185971A - Insulated gate semiconductor device - Google Patents
Insulated gate semiconductor deviceInfo
- Publication number
- JPH01185971A JPH01185971A JP1119088A JP1119088A JPH01185971A JP H01185971 A JPH01185971 A JP H01185971A JP 1119088 A JP1119088 A JP 1119088A JP 1119088 A JP1119088 A JP 1119088A JP H01185971 A JPH01185971 A JP H01185971A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- layer
- gate
- conductivity type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 230000002265 prevention Effects 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 abstract 4
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ソース層とドレイン層の間のチャネル形成半
導体ＳＪ！域上に備えられるゲート電極とドレイン層の
間にサージ電圧に対する保護回路を内蔵した絶縁ゲート
型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a channel forming semiconductor SJ! between a source layer and a drain layer. The present invention relates to an insulated gate type semiconductor device having a built-in protection circuit against surge voltage between a gate electrode and a drain layer provided on a region.
（従来の技術〕
第２図は従来の保護回路内蔵絶縁ゲート型半導体装置を
示し、ドレイン層となるＮ型半導体基板１にＰ型ベース
層２が形成され、その中に端部にチャネル領域４が残る
ようにＮ型ソース層３が形成されている。チャネル領域
４の上にはゲート絶縁膜５１を介してＮ型ポリシリコン
のゲート６が設けられ、ゲート６に絶縁膜５２の開口部
で配線７１が接触している。他の配線７２はソース層３
およびベース層２に接触している。このＭＯＳ Ｆ Ｅ
Ｔのゲート入力の保護回路として、シリコン基板の中に
形成される２層２１およびその２層２１の中に形成され
配線７１に接触するＮ層３１の間に生ずるダイオードと
２層２１とＮ型基板１の間に生ずるダイオードがゲート
配線７１とドレインとの間に逆向きに直列しかしこのよ
うな内蔵保護回路ではＮ層３１，２層２１．Ｎ１１ｌが
ＮＰＮ ）ランジスタを形成するために、トランジスタ
動作させないためには２層２１とその中に形成されるＮ
層３１によって作られるダイオードの伝導度変調による
電流増幅をなくす必要がある。そのためには、２層２１
．Ｎ層３１の不純物濃度の設定および２層２１．Ｎ層３
１によって形成される逆阻止電圧等に制約があるため、
条件設定が複雑になる欠点があった。(Prior Art) FIG. 2 shows a conventional insulated gate type semiconductor device with a built-in protection circuit. An N-type source layer 3 is formed so that a gate insulating film 52 remains on the channel region 4. An N-type polysilicon gate 6 is provided on the channel region 4 with a gate insulating film 51 interposed therebetween. Wiring 71 is in contact with the source layer 3. Other wiring 72 is in contact with the source layer 3.
and is in contact with the base layer 2. This MOS F E
As a protection circuit for the gate input of T, a diode is formed between two layers 21 formed in the silicon substrate and an N layer 31 formed in the two layers 21 and in contact with the wiring 71, and a diode is formed between the two layers 21 and the N type. However, in such a built-in protection circuit, a diode generated between the substrate 1 and the gate wiring 71 and the drain is connected in series in opposite directions. (N11l is NPN) In order to form a transistor, the second layer 21 and the NPN formed therein are required to prevent the transistor from operating.
Current amplification due to diode conductivity modulation created by layer 31 needs to be eliminated. To do this, two layers 21
．． Setting the impurity concentration of the N layer 31 and setting the second layer 21. N layer 3
Since there are restrictions on the reverse blocking voltage etc. formed by 1,
The disadvantage was that the condition settings were complicated.
本発明の目的は、保護回路の内蔵によってトランジスタ
が形成されることがなく、装置設計上の条件を容易に設
定できる絶縁ゲート型半導体装置を提供することにある
。An object of the present invention is to provide an insulated gate semiconductor device in which no transistor is formed due to the built-in protection circuit, and device design conditions can be easily set.
（＆！を解決するための手段〕
上述の目的を達成するために、本発明の絶縁ゲート型半
導体装置は、第一導電型のドレイン層とその中に設けら
れる第二導電型層とによって電圧クランプダイオードを
形成し、絶縁膜上の第一４電型のポリシリコン層ゲート
とその中に設けられる第二導電型のポリシリコン層とに
よって逆流防止ダイオードを形成し、ゲート端子とドレ
イン端子の間に逆向きに直列接続される前記電圧クラン
プダイオードとその逆流防止ダイオードによる保護回路
を有するものとする。(Means for Solving &!) In order to achieve the above-mentioned object, the insulated gate semiconductor device of the present invention has a first conductivity type drain layer and a second conductivity type layer provided therein to reduce voltage. A clamp diode is formed, and a backflow prevention diode is formed by a first fourth conductivity type polysilicon layer gate on an insulating film and a second conductivity type polysilicon layer provided therein, and a backflow prevention diode is formed between the gate terminal and the drain terminal. The voltage clamp diode and its reverse current prevention diode are connected in series in reverse directions to provide a protection circuit.
このような絶縁ゲート型半導体装置の保護回路は半導体
素体中に形成される電圧クランプダイオードと逆向きに
直列接続される絶縁膜上のゲートとしての多結晶シリコ
ン層内に形成される逆流防止ダイオードからなるため、
保護回路のために半導体素体内にトランジスタが形成さ
れることがない。The protection circuit for such an insulated gate type semiconductor device consists of a voltage clamp diode formed in the semiconductor body and a backflow prevention diode formed in a polycrystalline silicon layer as a gate on an insulating film connected in series in the opposite direction. Because it consists of
No transistors are formed within the semiconductor body for protection circuitry.
第１図は本発明の一実施例を示し、第２図と共通の部分
には同一の符号が付されている。第２図と異なりＮ型シ
リコン基板１内に形成される２層２１内にはＮ層がなく
、ゲート絶縁膜５１の上のゲート６のＮ型ポリシリコン
層の中にそれより低不純物濃度で高抵抗のＰ型ポリシリ
コン層８が形成されている。ポリシリコン層８はチャネ
ル領域４の上をはずれた部分に形成され、配線７１に接
続されている。この構成においてＮ層１と２層２１によ
って作られるダイオードがゲートに入力される負のサー
ジ電圧によりプレイダウンした場合、そのプレイダウン
電流は、配線７１．Ｐ型ポリシリコン層８を抜けてゲー
ト絶縁膜５１の上のＮ型ゲート６を介してソース配＆Ｉ
７２に流れる。これは、等価回路′図の第３図において
ＭＯ３ＦＥＴＩＯのドレイン端子りからＮ層１と２層２
１により形成される電圧クランプダイオード２０．ＰＮ
ポリシリコン層８．６によって形成されるダイオード３
０を介して図示されない配線を通ってゲート端子Ｇに流
れることを意味する。ＭＯ３ＦＥＴＩＯを導通させるた
めにゲート６に正の電圧が印加されるときには、ダイオ
ード３０は逆流防止ダイオードとして働くよう耐圧２０
Ｖ程度に作成される。FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. Unlike FIG. 2, there is no N layer in the two layers 21 formed in the N type silicon substrate 1, and the N type polysilicon layer of the gate 6 on the gate insulating film 51 has an impurity concentration lower than that of the N type polysilicon layer. A high resistance P-type polysilicon layer 8 is formed. Polysilicon layer 8 is formed in a portion off channel region 4 and connected to wiring 71 . In this configuration, when the diode formed by the N layer 1 and the second layer 21 is played down by a negative surge voltage input to the gate, the playdown current is caused by the wiring 71. The source wiring &I passes through the P-type polysilicon layer 8 and passes through the N-type gate 6 on the gate insulating film 51.
It flows to 72. In Figure 3 of the equivalent circuit diagram, N layer 1 and 2 layer 2 are connected from the drain terminal of MO3FETIO.
A voltage clamp diode formed by 20.1. P.N.
Diode 3 formed by polysilicon layer 8.6
0 to the gate terminal G through an unillustrated wiring. When a positive voltage is applied to the gate 6 to make the MO3FETIO conductive, the diode 30 has a breakdown voltage of 20 to function as a backflow prevention diode.
It is created to about V.
本発明によれば、保護回路を半導体素体内に形成される
電圧クランプダイオードとポリシリコンゲート内に形成
される逆流防止ダイオードによって構成することにより
、保護ダイオード形成のためにトランジスタ構造が半導
体素体に生ずることがないので、容易に製造プロセス条
件が設定できる絶縁ゲート型半導体装置が得られる。According to the present invention, by configuring the protection circuit with a voltage clamp diode formed within the semiconductor body and a reverse current prevention diode formed within the polysilicon gate, the transistor structure is integrated into the semiconductor body to form the protection diode. Since this does not occur, an insulated gate semiconductor device can be obtained in which manufacturing process conditions can be easily set.
第１図は本発明の一実施例の断面図、第２図は従来の保
護回路内蔵絶縁ゲート型半導体装置の断面図、第３図は
第１図の半導体装置の等価回路図である。
１：シリコン基板、２：Ｐ型ベース層、２１：ダイオー
ド２層、３：Ｎ型ソース層、４：チャネル領域、５１：
ゲート絶縁膜、６：Ｎ型ポリシリコンゲー）、７１．７
２：配線、８；Ｐ型ポリシリコン層。FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of a conventional insulated gate semiconductor device with a built-in protection circuit, and FIG. 3 is an equivalent circuit diagram of the semiconductor device of FIG. 1. DESCRIPTION OF SYMBOLS 1: Silicon substrate, 2: P-type base layer, 21: Diode 2 layer, 3: N-type source layer, 4: Channel region, 51:
Gate insulating film, 6: N-type polysilicon gate), 71.7
2: Wiring, 8: P-type polysilicon layer.
Claims (1)
導電型層とによって電圧クランプダイオードを形成し、
絶縁膜上のポリシリコン層ゲートとその中に設けられる
第二導電型のポリシリコン層とによって逆流防止ダイオ
ードを形成し、ゲート端子とドレイン端子の間に逆向き
に直列接続される前記電圧クランプダイオードと該逆流
防止ダイオードよりなる保護回路を有することを特徴と
する絶縁ゲート型半導体装置。1) forming a voltage clamp diode with a first conductivity type drain layer and a second conductivity type layer provided therein;
A reverse current prevention diode is formed by a polysilicon layer gate on an insulating film and a second conductivity type polysilicon layer provided therein, and the voltage clamp diode is connected in series in opposite directions between a gate terminal and a drain terminal. An insulated gate type semiconductor device comprising a protection circuit comprising: and the reverse current prevention diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63011190A JPH0810764B2 (en) | 1988-01-21 | 1988-01-21 | Insulated gate type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63011190A JPH0810764B2 (en) | 1988-01-21 | 1988-01-21 | Insulated gate type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01185971A true JPH01185971A (en) | 1989-07-25 |
| JPH0810764B2 JPH0810764B2 (en) | 1996-01-31 |
Family
ID=11771144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63011190A Expired - Lifetime JPH0810764B2 (en) | 1988-01-21 | 1988-01-21 | Insulated gate type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810764B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04767A (en) * | 1990-04-02 | 1992-01-06 | Fuji Electric Co Ltd | Mos semiconductor element |
| JPH08116051A (en) * | 1994-10-14 | 1996-05-07 | Nec Corp | Semiconductor device |
| JP2006324839A (en) * | 2005-05-18 | 2006-11-30 | Fuji Electric Holdings Co Ltd | Compound type semiconductor device |
| JP2013077656A (en) * | 2011-09-29 | 2013-04-25 | Toshiba Corp | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58151051A (en) * | 1982-03-03 | 1983-09-08 | Hitachi Ltd | Semiconductor device |
-
1988
- 1988-01-21 JP JP63011190A patent/JPH0810764B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58151051A (en) * | 1982-03-03 | 1983-09-08 | Hitachi Ltd | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04767A (en) * | 1990-04-02 | 1992-01-06 | Fuji Electric Co Ltd | Mos semiconductor element |
| JPH08116051A (en) * | 1994-10-14 | 1996-05-07 | Nec Corp | Semiconductor device |
| JP2006324839A (en) * | 2005-05-18 | 2006-11-30 | Fuji Electric Holdings Co Ltd | Compound type semiconductor device |
| JP2013077656A (en) * | 2011-09-29 | 2013-04-25 | Toshiba Corp | Semiconductor device |
| US9349721B2 (en) | 2011-09-29 | 2016-05-24 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0810764B2 (en) | 1996-01-31 |
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