JPS58151051A - Semiconductor device - Google Patents

Abstract

PURPOSE:To remarkably widen the p-n junction area and improve current capacity by forming a part in the depth direction in the p-n layer provided in a semiconductor layer. CONSTITUTION:A poly-Si film is stacked on an SiO2 film 2 formed on p type Si substrate 1, and n<+> regions 3, 6 and 4, 7 and p region 5 connected to electrode terminal are formed in such a film. According to this structure, a current capacity between the regions 3 and 4 is almost doubled but the p-n junction is reduced to about 1/3 as compared with parallel formation of the conventional n-p-n region, because the p-n junction of the conventional type exists at the interface with the SiO2 film but still it exists, in the case of this invention, mainly within the poly-Si since it extends in the depth direction.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a semiconductor substrate formed on an insulating film on a semiconductor substrate.
The present invention relates to an integrated semiconductor device.

(2) Prior Art Conventionally, a nine-pn junction semiconductor device formed on an insulating film has been formed on an insulating film, as shown in FIG. , an insulating film 2 is formed on a semiconductor substrate 1, a polycrystalline silicon film is deposited thereon, and impurities are selectively introduced into the polycrystalline silicon film to form an n4p region 3.4 and a p region 5. Therefore, since the np junction is configured in the horizontal direction and the silicon film thickness is as thin as 0.5 fi m, the cross-sectional area of the junction is small.

The current capacity flowing through the 3.4 terminal was limited.

(3) Purpose of the Invention The present invention provides a new pnW structure that is effective in solving the problems of the prior art described above. The purpose is to provide a coupling conductor device.

(4) General description of the invention In order to achieve the above object, in the pn junction semiconductor device of the present invention, the pn junction surface in the semiconductor film is configured as a horizontal cross section, the junction cross section is increased, and the current capacity is significantly increased. We are trying to improve.

(5) Examples Hereinafter, the present invention will be explained in detail with reference to examples.

Figure 5g2 is an embodiment of the present invention, and is a vertical cross-sectional structural view of the main part of a polycrystalline silicon film having a pn junction in the depth direction.

Here - 1 medium Qt type silicon (specific resistance 20Ω・equipment),
2 is silicon oxide film (thickness α6 m), 3.4 is thickness I
An n-type high concentration impurity region (impurity concentration 15 Xi
O'~w-"Js5 is a p shadow region with an impurity concentration of 2
6 is the n-type high concentration impurity region 7 with a depth α2 m and a thickness o and aJm in the depth direction.
%3.
The current capacity flowing between the two is approximately twice as high as that of the conventional structure. Furthermore, the leakage current that is thought to occur in the sp" junction is approximately 1 when compared with the conventional structure at the same current value.
/3. This is because the conventional pn junction exists mostly at the interface with the oxide film because it is in the lateral direction, whereas the pn junction of the present invention is located inside the polycrystalline silicon because it is in the depth direction. I panic because most of it exists.

FIG. 3 shows another embodiment of the present invention, in which the pn junction in the depth direction is formed only on the surface. Even in such a structure, since the area of the pn junction surface per unit area increases, it is effective in increasing the current capacity.

FIG. 4 shows another embodiment of the present invention, in which numeral 8 denotes an n-type high concentration impurity region with a depth of 0.6 μm formed on the surface. Also, 9 is p-type highllI! This is a highly impurity region. This structure is a simple pn junction element, but the conventional lateral pn
Compared to a junction element, the reverse IJ current is significantly reduced.

FIG. 5 shows another embodiment of the present invention, in which a p-type high concentration impurity region 10 is formed in an n-type silicon substrate 1, and is connected to one electrode terminal 101. Furthermore, the silicon oxide film 2 on the silicon substrate is selectively removed, and the deposited polycrystalline silicon film 5v: single crystal l
It has a structure in which it is in direct contact with the O region. Besides,
Therefore, the crystallinity of polycrystalline silicon is improved, and the characteristics of the pn junction composed of 5 and 6 are improved. Therefore, the reverse leakage current of the pn junction is reduced.

FIG. 6 shows another embodiment of the present invention in which laser light 11 is irradiated to improve the crystallinity of polycrystalline silicon. The laser beam irradiation conditions were to keep the substrate at 500C;
A 4R laser with an output of aW and a beam diameter of 3011 m was used at a sweep speed of 8 oeIIv/s. the result,
A good pn junction was obtained and the leakage IIIL flow in the reverse direction was reduced.

#I7 is another embodiment of the present invention, and is a (ml cross-sectional structure diagram, (b) equivalent circuit diagram) when the polycrystalline semiconductor element DI is applied as a gate protection element of M08FETQ1.

Here, 1 to 7 are the same as those already explained,
12 is a p-type impurity region connected to the base of the MOSFET. 13° and 14 are MOSFETs, respectively.
drain region, drain/electrode. 15.16 is
AL and other terminals of gate protection element, each MOS
FET source 18. 17). 1
8 is a 1M08PET source region, which is an n-type highly concentrated impurity region. According to this structure, the polycrystalline silicon gate protection element has a pn junction in the depth direction, which increases current capacity and reduces reverse leakage current, resulting in good characteristics. ing. As a result, the area of the device according to the present invention to obtain the same level of gate protection effect is reduced to about 1/2 compared to the case where a conventional lateral pn junction device is used.

(6) Summary As explained above, according to the present invention, for example, a polycrystalline silicon pn junction element formed on an insulating film can have the features of large current capacity and small leakage current.

[Brief explanation of drawings]

Figure 1 is a sectional view showing the main parts of the conventional structure, Figures 2 to 6
The figure is a cross-sectional view showing the main structure of the present invention, and FIG. 7 is an explanatory diagram showing an application example of the present invention, which is a cross-sectional view and an equivalent circuit diagram of MC)8PET and a gate protection element. 1... Semiconductor metal integrated (Si etc.), 42... Insulating film (S
IO* etc.), 3, 4.6.7・n! 1A high concentration impurity doped region IA 1 Figure 3 Figure 4 Figure 5 Figure I! /71) Figure 6 η 7 Figure (α) Continuation of page 1 0 Author Mitsuo Ito 111 Nishiyokote-cho, Takasaki City, Hitachi, Ltd. Takasaki Factory 0 Author Okura Ri 1-280 Higashi Koigakubo, Kokubunji City Stock Company Hitachi, Ltd. Central Research Laboratory

Claims (1)

[Claims] 1. In a semiconductor layer having a pn junction formed on an insulating film on a semiconductor substrate, a pn junction provided in the semiconductor layer
A semiconductor device characterized by having a portion in which a junction is formed in the depth direction. 2. The semiconductor device according to claim 1, wherein the semiconductor layer having the pn junction is formed on the same substrate as the semiconductor element as a storage element of the semiconductor element. 3. The semiconductor device according to item 1 or 2, wherein the semiconductor layer is a polycrystalline semiconductor layer.