JPS627153A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a dynamic MOS.RAM memory cell having high yield by forming a word line of the first gate electrode layer, burying the second and third gate electrode layers in a deep hole to form a storage capacity, and forming a plate electrode of the third gate electrode layer. CONSTITUTION:A transfer transistor of dynamic memory cell is composed of the first gate electrode layer 15, and source and drain diffused layers 16, 17. The first gate electrode layers 15, 18 operate as word line of a memory cell. The second gate electrode 19 layer made of polycrystalline silicon is formed on the surface of a thin insulating film 14 in a deep hole 13, and the electrode of an insulating film capacity is formed of the film 14 to a silicon substrate 1. Further thin insulating film 20 is formed, and the third polycrystalline silicon layer 21 is formed thereon as a plates electrode. The storage capacity is formed of the first insulating film capacity between the substrate 1 and the layer 19, and the second insulating film capacity between the second electrode layer and the third electrode layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory, and more particularly to a memory cell of a dynamic MO3 random access memory (hereinafter referred to as dynamic MO5-RAM) that can be highly integrated.

[Background of the invention]

In the dynamic MO5-RAM, it is necessary to reduce the area of the memory cell in order to achieve high integration.

For this purpose, as shown in FIG. 2, IE has developed a method of forming a deep hole 2 in a silicon substrate 1 and forming a thin insulating film 3 therein to realize a large memory storage capacity.・IEEETransactions on Electron Devices
n Electron Devices ED-31,
Na6°, pp. 746-753, 1984. In this structure, the first layer of polycrystalline silicon 4 is also embedded in the deep hole 2, forming a capacitor electrode called a plate. Furthermore, the gate electrodes 5, 6 of the second layer form a word line in the memory cell. A memory cell having such a structure has the following drawbacks.

(1) In the storage capacitor section, charges are formed on the silicon substrate side of the deep hole, so if noise charges enter the memory cell section due to alpha rays, etc., they will easily mix with the stored charges and cause memory information to be lost. .

(2) Since the word lines 5 and 6 are formed on the thick oxide film 7 for isolation between elements and the first layer single crystal silicon 8, the word line 6 requires the most precise microfabrication. must be formed in areas with large base steps, making microfabrication difficult.

(3) Furthermore, as seen in the planar layout of the memory cell shown in FIG. , 9, the resistance increases and, in some cases, the wire becomes more likely to break.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a dynamic MO8RAM memory cell that can be highly integrated, has high reliability, and has a good manufacturing yield.

[Summary of the invention]

In the present invention, in order to achieve the above object, a word line is formed using the first layer gate electrode in order to reduce the step difference between the base layers,
A deep hole is formed in a silicon substrate.

Further, the gate electrodes of the second and third layers are buried in the deep holes to form a storage capacitor, and the stored charges are stored in the polycrystalline silicon instead of in the silicon substrate. Furthermore, the third
A plate electrode is formed by the gate electrodes in layers, so that a thin plate electrode portion is not formed.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using Examples.

Embodiment 1 A memory cell structure according to a first embodiment of the present invention is shown in FIG. 1 taking an n-channel type as an example. In the figure, a deep hole 13 with a depth of 1 to 6 μm is formed on the surface of a p-type silicon substrate 1. On the surface of the deep hole, a SiO□ film, a Si, N4 film, or a composite film 14 of these is formed with a thin film thickness of 5 to 50 nm.

The transfer transistor of the dynamic memory cell differs from the conventional example shown in FIG. 2 in that it is composed of a first layer gate electrode 15 made of polycrystalline silicon, silicide, or high melting point metal, and source/drain diffusion layers 16 and 17. ing. The gate electrodes 15 and 18 in the first layer function as word lines of memory cells. A second layer gate electrode 19 made of polycrystalline silicon is formed on the surface of the thin insulating film 14 in the deep hole 13, and constitutes an electrode for the insulating film capacitance between the thin insulating film 14 and the silicon substrate 1. ing.

Furthermore, on the surface of the second layer gate electrode, SiO□ and S
A thin insulating film 20 of I, N, etc. is formed, and a third layer of polycrystalline silicon 21 is formed thereon as a plate electrode. In a memory cell with such a configuration, the word line 15.18, which requires the most minute processing, is connected from the n0 diffusion layer 16 to the second layer through a transfer gate MOS transistor in the first layer memory cell structure with a small ground level difference.
Accumulated charges are stored in the gate electrode 19 of the second layer. Since there is no accumulated charge within the silicon substrate 1, it is resistant to external noise such as alpha rays. The storage capacitance is the first insulating film capacitance between the silicon substrate 1 and the second layer gate electrode 19, and the second insulating film capacitance between the second layer gate electrode and the third layer gate electrode. Since it consists of a capacitor, a larger storage capacitance than the conventional structure can be realized, and the accumulated signal charge can also be increased, thereby obtaining favorable characteristics. Furthermore, the fourth
As shown in the planar layout of the memory cell according to the present embodiment, the plate electrode 22 formed of the third layer of PolySi is almost entirely plate electrode except for the contact electrode 23 area. Since there is no narrow region as in the conventional example shown in FIG. 3, defects such as disconnection of the plate electrode do not occur, and a highly reliable memory cell can be constructed. In FIG. 4, 24 is a word line formed by the first layer gate electrode, 25 is an active region where a diffusion layer is formed, 26 is a deep hole region formed in the silicon substrate, and 27 is a word line formed by the second layer gate electrode. The gate electrode 28 is a data line made of aluminum or the like.

Embodiment 2 A second embodiment of the present invention is shown in FIG. 5. In this embodiment, a transfer gate MOS transistor is formed by the first layer gate electrode 31, and The structure of the memory cell in which a capacitance is formed by electrodes is the same as that of the embodiment shown in FIG. 1, except for the second layer.

In order to reduce the overlap capacitance between the gate electrode 31, 32 of the third layer and the gate electrode 30 of the first layer, the gate electrode 31, 32 of the second and third layers is connected to the gate electrode 30 of the first layer. 30
It is formed so that it does not overlap. FIG. 6 is a plan layout diagram of a memory cell corresponding to FIG. 5. In this layout diagram as well, the top layer plate electrode 22 runs horizontally with a large width.
A memory cell with such a structure does not have the narrow plate region seen in the conventional structure, and the capacitance of the word line is small, making it possible to increase the speed of the memory.

Embodiment 3 A third embodiment of the present invention is shown in FIG. The gate electrode 34 forming the capacitance by the lil film 14 is formed of the same first layer polycrystalline silicon or silicide layer as the gate electrode 1fA35 of the transfer gate MOS transistor. Therefore, in this embodiment, the gate electrode has a two-layer structure of 34 and 36, which can be manufactured with higher reliability than the three-layer structure of the previous embodiment.

Embodiment 4 This embodiment relates to a structure for preventing soft errors caused by alpha rays in a memory cell according to the present invention.

In FIG. 8, a P shadow region 40 having a medium concentration of 1016 to 1Qlffc13 is formed around a deep hole 13 formed in a P type silicon substrate 1. Since the spread of the depletion layer from the hole to the silicon substrate is suppressed, fewer electrons are generated in the depletion layer by alpha rays, which is effective in preventing soft errors.

FIG. 9 shows that a P shadow region 41 is formed only in the upper part of the deep hole 41, and the concentration is 1 to 2 orders of magnitude higher than that of the P-type silicon substrate (10" to 1017a@-"). This prevents electrons caused by alpha rays from diffusing into the high concentration V-shaped wave scattering layer 42 at the top of the deep hole.

Figure 10 shows 101' to 1017c13 in the middle region of the deep hole.
This is a structure in which a P shadow region 43 having an impurity concentration is formed, and such a P shadow region formed inside the silicon substrate can be realized by high energy ion implantation.

FIG. 11 shows that a P9 region 44 having a high impurity concentration of 1017 to 10"cm-3 is formed around the deep hole, and
The shadow region 45 has a relatively low impurity concentration of 1011 to 10'"am-" so as not to lower the junction breakdown voltage with the high concentration P shadow region 44.

FIG. 12 shows a structure in which a P shadow region 46 having a depth equal to or greater than the deep hole and having an impurity concentration of 101'' to 1017c13 is formed on the surface of a low concentration P type substrate. A potential barrier due to the difference in impurity concentration between the substrate 1 and the P-concentration substrate 1 contributes to preventing soft errors caused by alpha rays.

FIG. 13(A) has a depth of 1 to 2 μm on an n-type substrate 47, and an impurity concentration of 101s to 1017c+m-
A P-type well 46 (a) is formed, and a deep hole 13 is further formed so as to pass through this P-well. In this structure, most of the deep holes with a depth of 5 to 6 μm are in contact with the n-type substrate 47 to which the power supply voltage is applied, so the inside of the n-type substrate under the capacitive gate electrode 31 to which a positive voltage is applied is No depletion layer is formed in this structure, making it an optimal structure for preventing soft errors caused by alpha rays. Furthermore, Fig. 13 (
As shown in Fig. B), the peripheral circuit of the memory is composed of a P-well type complementary MO3 (hereinafter abbreviated as 0MO8), and the n-channel MOS transistor 49 is a P-well type complementary MO3 (hereinafter abbreviated as 0MO8).
A P channel MOS transistor 50 having a source and drain formed by a P0 diffusion layer 51 is formed in the well 46 in an n well 48 formed on the surface of an n type substrate 47 or a lightly doped n type substrate.

FIG. 14 shows 1018 to 10"6C13 with a thickness of 1 to 2 μm on a P0 type substrate 52 having a high impurity concentration.
A P-type epitaxial layer 53 having a concentration of ~1011c1'A is formed, and a deep hole 13 is formed so as to reach the P0 substrate. This is because in this structure, most of the surface of the deep hole is in contact with the P0 substrate 52.

The thickness of the depletion layer extending toward the P0 substrate side is extremely small, and is highly effective in preventing soft errors.

In addition, Fig. 1, Fig. 5, Fig. 7, Fig. 8, Fig. 9, Fig. 1
In the embodiments shown in FIGS. 0, 11, 12, and 14, a P-type substrate is used;
0M with P channel MOS range meta formed in the well
Preferably, the O8 structure is used.

Embodiment 5 In this embodiment, a typical manufacturing process for a memory cell structure according to the present invention will be described.

First, on the surface of the n-type substrate (or p-type substrate) 60, a depth of 1~
After forming an n-type well 61 and a p-type well 62 with an average impurity concentration of 1015 to 10110l71, a field oxide film 63 and a thin gate oxide film 64 of 5 to 50 nm are formed. The impurity concentration for the high breakdown voltage ratio of the first layer gate electrode 652M0S transistor made of polycrystalline silicon, silicide, or a composite film thereof is 1017 to i0"
c■-1 low concentration P type layer 67, n type layer 68. Furthermore, a SiO□ film 66 is formed to surround the gate electrode (FIG. 15A). Next, a depth of 1 to 6 μm is applied to the area where memory cells will be formed.
A deep hole 69 is formed in the silicon substrate 60 by dry etching (FIG. 15B). Next, an insulating film 70 is formed inside the deep hole, and then a part of the insulating film 70 on the silicon substrate surface is removed in order to bring the second layer gate electrode into contact with the silicon substrate surface (FIG. 15C). ) Next, a second layer gate electrode 72 made of polycrystalline silicon doped with a high concentration of n-type impurities is formed, and a layer of 5 to 50
A very thin insulating film 73 with a thickness of 10 nm thick and a third layer gate electrode 74 made of polycrystalline silicon are formed. In this step, n-type impurities are diffused into the silicon substrate from the portion of the second layer polycrystalline gate electrode that is in direct contact with the silicon substrate surface, and a high concentration n-type wave dispersion layer 15 is formed. After that, MOS transformer diagram D). Next, phosphor glass film (PSG) 7
8. First layer metal electrode 79, interelectrode interlayer insulating film 80 made of SiO□ or organic resin. A second layer metal electrode 812 surface protection film 82 is formed to configure a memory.

〔Effect of the invention〕

As described above, according to the present invention, (1) memory cells that can be highly integrated can be realized in a small area, (2) soft errors caused by alpha rays etc. can be prevented, and (3) microfabrication is possible with high manufacturing yield. A possible dynamic memory cell can be realized. It should be noted that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the spirit of the present invention.

For example, in the embodiment, an n-channel type memory cell is used as an example, but a p-channel type is also possible. Furthermore, in FIG. 14, it is also possible to use an epitaxial substrate in which a lightly doped n-type layer is formed on the surface of a highly doped n-type substrate as the n-type substrate.

[Brief explanation of drawings]

FIG. 2 is a diagram showing a cross-sectional structure of a conventional semiconductor device. Figure 1, Figure 5, Figure 7, Figure 8, Figure 9, Figure 10,
11, 12, 13, and 14 are diagrams showing cross-sectional structural diagrams of different embodiments of the present invention, FIG. 3 is a plan layout diagram of a conventional semiconductor device, and FIGS. 4 and 6. 15 is a plan layout diagram of an embodiment of the present invention, and FIG. 15 is a diagram showing an example of a manufacturing process of a semiconductor device according to the present invention. 1.47,52,60...Silicon substrate, 2,12°13.26,69...Deep hole, 3,14,20,63°66.70,73,78,80,82... Insulating film, 4
．． 5, 6, 15, 18, 19, 21, 27°30.31
．． 32, 35, 36, 65, 72° 74... Gate electrode, 16, 17, 45, 48° 61.68, 75, 77
... n-type impurity layer, 40°41.43,44,46,
53,62,67°76...P type impurity layer, 79.8
1...Metal electrode. 11.25... Diffusion layer region, 7, 22... Plate electrode, 10.24... Word line, 28... Data line, 23... Electrode hole, 8, 9... Plate electrode narrow area,.

Claims (1)

[Claims] 1. In a semiconductor memory configured with a dynamic memory cell consisting of an insulated gate field effect transistor and a charge storage capacitor provided on a semiconductor substrate, the insulated gate field effect transistor is The gate electrode is the first
The charge storage capacitor includes a deep hole formed in the semiconductor substrate, a first thin insulating film formed on the surface of the deep hole, and a first thin insulating film formed on the surface of the insulating film. is,
and a second gate electrode made of a second conductive layer directly in contact with the semiconductor substrate at the upper part of the deep hole, a second thin insulating film formed on the second gate electrode, and a second thin insulating film formed on the second gate electrode. A semiconductor memory comprising a third gate electrode formed of a third conductive layer formed on an insulating film. 2. The second gate electrode on the first thin insulating film formed on the surface of the deep hole is formed of the same conductive layer as the first conductive layer constituting the gate electrode of the insulated gate field effect transistor. A semiconductor memory according to claim 1, characterized in that: