JPH0810764B2 - Insulated gate type semiconductor device - Google Patents
Insulated gate type semiconductor deviceInfo
- Publication number
- JPH0810764B2 JPH0810764B2 JP63011190A JP1119088A JPH0810764B2 JP H0810764 B2 JPH0810764 B2 JP H0810764B2 JP 63011190 A JP63011190 A JP 63011190A JP 1119088 A JP1119088 A JP 1119088A JP H0810764 B2 JPH0810764 B2 JP H0810764B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- type
- conductivity
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 8
- 230000002265 prevention Effects 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ソース層とドレイン層の間のチャネル形成
半導体領域上に備えられるゲート電極とドレイン層の間
にサージ電圧に対する保護回路を内蔵した絶縁ゲート型
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention has a surge voltage protection circuit built in between a drain electrode and a gate electrode provided on a channel forming semiconductor region between a source layer and a drain layer. The present invention relates to an insulated gate semiconductor device.
第２図は従来の保護回路内蔵絶縁ゲート型半導体装置
を示し、ドレイン層となるＮ型半導体基板１にＰ型ベー
ス層２が形成され、その中に端部にチャネル領域４が残
るようにＮ型ソース層３が形成されている。チャネル領
域４の上にはゲート絶縁膜51を介してＮ型ポリシリコン
のゲート６が設けられ、ゲート６に絶縁膜52の開口部で
配線71が接触している。他の配線72はソース層３および
ベース層２に接触している。このMOSFETのゲート入力の
保護回路として、シリコン基板の中に形成されるＰ層21
およびそのＰ層21の中に形成され配線71に接触するＮ層
31の間に生ずるダイオードとＰ層21とＮ型基板１の間に
生ずるダイオードがゲート配線71とドレインとの間に逆
向きに直列接続されている。FIG. 2 shows a conventional insulated gate semiconductor device with a built-in protection circuit, in which a P-type base layer 2 is formed on an N-type semiconductor substrate 1 serving as a drain layer, and a channel region 4 is left at the end of the P-type base layer 2. The mold source layer 3 is formed. An N-type polysilicon gate 6 is provided on the channel region 4 via a gate insulating film 51, and a wiring 71 is in contact with the gate 6 at the opening of the insulating film 52. The other wiring 72 is in contact with the source layer 3 and the base layer 2. As a protection circuit for the gate input of this MOSFET, the P layer 21 formed in the silicon substrate
And an N layer formed in the P layer 21 and in contact with the wiring 71
The diode generated between 31 and the diode generated between the P layer 21 and the N-type substrate 1 are connected in series in the opposite direction between the gate wiring 71 and the drain.
しかしこのような内蔵保護回路ではＮ層31,P層21,N層
１がNPTトランジスタを形成するために、トランジスタ
動作させないためにはＰ層21とその中に形成されるＮ層
31によって作られるダイオードの伝導度変調による電流
増幅をなくす必要がある。そのためには、Ｐ層21,N層31
の不純物濃度の設定およびＰ層21,N層31によって形成さ
れる逆阻止電圧等に制約があるため、条件設定が複雑に
なる欠点があった。However, in such a built-in protection circuit, the N layer 31, the P layer 21, and the N layer 1 form an NPT transistor. Therefore, in order to prevent the transistor from operating, the P layer 21 and the N layer formed therein
It is necessary to eliminate the current amplification due to the conductivity modulation of the diode made by 31. For that purpose, P layer 21, N layer 31
Since there is a restriction on the setting of the impurity concentration and the reverse blocking voltage formed by the P layer 21 and the N layer 31, there is a drawback that the condition setting becomes complicated.
本発明の目的は、保護回路の内蔵によってトランジス
タが形成されることがなく、装置設計上の条件を容易に
設定できる絶縁ゲート型半導体装置を提供することにあ
る。An object of the present invention is to provide an insulated gate semiconductor device in which a transistor is not formed by incorporating a protection circuit and the device design conditions can be easily set.
本発明の絶縁ゲート型半導体装置は、基板上にゲート
絶縁膜を介してポリシリコンゲートを備え、基板内に第
一導電型のドレイン層とその中に設けられる第二導電型
のベース層と、該ベース層の中に設けられる第一導電型
のソース層とを備えるものにおいて、第一導電型のドレ
イン層とその中に設けられる第二導電型層とによって電
圧クランプダイオードを形成し、前記ゲート絶縁膜上の
ポリシリコンゲート層とその中に設けられる第二導電型
のポリシリコン層とによって逆流防止ダイオードを形成
し、前記第二導電型層と前記第二導電型のポリシリコン
層とを配線で接続し、逆向きに直列接続される前記電圧
クランプダイオードと前記逆流防止ダイオードよりなる
保護回路をゲート端子とドレイン端子の間に有するもの
とする。The insulated gate semiconductor device of the present invention comprises a polysilicon gate on a substrate via a gate insulating film, a first conductivity type drain layer in the substrate, and a second conductivity type base layer provided therein, A source layer of the first conductivity type provided in the base layer, wherein a voltage clamp diode is formed by a drain layer of the first conductivity type and a layer of the second conductivity type provided therein; A backflow prevention diode is formed by the polysilicon gate layer on the insulating film and the second conductivity type polysilicon layer provided therein, and the second conductivity type layer and the second conductivity type polysilicon layer are wired. And a protection circuit composed of the voltage clamp diode and the backflow prevention diode connected in series in the opposite direction is provided between the gate terminal and the drain terminal.
このような絶縁ゲート型半導体装置の保護回路は半導
体素体中に形成される電圧クランプダイオードと逆向き
に直列接続される絶縁膜上のゲートとしての多結晶シリ
コン層内に形成される逆流防止ダイオードからなるた
め、保護回路のために半導体素体内にトランジスタが形
成されることがない。A protection circuit for such an insulated gate semiconductor device is a reverse current prevention diode formed in a polycrystalline silicon layer as a gate on an insulating film connected in series in the opposite direction to a voltage clamp diode formed in a semiconductor element body. Therefore, no transistor is formed in the semiconductor body for the protection circuit.
第１図は本発明の一実施例を示し、第２図と共通の部
分には同一の符号が付されている。第２図と異なりＮ型
シリコン基板１内に形成されるＰ層21内にはＮ層がな
く、ゲート絶縁膜51の上のゲート６のＮ型ポリシリコン
層の中にそれより低不純物濃度で高抵抗のＰ型ポリシリ
コン層８が形成されている。ポリシリコン層８はチャネ
ル領域４の上をはずれた部分に形成され、配線71に接続
されている。この構成においてＮ層１とＰ層21によって
作られるダイオードがゲートに入力される負のサージ電
圧によりブレイクダウンした場合、そのブレイクダウン
電流は、配線71,P型ポリシリコン層８を抜けてゲート絶
縁膜51の上のＮ型ゲート６を介して流れる。これは、等
価回路図の第３図においてMOSFET10のドレイン端子Ｄか
らＮ層１とＰ層21により形成される電圧クランプダイオ
ード20,PNポリシリコン層8,6によって形成されるダイオ
ード30を介して図示されない配線を通ってゲート端子Ｇ
に流れることを意味する。MOSFET10を導通させるために
ゲート６に正の電圧が印加されるときには、ダイオード
30は逆流防止ダイオードとして働くように耐圧20V程度
に作成される。FIG. 1 shows an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. Unlike in FIG. 2, there is no N layer in the P layer 21 formed in the N type silicon substrate 1, and the N type polysilicon layer of the gate 6 on the gate insulating film 51 has a lower impurity concentration than that. A high resistance P-type polysilicon layer 8 is formed. The polysilicon layer 8 is formed in a portion off the channel region 4 and is connected to the wiring 71. In this configuration, when the diode formed by the N layer 1 and the P layer 21 breaks down due to the negative surge voltage input to the gate, the breakdown current passes through the wiring 71 and the P-type polysilicon layer 8 to insulate the gate. Flow through the N-type gate 6 above the membrane 51. This is illustrated in FIG. 3 of the equivalent circuit diagram via the drain terminal D of the MOSFET 10 through the voltage clamp diode 20 formed by the N layer 1 and the P layer 21 and the diode 30 formed by the PN polysilicon layers 8 and 6. Gate terminal G through the wiring not
Means to flow to. When a positive voltage is applied to gate 6 to turn on MOSFET 10, the diode
30 is made with a withstand voltage of about 20 V so as to function as a backflow prevention diode.
本発明によれば、保護回路を半導体素体内に形成され
る電圧クランプダイオードとポリシリコンゲート内に形
成される逆流防止ダイオードによって構成することによ
り、保護ダイオード形成のためにトランジスタ構造が半
導体素体に生ずることがないので、容易に製造プロセス
条件が設定できる絶縁ゲート型半導体装置が得られる。According to the present invention, the protection circuit is configured by the voltage clamp diode formed in the semiconductor element body and the backflow prevention diode formed in the polysilicon gate, so that the transistor structure is formed in the semiconductor element body for forming the protection diode. Since it does not occur, an insulated gate semiconductor device in which the manufacturing process conditions can be easily set can be obtained.
第１図は本発明の一実施例の断面図、第２図は従来の保
護回路内蔵絶縁ゲート型半導体装置の断面図、第３図は
第１図の半導体装置の等価回路図である。 1:シリコン基板、2:P型ベース層、21:ダイオードＰ層、
3:N型ソース層、4:チャネル領域、51:ゲート絶縁膜、6:
N型ポリシリコンゲート、71,72:配線、8:P型ポリシリコ
ン層。FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of a conventional insulated gate type semiconductor device having a protection circuit, and FIG. 3 is an equivalent circuit diagram of the semiconductor device of FIG. 1: Silicon substrate, 2: P type base layer, 21: Diode P layer,
3: N-type source layer, 4: Channel region, 51: Gate insulating film, 6:
N-type polysilicon gate, 71, 72: wiring, 8: P-type polysilicon layer.
Claims (1)
ンゲートを備え、基板内に第一導電型のドレイン層とそ
の中に設けられる第二導電型のベース層と、該ベース層
の中に設けられる第一導電型のソース層とを備えるもの
において、第一導電型のドレイン層とその中に設けられ
る第二導電型層とによって電圧クランプダイオードを形
成し、前記ゲート絶縁膜上のポリシリコンゲート層とそ
の中に設けられる第二導電型のポリシリコン層とによっ
て逆流防止ダイオードを形成し、前記第二導電型層と前
記第二導電型のポリシリコン層とを配線で接続し、逆向
きに直列接続される前記電圧クランプダイオードと前記
逆流防止ダイオードよりなる保護回路をゲート端子とド
レイン端子の間に有することを特徴とする絶縁ゲート型
半導体装置。1. A first conductive type drain layer, a second conductive type base layer provided therein, and a base layer of the base layer, the polysilicon layer having a polysilicon gate on a substrate via a gate insulating film. A source layer of the first conductivity type provided on the gate insulating film, a voltage clamp diode is formed by the drain layer of the first conductivity type and the second conductivity type layer provided therein. A backflow prevention diode is formed by the silicon gate layer and the second-conductivity-type polysilicon layer provided therein, and the second-conductivity-type layer and the second-conductivity-type polysilicon layer are connected by a wiring. An insulated gate semiconductor device, comprising a protection circuit composed of the voltage clamp diode and the backflow prevention diode connected in series in a direction between a gate terminal and a drain terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63011190A JPH0810764B2 (en) | 1988-01-21 | 1988-01-21 | Insulated gate type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63011190A JPH0810764B2 (en) | 1988-01-21 | 1988-01-21 | Insulated gate type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01185971A JPH01185971A (en) | 1989-07-25 |
| JPH0810764B2 true JPH0810764B2 (en) | 1996-01-31 |
Family
ID=11771144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63011190A Expired - Lifetime JPH0810764B2 (en) | 1988-01-21 | 1988-01-21 | Insulated gate type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810764B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035641A (en) * | 2011-09-29 | 2013-04-10 | 株式会社东芝 | Semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2692350B2 (en) * | 1990-04-02 | 1997-12-17 | 富士電機株式会社 | MOS type semiconductor device |
| JP2701758B2 (en) * | 1994-10-14 | 1998-01-21 | 日本電気株式会社 | Semiconductor device |
| JP4844007B2 (en) * | 2005-05-18 | 2011-12-21 | 富士電機株式会社 | Composite type semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58151051A (en) * | 1982-03-03 | 1983-09-08 | Hitachi Ltd | Semiconductor device |
-
1988
- 1988-01-21 JP JP63011190A patent/JPH0810764B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035641A (en) * | 2011-09-29 | 2013-04-10 | 株式会社东芝 | Semiconductor device |
| CN103035641B (en) * | 2011-09-29 | 2015-11-11 | 株式会社东芝 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01185971A (en) | 1989-07-25 |
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