JP2523466Y2 - Transistor - Google Patents

Description

The present invention relates to a transistor, and more particularly, to a structure in which a bipolar transistor and a field-effect transistor are combined.

Description of the Related Art Conventionally, transistors of this type, as shown in FIG. 3 (a), the P ⁺ -type anti conductor substrate 11 serving as the emitter of the bipolar transistor Q ₀ in an equivalent circuit diagram of FIG. 3 (b) An N ⁻ -type epitaxial layer 12 serving as a base of the bipolar transistor Q ₀ and a drain of the field-effect transistor Q ₁ is grown, and a bipolar transistor is formed on the epitaxial layer 12.
Q Select diffusing P-type high-concentration impurity serving as the collector lead-out layer of the bipolar transistor in the center of the collector region 13 a P-type impurity serving as the collector and the field effect transistor to Q ₁ back gate formed by selective diffusion of ₀ To form the collector extraction layer 14,
N-type high-concentration impurity is selectively diffused so as to surround the collector extraction layer 14 and the source extraction layer 14 and the source region.
Reference numeral 15 is short-circuited by wiring 16.

Furthermore, the drain region 12 of the field effect transistor Q _1,
A gate electrode 18 is formed on a surface of a bipolar collector region 13 between source regions 15 with an oxide film 17 interposed therebetween.

FIG. 3 (b) is an equivalent circuit diagram of the transistor.
The operation will be described with reference to FIG.

As you increase the voltage of the gate G to the collector C, first field effect transistor Q ₁ is turned, a base of the bipolar transistor Q _0, current flows through the region 12 is the drain of the field effect transistor Q _1, a bipolar transistor Q ₀ is to conduct.

Problems to be solved by the invention By the way, in the above-mentioned conventional transistor IGBT,
Since a Darlington structure in which the main transistor and the bipolar transistor Q ₀ initial stage transistor and a field effect transistor Q _1, even when the saturation of the main transistor, 0.
It had the disadvantage that a saturation voltage of 7-1 V remained.

Means for Solving the Problems The present invention provides a back-gate region formed by selectively diffusing an impurity of another conductivity type into a semiconductor substrate serving as a drain region base of a field-effect transistor, and an impurity of one conductivity type in a central portion thereof. Is selectively diffused to form a source region,
In the case where a gate electrode is formed on the surface of the back gate region between the drain and source regions via an oxide film, the back gate region and the source region are connected via a resistor, and the back gate region and the gate electrode are connected via a resistor. It is characterized by doing.

According to the above configuration, in a region where a gate voltage is applied where the field effect transistor does not conduct, a bipolar transistor having a source region as an emitter, a back gate region as a base, and a drain region as a collector conducts. In a region where a gate voltage at which the transistor conducts is applied, the bipolar transistor and the field-effect transistor conduct in parallel, so that the saturation voltage can be reduced.

Embodiment FIGS. 1A and 1B show a first embodiment of the present invention.
This will be described with reference to FIG. FIG. 1A shows a cross-sectional structure thereof, and FIG. 1B shows an equivalent circuit diagram thereof.

In FIG. 1 (a), 2 is a bipolar transistor
Region forming a collector and drain of the field effect transistor to Q ₁ Q _0, regions to be each of the base and back gates 3, regions to be each emitter and source of 5, 7 oxide film, 8 denotes a gate electrode, 9 is the transistor Q ₀
Is a region where a base resistance is formed.

The region 2 serving as the collector and the drain is an N ⁻ type semiconductor substrate, and an N ⁺ type semiconductor layer 10 for taking out an external electrode is formed on the back surface thereof. Base and region 3 serving as the back gate, P in the region 2 serving as the collector and drain ^-
It is formed by selectively diffusing a mold impurity.

The region 5 serving as the emitter and the source is formed by selectively diffusing an N ⁺ -type impurity substantially at the center of the region 3 serving as the gate and the back gate. An impurity of the same type is selectively diffused in a band shape from a part of the region 3 serving as a base and a back gate to form a base resistance region 9.

A gate oxide film 7 is formed on the entire periphery of the base 3 and the back gate region 3 between the region 2 serving as the collector and the drain and the region 5 serving as the emitter and the source, or on the surface excluding the extension of the base resistance region 9. , A gate electrode 8 is formed.

Further, the gate electrode 8 has a structure in which the gate electrode 8 is connected via a high-concentration P-type layer (not shown) at an extended end of the base resistance region 9.

Based on the above configuration, the operation of the present invention will be described below with reference to the equivalent circuit diagram of FIG.

First, a positive control voltage is applied to the gate electrode G with respect to the emitter electrode E, and the voltage is gradually increased. When the voltage reaches V _BE of the bipolar transistor Q _0, a base current flows through the base resistor R. , the transistor Q ₀ is turned on.

Furthermore, when the voltage is increased, the field effect transistor
Q reached _one of the ON voltage V _T, tailored to the conduction of the bipolar transistor Q _0, the field effect transistor Q ₁ becomes conductive in parallel.

In the equivalent circuit diagram of FIG. 1B, a second resistor R 'may be connected between the back gate and the source region as shown by a dotted line in the figure. With such a configuration,
Bipolar transistor Q ₀ and field-effect transistor
Can change the gate voltage and the timing Q ₁ is turned and the resistance R 'acts as a discharge resistor of the charge stored in the conduction time of the base of the bipolar transistor Q _0, the advantage of improving the switching speed.

Embodiment 2 FIG. 2 is a sectional view of an element showing a second embodiment of the present invention, and the equivalent circuit is the same as FIG. 1 (b).

In this embodiment, a band-shaped base resistance layer 11 made of polysilicon is formed on the element surface via an oxide film 7 instead of the semiconductor resistance due to diffusion of the base resistance region 9.

To achieve the above-described configuration, in this embodiment the base and the field-effect transistor to Q ₁ bipolar transistor Q ₀
A high-concentration P-type impurity for achieving ohmic contact of the wiring to the base resistance layer 11 is selectively diffused in the center of the region 3 serving as the back gate, thereby forming the base extraction layer 4 and surrounding the bipolar transistor. select diffused high-concentration N-type impurity serving as the emitter and source of the field effect transistor to Q ₁ Q _0, since the addition forming the emitter and source regions 5, it is the same as the first embodiment, The following description is omitted.

Effect of the Invention As described above, in the transistor based on the invention, the bipolar transistor and the field-effect transistor operate in parallel, so that not only does the on-resistance decrease, the saturation voltage decreases, but also the on-voltage increases the V _{BE of the} bipolar transistor. , The rising response is faster than that of a field effect transistor.

Furthermore, in the case of the conventional field-effect transistor, the main channel of the current is the horizontal channel generated in the inversion layer immediately below the gate on the surface of the pellet, but according to the present invention, the bipolar transistor operates in parallel and the vertical Since the current also flows in the direction, the current driving capability per unit area of the pellet is increased, which is also effective in reducing the size of the pellet.

[Brief description of the drawings]

1A and 1B show a first embodiment of the present invention, wherein FIG. 1A is a sectional view of the device, and FIG. 1B is an equivalent circuit. FIG. 2 is a sectional view of an element according to the second embodiment. FIG. 3 shows a conventional element cross-sectional view (a) and an equivalent circuit diagram (b). 2 ... N ^- type semiconductor substrate (collector / drain region), 3
... P ^- type (base / back gate) region, 4... P ⁺ type base extraction region, 5... N ⁺ type (emitter / source) region, 7... Gate oxide film, 8. ... Base resistance region, 10 N ⁺ type semiconductor layer, 11 Base resistance layer, R Base resistance, R ′ Second resistance.

Claims (1)

(57) [Scope of request for utility model registration] A back gate region of another conductivity type selectively formed on a semiconductor substrate of one conductivity type serving as a drain region; a source region of one conductivity type selectively formed at a central portion of the back gate region; In a transistor having a gate electrode formed on the surface of the back gate region between the drain and source regions via an oxide film, the back gate region and the gate electrode are connected via a resistor, and the back gate region and the source region are connected. Are connected via a second resistor.