JP3161092B2 - Dual gate MOS thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-gate MOS thyristor which operates as a thyristor during normal operation and operates as an IGBT (conductivity modulation type MOSFET) at turn-off.

[0002]

2. Description of the Related Art Conventionally, MOSFETs, IGBTs and MCTs have been used as MOS gate type power semiconductor elements.
(MOS control thyristors) have been proposed.
Among them, in switching of relatively large current capacity,
IGBTs and MCTs with low on-voltage are the mainstays. Especially IG
In recent years, BT has undergone remarkable technological innovation, and has been put into practical use as a product due to progress in lowering on-voltage and lowering switching loss.

The IGBT has a structure similar to that of a power MOSFET, but has a characteristic of low on-voltage because it is an element using conductivity modulation. FIG. 2 shows a typical structure thereof. In the figure, ap ⁺ layer 21 serving as a drain region is shown.
And an n ⁺ buffer layer 22 formed on one side thereof, an n ⁻ layer 23 formed on the upper side thereof, and a polycrystalline silicon gate electrode 27 formed on a silicon oxide film 26 on the surface thereof as a mask. A p-type channel region 24 diffused and formed, and an n ⁺ region 25 serving as a source region of the surface layer. In this element, a voltage is applied between the source electrode 11 that is in common contact with the p region 24 and the n ⁺ region 25 and the drain electrode 12 that is in contact with the entire p ⁺ region 21, and the source electrode
Given a positive potential with respect to 11, since the region 28 immediately below the gate through the gate oxide film 26 operates as an inverted channel, n ⁺ source region 25 from the source electrode 21, the channel 51
, Electrons flow into n ⁻ layer 3. In response to this, holes are injected from the drain side p ⁺ layer 21, so that the n ⁻ layer
In the region 23, so-called conductivity modulation in which both electrons and holes are present occurs. As a result, the GBT can realize a low on-voltage.

[0004] In the IGBT, although the on-state voltage has been reduced, the limit for further reducing the on-state voltage is beginning to be seen. As is easily understood from the basic structure of the IGBT, the IGBT takes a form in which the base current of the built-in npn transistor is supplied by the MOSFET. For this reason, the IGBT cannot not only reduce the ON voltage of the transistor but also the MOSF.
An increase in the on-state voltage due to the JFET effect, which is a problem in ET, cannot be ignored. As described above, the IGBT has a great merit that it can be turned on and off by the MOS gate, but there is a limit in reducing the on-voltage because it involves the above-described fundamental problem.

The on-state voltage can be further reduced by forming the element in a thyristor structure. However, current thyristors are current driven and difficult to use. Also, it is difficult to use because turn-off is not easy. The DU proposed by the present inventors as an element which solves all these problems, realizes a low on-voltage, and can be driven by a MOS gate.
GMOT (Dual Gate MOS Thyristor) is a paper of the National Meeting of the Institute of Electrical Engineers of 1992 (March 1992) 5-7
Is known.

FIG. 3 shows a cross-sectional structure thereof, in which ap ⁺ layer 1 and an n ⁻ layer 3 laminated thereon with an n ⁺ buffer layer 2 interposed therebetween.
The p ⁺ region 4 selectively formed on the surface layer of the n ⁻ layer 3 and the n ⁺ region 5 selectively formed on the surface layer are respectively composed of the p emitter, n base, p base, and n base of the thyristor.
A four-layer structure of the emitter is formed. And the p region 4
Between the exposed portion of n ⁻ layer 3 and n ⁺ region 5
A gate insulating film 6 on the surface to form an n-channel
Gate electrode 7 connected to gate terminal G ₁ via
Is provided. The source electrode 11 connected to the source terminal S is in contact with the n ⁺ region 5. On the other hand, p region 31 is selectively formed separately on the surface layer of n ⁻ layer 3. N ⁺ region 32 selectively formed on the surface layer of p region 31;
33 is the drain and source, and the part between them is 52
Was a channel portion, MOSFET made by providing the second gate electrode 37 connected to the gate terminal G ₂ via the gate insulating film 36 is formed thereon exist. And n ⁺
The electrode 34 in contact with the drain region 32 is connected to the electrode 13 in contact with the p ⁺ contact region 8 selectively formed in the surface layer of the p region 4 by the wiring 10, and the p in the surface layer of the p region 31 is formed. ^The electrode 35 that is in common contact with the ⁺ region 38 and the n ⁺ source region 33 is connected to the source electrode 11 that is in contact with the n ⁺ region 5 by the wiring 20. The drain electrode 12 is in contact with the p ⁺ layer 1 on the back side.

FIG. 4 shows an equivalent circuit of the DUGMOT. A pnp transistor 41 is composed of a p ⁺ layer 1 and an n ⁺ layer 2 and an n ⁻ layer 3 and a p region 4.
The npn transistor 42 is composed of the n ⁺ layer 2 and the n ⁻ layer 3 and the p ⁺
A transistor composed of a region 4 and an n ⁺ region 5
The base of 41 is connected to the collector of transistor 42 to form a thyristor. A MOS composed of the n ⁺ region 5, the p region 4, the n ⁻ layer 3 and the first gate electrode 7 formed on the region 51 via the gate insulating film 6
The FET 43 has the first gate electrode 7 with respect to the source electrode 6.
For example, it is turned on by biasing positively at 15 V, and n ⁺
Electrons from the source region 5 flow into the n ⁻ layer 3 via the channel formed in the region 51, and holes are formed in the p ⁺ layer 1.
Is injected into the n ⁻ layer 3 and flows into the n ⁺ region 5 via the p region 4 to turn on the thyristor. On the other hand, the above n ⁺ drain region 32, p region 31, n
⁺ The drain of the MOSFET 44 constituted by the source region 33 and the second gate electrode 37 is an npn transistor
42 is connected to the base of the thyristor, that is, the p base of the thyristor, and the source is connected to the S terminal. This DUGMOT
Performs a thyristor operation in the on state, and cannot be turned off with the thyristor as it is. Therefore, shortly before the turn-off, for example, 5 μsec before, the IGBT operation is performed once. To transition from the thyristor operation to IGBT operation, forward bias to the second gate terminal G _2. As a result, the MOSFET 44 is turned on, and the hole current that has flowed into the n ⁺ source region 5 until then flows from the electrode 35 to the S terminal through this MOSFET. As a result, the base current of the thyristor is drawn, and the emitter-base junction of the thyristor recovers. At this stage, the device is in the same operation mode as the IGBT. That is, the electron current flows out of the channel portion 51, and the holes coming in from the drain layer 1 flow only in the p region 4. When stopping the voltage application at this stage to the first gate terminal G _1, the entire device is turned off. FIG. 5 shows a time chart of the voltages applied to G ₁ and G ₂ . The G ₁ As is apparent from FIG. 5 by positive bias, it starts thyristor operation, G before the turn-off
₂ is forward biased to shift from thyristor operation to IGBT operation. Thereafter, by turning off the G _1, the present device is turned off.

[0008]

However, in the DUGMOT shown in FIG. 3, it is necessary to form a region 31 in addition to the thyristor portion, and furthermore, since n ⁺ layers 32 and 33 are formed in the region, a parasitic region is formed. A thyristor is generated, and when the thyristor is turned on, the original thyristor operation may be hindered.

An object of the present invention is to solve the above-mentioned problems and to provide a dual-gate MOS thyristor in which the equivalent circuit shown in FIG. 4 is formed by eliminating a parasitic effect on a semiconductor substrate.

[0010]

In order to achieve the above object, the first conductive type emitter layer, the second conductive type base layer, the first conductive type base layer, and the second conductive type emitter layer are provided. A first gate electrode is provided on a first conductivity type base layer exposed surface on a semiconductor substrate having a thyristor structure, with a first gate insulating film interposed therebetween, and the semiconductor layer is formed using the semiconductor layer with the semiconductor substrate and the insulating film interposed therebetween. A MOS field effect transistor having a second gate electrode provided on the layer with a second gate insulating film interposed therebetween, wherein the drain region of the MOS field effect transistor has a first conductivity type base layer of the thyristor structure and a source region. It is assumed that the thyristor structure is electrically connected to the second conductivity type emitter layer with low resistance. It is effective that the semiconductor layer of the MOSFET includes a channel forming region and a source region and a drain region which sandwich the region and have different conductivity types from the region. It is effective that the semiconductor layer is made of polycrystalline silicon. Further, an electrode that makes ohmic contact with the drain region of the MOSFET is connected to an electrode that makes ohmic contact with the first conductivity type base layer of the thyristor structure via a wiring, and an electrode that makes ohmic contact with the source region is the second electrode of the thyristor structure. It is effective that the conductive type emitter layer is connected to an electrode in ohmic contact via a wiring.

[0011]

By forming a MOSFET for short-circuiting the emitter layer and the base layer having a four-layer structure not in the substrate but in the semiconductor layer formed via the substrate and the insulating film, a parasitic element which hinders the thyristor operation inherent to the element is formed. No effect.

[0012]

FIG. 1 shows an embodiment of a dual gate MOS thyristor according to the present invention, in which parts common to those in FIGS. This element is also the equivalent circuit diagram is the same as FIG. 4, MOSFET 44 in Fig. 4 p ⁺ layer 1, n ⁺ layer 2, n
^- is formed by a layer 3, p region 4, n ⁺ SOI on a silicon substrate formed of a pnpn structure consisting region 5.
That is, the polycrystalline silicon layer deposited on the n ⁻ layer 3 via the oxide film 9 is doped with impurities, and the polycrystalline silicon layer having a resistivity of about 0.1 Ωcm is sandwiched by a p-type channel formation region 14 of about several Ωcm. Resistive p ⁺ drain region 15 and p ⁺ source region 16
Is formed. Then, the second gate electrode 18 made of polycrystalline silicon having a resistivity of about several Ωcm is provided on the surface of the p region 14 via the gate oxide film 17, whereby the MOSFET 44 of FIG. 4 is completed. Further, FIG.
Similarly to the above case, the drain electrode 34 on the drain region is connected to the electrode 13 and the wiring 10 connects the source electrode 35 on the source region to the electrode 11 and the wiring 20. The driving of this element is performed according to the time chart of FIG. 5 similarly to the conventional DUGMOT, and a voltage is applied to the second gate electrode 18 to drive the MO of FIG.
By turning on the SFET 44, the n ⁺ region 5 and the p ⁺
Area 8 is electrically short-circuited, and
The operation can be shifted to the T operation.

[0013]

According to the present invention, in the ON state, the thyristor operation is performed to reduce the ON voltage, and for the turn-off, the DUGMOT that switches at a high speed by converting to the IGBT operation immediately before is used. MOSFET
Is formed in an SOI structure, there is no parasitic effect as in the case where it is formed inside a semiconductor substrate, and the degree of freedom for element design is increased. Furthermore, this SOI structure MOSF
Since the ET can be made by using the polycrystalline silicon layer forming technology used for forming the thyristor portion, there is also an advantage that there is no problem in the manufacturing technology.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a dual-gate MOS thyristor according to one embodiment of the present invention.

FIG. 2 is a sectional view of an IGBT.

FIG. 3 is a sectional view of a conventional dual-gate MOS thyristor;

FIG. 4 is an equivalent circuit diagram of the device shown in FIGS. 1 and 3;

FIG. 5 is a time chart of a gate voltage of the device shown in FIGS. 1 and 3;

[Explanation of symbols]

Reference Signs List 1 p ⁺ layer (p emitter layer) 2 n ⁺ buffer layer (n base layer) 3 n ⁻ layer (n base layer) 4 p region (p base layer) 5 n ⁺ region (n emitter layer) 6 gate insulating film 7 First gate electrode 8 p ⁺ contact region 9 oxide film 10 wiring 11 source electrode 12 drain electrode 14 channel formation region 15 n ⁺ drain region 16 n ⁺ source region 17 gate oxide film 18 second gate electrode 20 wiring

Continuation of front page (56) References JP-A-5-335554 (JP, A) JP-A-5-326936 (JP, A) JP-A-5-315619 (JP, A) JP-A-5-235363 (JP) JP-A-4-18763 (JP, A) JP-A-3-148872 (JP, A) JP-A-3-145163 (JP, A) JP-A-3-136371 (JP, A) 1-181571 (JP, A) JP-A-63-288064 (JP, A) JP-A-57-78225 (JP, A) Proceedings of the National Meeting of the Institute of Electrical Engineers of Japan in 1992. 5, p. 5.7 (1992) [Dual gate MOS gate thyristor [DUGMOT]] (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/749

Claims (4)

(57) [Claims] 1. A first conductivity type on a semiconductor substrate having a thyristor structure including a first conductivity type emitter layer, a second conductivity type base layer, a first conductivity type base layer, and a second conductivity type emitter layer. is first gate electrode provided via a first gate insulating film on the base layer exposed surface, a semiconductor layer over the semiconductor substrate and the insulating film, the second through the second gate insulating film on said semiconductor layer A MOS field effect transistor provided with a gate electrode, wherein a drain region of the MOS field effect transistor is electrically connected to the first conductive type base layer of the thyristor structure, and a source region is electrically connected to the second conductive type emitter layer of the thyristor structure. A dual-gate MOS thyristor, characterized in that the thyristor is connected to a low resistance. 2. The dual gate MOS thyristor according to claim 1, wherein the semiconductor layer of the MOS field effect transistor comprises a channel forming region, and a source region and a drain region sandwiching the region and having different conductivity types from the region. 3. The dual gate MOS thyristor according to claim 2, wherein the semiconductor layer is made of polycrystalline silicon. 4. An electrode in ohmic contact with a drain region of a MOS field effect transistor is connected to an electrode in ohmic contact with a first conductivity type base layer of a thyristor structure via a wiring, and an electrode in ohmic contact with a source region. 4. The dual-gate MOS thyristor according to claim 1, wherein said transistor is connected via an interconnect to an electrode in ohmic contact with the emitter layer of the second conductivity type having a thyristor structure.