JP3183037B2 - Insulated gate bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (hereinafter, referred to as an IGBT) having a gate of a MOS structure and used as a voltage-driven switching element.

[0002]

2. Description of the Related Art Recently, MOSFETs using conductivity modulation, so-called IGBTs, have attracted attention as switching elements. This IGBT has a high input impedance like a MOSFET, and can have a low on-resistance like a bipolar transistor. Taking advantage of these advantages, IGBTs have been applied to driving of variable speed motors and horizontal deflection of television receivers in place of conventional bipolar transistors. I have. The switching semiconductor element is
Ideally, the total loss including the steady loss and the switching loss is small. However, since the switching loss is proportional to the switching frequency, the higher the frequency is, the more the heat generation of the element increases, and the safe operation area of the element itself narrows.

FIG. 4 is a sectional view of the basic structure of an IGBT. The figure shows a unit part (hereinafter referred to as a cell) including one control electrode, and an active region that performs a switching operation of conducting and blocking the main current of the IGBT includes an extremely large number of such cells. Consists of The IGBT has
In addition to such an active region, there is a withstand voltage structure that shares the withstand voltage at a peripheral portion surrounding the active region, but is omitted because it does not relate to the essence of the present invention. In the figure, p ⁺ substrate 1
There is an n base layer 3 laminated via an n ⁺ buffer layer 2 above, and a p base region 4 is selectively formed on the surface layer of the n base layer 3. An n ⁺ emitter region 5 is selectively formed in p base region 4, and p ⁺ base region 4 is formed.
A gate electrode 7 made of polycrystalline silicon and connected to a G terminal via a gate oxide film 6 is provided on the surface of a channel region 11 sandwiched between n base layer 3 and n ⁺ emitter region 5. I have. On the surfaces of the n ⁺ emitter region 5 and the p base region 4, an emitter electrode that is in common contact with both regions and is connected to the E terminal, and the back surface of the p ⁺ substrate 1 is connected to the C terminal Collector electrodes 8 are provided. In the figure, the insulating film 10 is formed on the gate electrode 7.
, The emitter electrode 9 is extended.

[0004] The n base layer 3 of such an IGBT has a
It is formed by epitaxial growth on a substrate comprising a ⁺ substrate 1 and an n ⁺ buffer layer 2 laminated thereon. The p base region 4 is formed by introducing impurities using the gate electrode 7 formed earlier as a mask, and the n ⁺ emitter region 5 is formed by introducing impurities using a photoresist (not shown) as a mask. You.

The switching operation of the IGBT is performed as follows. When a voltage equal to or higher than the threshold value is applied to the gate electrode 7 while a positive voltage is applied to the C terminal and the E terminal, a channel is formed in the channel region 11 on the surface of the p base region 4 immediately below the gate electrode 7. Then, electrons are injected into n base layer 3 from n ⁺ emitter region 5 through the channel. Since the junction between the n ⁺ buffer layer 2 and the p ⁺ substrate 1 is forward-biased, the electron current injected into the n base layer 3 passes through the n ⁺ buffer layer 2 and passes through the junction. And flows into the p ⁺ substrate 1. Then, holes are injected from p ⁺ substrate 1 into n ⁺ buffer layer 2 and n base layer 3, and as a result, conductivity modulation occurs in n ⁺ buffer layer 2 and stn base layer 3. That is, p ⁺
A pn having a substrate 1, an n ⁺ buffer layer 2, an n base layer 3, and a p base region 4 as an emitter, a base, and a collector, respectively.
The p-transistor operates, and the hole current injected into the n-base layer 3 enters the p-base region 4, flows just below the n ⁺ emitter region 5, passes through the emitter electrode 9, and turns on the IGBT. To turn off the IGBT, if the voltage of the gate electrode 7 is removed, the emitter electrode 9 short-circuits the p base region 4 and the n ⁺ emitter region 5, so that the p base region 4 immediately below the gate electrode 7 The channel formed on the surface disappears, injection of electrons from the n ⁺ emitter region 5 stops, and the p ⁺ substrate 1, the n ⁺ buffer layer 2, the n base layer 3, the p base region 4, and the n ⁺ emitter region The operation of the four-layer thyristor composed of 5 is prevented, and the element can be turned off.

[0006]

In such an IGBT, electrons are swept out to the collector electrode 8 side by a depletion layer formed on both sides of the junction between the n base layer 3 and the p base region 4 at the time of turn-off. Then, holes are swept out to the emitter electrode 9 side. When this hole current flows in p base region 4 immediately below n ⁺ emitter region 5, the resistance in p base region 4 is large, and the potential drop, which is the product of the resistance and the hole current, is reduced by p base region 4 Exceeds the built-in potential difference at the junction between n ⁺ emitter region 5 and n ⁺ emitter region 5.
, A four-layer parasitic thyristor composed of the p ⁺ substrate 1, the n ⁺ buffer layer 2, the n base layer 3, the p base region 4, and the n ⁺ emitter region 5 operates, and latches up. It cannot be turned off. For this reason, there has been a problem that the safe operation area at the time of turn-off becomes narrow.

Conventionally, as a countermeasure, the pattern is made finer as a whole, the hole current generated in the p base region at the time of turn-off is dispersed, and the width of the n ⁺ emitter region 5 is reduced to reduce the hole current. , The operation of the parasitic thyristor is suppressed. However, when the width of the n ⁺ emitter region 5 is reduced,
At the same time, the contact width of the n ⁺ emitter region 5 with the emitter electrode 9 is reduced, so that the contact resistance is increased.
It is not necessarily possible to reduce the size indefinitely.

In view of the above problems, an object of the present invention is to provide an IGB having a wide safe operation area by making the above-mentioned parasitic thyristor difficult to operate and having a structure with small contact resistance.
T.

[0009]

In order to achieve the above object, the present invention provides a second conductive type base layer formed on one main surface of a semiconductor substrate of a first conductive type, and a second conductive type base layer formed on the second conductive type base layer. A first conductivity type base region formed on a part of the surface layer of the mold base layer; a second conductivity type emitter region selectively formed on the surface layer of the first conductivity type base region; A gate electrode provided on the surface of the first conductivity type base region interposed between the mold base layer and the second conductivity type emitter region with a gate insulating film interposed therebetween, and the first conductivity type base region and the second conductivity type A first conductivity type base region and a second conductivity type emitter, excluding a portion immediately below the gate electrode, having an emitter electrode commonly in contact with the surface of the emitter region and a collector electrode provided on the back surface of the semiconductor substrate; Between the region and the second conductivity type It shall sandwiching the semiconductor layer of the first conductivity type having a band gap wider than data region.

As a semiconductor material having a wide band gap,
Any of semiconductor materials among silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, zinc sulfide, zinc selenide, zinc telluride, cadmium sulfide, cadmium selenide, and cadmium telluride can be used. A second conductivity type base layer formed on one main surface of the first conductivity type semiconductor substrate, and a first conductivity type base region formed on a part of the surface layer of the second conductivity type base layer, A second conductivity type emitter region selectively formed on a surface layer of the first conductivity type base region; and a first conductivity type base region sandwiched between the second conductivity type base layer and the second conductivity type emitter region. A gate electrode provided on the surface of the via a gate insulating film,
An emitter electrode which is in common contact with the surfaces of the first conductivity type base region and the second conductivity type emitter region, and a collector electrode provided on the back surface of the semiconductor substrate,
An insulator layer having a wider band gap than the second conductivity type emitter region may be interposed between the first conductivity type base region and the second conductivity type emitter region except for a portion immediately below the gate electrode.

As the insulating layer having a wide band gap, any one of silicon oxide, silicon nitride, and diamond can be used.

[0012]

The first conductive type semiconductor layer having a wider band gap than the second conductive type emitter region is interposed between the first conductive type base region and the second conductive type emitter region. This suppresses the injection of carriers from the second conductivity type emitter region into the first conductivity type base region.

Further, the second conductive type base region and the second conductive type emitter region may have a structure in which an insulator layer having a wider band gap than the second conductive type emitter region is sandwiched between the first conductive type base region and the second conductive type emitter region. Injection of carriers from the conductivity type emitter region into the first conductivity type base region is suppressed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings in which parts common to those in FIG. FIG. 1 is a partial sectional view of an IGBT according to an embodiment of the present invention. In the figure, an n base layer 3 is laminated on ap ⁺ substrate 1 via an n ⁺ buffer layer 2, and a p base region 4 is selectively formed on a surface layer of the n base layer 3. An n ⁺ emitter region 5 is selectively formed in p base region 4, and a gate oxide film is formed on the surface of channel region 11 sandwiched between n base layer 3 and n ⁺ emitter region 5 of p base region 4. 6, a gate electrode 7 made of polycrystalline silicon and connected to the G terminal is provided. On the surfaces of the n ⁺ emitter region 5 and the p base region 4, an emitter electrode which is in common contact with both regions and is connected to the E terminal is formed by p.
On the back surface of ⁺ substrate 1, a collector electrode 8 connected to the C terminal is provided. In the figure, an emitter electrode 9 is extended above a gate electrode 7 via an insulating film 10. 4 is different from the conventional IGBT of FIG. 4 in that a channel region 11 is provided between n ⁺ emitter region 5 and p base region 4.
Gallium arsenide wide-gap layer 20 is provided as a semiconductor material having a band gap wider than n ⁺ emitter region 5 except for the portion. The structure of FIG. 1 is manufactured as follows. First, an n base layer 3 is formed by epitaxial growth on a substrate composed of ap ⁺ substrate 1 and an n ⁺ buffer layer 2 laminated thereon. Next, the p base region 4 is formed by introducing impurities using the gate electrode 7 formed earlier as a mask. Next, a portion to be an n ⁺ emitter region is etched, and gallium arsenide is laminated by MOCVD to form a wide gap layer 20. Further, after amorphous silicon or polycrystalline silicon is deposited on the wide gap layer 20 by a CVD method, a single crystal is formed by heat treatment, and phosphorus is ion-implanted to form the emitter region 5. Gallium arsenide has relatively close lattice constants of silicon and crystal,
A semiconductor element with few crystal defects can be obtained. Even if the band gap is large, a semiconductor material whose lattice constant is very different from that of silicon is not suitable. From this point, gallium arsenide, gallium phosphide, zinc sulfide, cadmium sulfide, indium phosphide,
Silicon carbide is suitable.

[0015] In the IGBT shown in FIG.
It is not different from IGBT. That is, the C terminal and the E terminal
When a positive voltage is applied to the gate electrode 7,
When a voltage higher than the threshold voltage is applied,
Channel is formed in the channel region 11 on the surface of the source region 4
Through the channel⁺From the emitter region 5,
Electrons are injected into the n base layer 3. n⁺Buffer layer 2
p⁺The junction with the substrate 1 is forward biased.
The electron current injected into the n base layer 3 is n⁺Buff
Through the layer 2 and through the junction described above.⁺Flow into substrate 1
I do. Then p ⁺Substrates 1 to n⁺Buffer layer 2 and
Holes are injected into the n base layer 3, and as a result n⁺Bag
Conductivity modulation occurs in the f-layer 2 and the n-base layer 3.
You. In the normal ON state, p⁺Substrate 1, n⁺
A buffer layer 2, an n-base layer 3, and a p-base region 4
Wide base pnp transistor becomes conductive
Therefore, the element is on. However, in this device, n⁺Ba
Buffer layer 2, p base region 4, n⁺Emitter region 5
The raw npn transistor constitutes the above wide
Base pnp transistor and npn transistor
And their composite p⁺Substrate 1, n⁺Buffer layer 2,
n base layer 3, p base region 4 and n⁺Emitter area
Thus, five four-layer parasitic thyristors are formed. This
When a voltage is applied at the time of turn-off of the
Holes and electrons generated by conductivity modulation in the semiconductor layer 3
Are formed between the p base region 4 and the n base layer 3, respectively.
The former is connected to the emitter electrode 9 and the latter to the
It is swept out to the collector electrode 8. At this time, the conventional IGB
In T, it is extracted to the emitter electrode through the p base region 4.
The product of the hole current and the resistance in the p base region 4 is
Source region 4 and n⁺Contact formed between emitter region 5
If the built-in potential difference exceeds⁺Emitter region 5
, Electrons are injected into p base region 4. Of this electron
The injection drives the parasitic transistor and activates the thyristor.
Operation to lower the safe operation area of the device. Only
However, according to the present invention, except for the channel region 11
n⁺A wide gap layer 20 is provided below the emitter region 5.
And this becomes a barrier to electrons, and n⁺Emi
Suppresses injection of electrons from the data region 5 into the p base region 4,
A parasitic thyristor operation can be suppressed.

FIG. 2 is a partial sectional view of an IGBT according to a second embodiment of the present invention. The difference from the first embodiment of FIG.
Trench 12 reaching n base layer 3 in p base region 4
A gate electrode 7 is buried in the trench 12 via a gate oxide film 6, an n ⁺ emitter region 5 is formed on the side wall of the trench 12, and a channel region 11 is formed on the side wall of the trench 12. Is formed vertically. n ⁺ between the emitter region 5 and the p base region 4, except as in the case the channel region 11 of FIG. 1 n ⁺
Gallium arsenide wide gap layer 20 is provided as a semiconductor layer having a band gap wider than emitter region 5. Then, suppressing the operation of the parasitic thyristor at the time of turn-off is the same as in the case of FIG. However, in this structure, the wide gap layer 20 is
Since it is configured in parallel with the side wall of the base member and is not bent, manufacture is easy.

FIG. 3 is a partial sectional view of an IGBT according to a third embodiment of the present invention. The structure is substantially the same as that of the first embodiment shown in FIG. 1 and includes a p ⁺ substrate 1, an n ⁺ buffer layer 2, an n base layer 3, a p base region 4, an n ⁺ emitter region 5, and a p base region 4. A gate oxide film 6 is formed on the surface of channel region 11 sandwiched between n base layer 3 and n ⁺ emitter region 5.
The emitter electrode 9 is provided on the surface of the gate electrode 7, the n ⁺ emitter region 5 and the p base region 4, and the collector electrode 8 is provided on the back surface of the p ⁺ substrate 1. However, n ⁺
An insulator layer 21 made of silicon oxide is provided between the emitter region 5 and the p base region 4 instead of the semiconductor wide gap layer 20 having a wider band gap than the n ⁺ emitter region 5 unlike the case of FIG. Is provided. Since the insulator layer 21 is a material having a band gap much larger than that of a semiconductor and is considered to be an extreme case of the wide gap layer 20, the injection of electrons from the n ⁺ emitter region at the time of turn-off is suppressed, and the operation of the parasitic thyristor is reduced. Is the same as in FIG. As the insulator layer, in addition to the above-described silicon oxide, silicon nitride and diamond are well compatible with silicon, and are easily formed and suitable.

[0018]

According to the present invention, a semiconductor layer having a band gap wider than that of the second conductivity type emitter region is sandwiched between the first conductivity type base region and the second conductivity type emitter region except for the channel region. In addition, the barrier against injection of electrons from the second conductivity type emitter region is increased, and the operation of the parasitic thyristor when the IGBT is turned off is suppressed, so that the safe operation region can be expanded.

The same effect can be obtained by interposing an insulating layer having a wider band gap.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of an IGBT according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of an IGBT according to a second embodiment of the present invention.

FIG. 3 is a partial sectional view of an IGBT according to a third embodiment of the present invention.

FIG. 4 is a partial cross-sectional view of a conventional IGBT.

[Explanation of symbols]

Reference Signs List 1 p ⁺ substrate 2 n ⁺ buffer layer 3 n base layer 4 p base region 5 n ⁺ emitter region 6 gate oxide film 7 gate electrode 8 collector electrode 9 emitter electrode 10 insulating film 11 channel region 20 wide gap layer 21 insulating layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (7)

(57) [Claims] A first conductive type base layer formed on one main surface of a first conductive type semiconductor substrate; and a first conductive type base layer formed on a part of the surface layer of the second conductive type base layer. A base region, a second conductivity type emitter region selectively formed on a surface layer of the first conductivity type base region, and a semiconductor substrate.
One is on the main surface and the second conductivity type base layer and a gate electrode formed via a gate insulating film on the surface of the first conductivity type base region sandwiched between the second conductive type emitter region, the An emitter electrode which is in common contact with the surfaces of the first conductivity type base region and the second conductivity type emitter region, and a collector electrode provided on the other main surface of the semiconductor substrate, wherein the collector electrode is provided immediately below the gate electrode. Gallium arsenide, gallium phosphide, indium phosphide, sulfur having a wider band gap than the second conductivity type emitter region between the first conductivity type base region and the second conductivity type emitter region excluding the portion.
Either zinc oxide or cadmium sulfide
An insulated gate bipolar transistor characterized by being sandwiched . 2. A second conductivity type base layer formed on one main surface of a first conductivity type semiconductor substrate, and a first conductivity type base region formed on a surface layer of the second conductivity type base layer. When,
A second conductivity type emitter region selectively formed on a surface layer of the first conductivity type base region, and a side surface reaching the second conductivity type base layer from one main surface of the semiconductor substrate and having a second conductivity type. A groove formed to contact the emitter region;
A gate electrode provided in the trench with a gate insulating film interposed therebetween, an emitter electrode commonly in contact with the surfaces of the first conductivity type base region and the second conductivity type emitter region, and on the other main surface of the semiconductor substrate A collector electrode provided in the first conductive type base region and the second conductive type emitter region at least partially between the semiconductor layer having a band gap wider than the second conductive type emitter region An insulated gate bipolar transistor characterized by being sandwiched. 3. The insulated gate bipolar transistor according to claim 1, wherein the semiconductor layer having a wide band gap is of a first conductivity type. 4. The semiconductor layer according to claim 2, wherein the semiconductor layer having a wide band gap is made of any one of gallium arsenide, gallium phosphide, indium phosphide, zinc sulfide, cadmium sulfide, and silicon carbide. Insulated gate bipolar transistor. 5. A second conductivity type base layer formed on one main surface of a first conductivity type semiconductor substrate, and a first conductivity type formed on a part of the surface layer of the second conductivity type base layer. Mold base region, a second conductivity type emitter region selectively formed on the surface layer of the first conductivity type base region, and a second conductivity type emitter region sandwiched between the second conductivity type base layer and the second conductivity type emitter region. A gate electrode provided on the surface of the one conductivity type base region via a gate insulating film, an emitter electrode commonly contacting the surfaces of the first conductivity type base region and the second conductivity type emitter region, And a collector electrode provided on the other main surface, wherein the second conductivity type emitter region is located between the first conductivity type base region and the second conductivity type emitter region except for a portion immediately below the gate electrode. Insulation with wide band gap Insulated gate bipolar transistor, characterized in that across the. 6. On one main surface of a semiconductor substrate of the first conductivity type.
A second conductivity type base layer formed on the second conductivity type base layer;
A first conductivity type base region formed on the surface layer of the base layer,
Selectively formed on the surface layer of the first conductivity type base region
A second conductivity type emitter region, and one of the semiconductor substrates
The side surface reaching the second conductive type base layer from the main surface is the second conductive type base layer.
A groove formed in contact with the two-conductivity type emitter region,
A gate electrode provided in the trench via a gate insulating film
And the first conductivity type base region and the second conductivity type emitter region.
Emitter electrode in common contact with the surface of the region and the semiconductor substrate
And a collector electrode provided on the other main surface of
The first conductive type base region and the second conductive type base region.
The second conductivity type at least in part between the second conductivity type
An insulator with a bandgap wider than the emitter region
Insulated gate bipolar transistor characterized by being sandwiched
Star. 7. An insulator having a wide band gap is used as an insulator.
Any of silicon, silicon nitride and diamond
7. An insulating material according to claim 5 or claim 6.
Insulated gate bipolar transistor according to any of the above
Ta.