JPH0669510A - High-breakdown-strength semiconductor device - Google Patents

High-breakdown-strength semiconductor device

Info

Publication number
JPH0669510A
JPH0669510A JP24119792A JP24119792A JPH0669510A JP H0669510 A JPH0669510 A JP H0669510A JP 24119792 A JP24119792 A JP 24119792A JP 24119792 A JP24119792 A JP 24119792A JP H0669510 A JPH0669510 A JP H0669510A
Authority
JP
Japan
Prior art keywords
region
substrate
diffusion region
conductor wiring
concentration diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24119792A
Other languages
Japanese (ja)
Other versions
JP3217484B2 (en
Inventor
Takaaki Negoro
宝昭 根来
Masanori Ohito
正則 大仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP24119792A priority Critical patent/JP3217484B2/en
Publication of JPH0669510A publication Critical patent/JPH0669510A/en
Application granted granted Critical
Publication of JP3217484B2 publication Critical patent/JP3217484B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To relax that an electric field is concentrated at the tip part of a field plate. CONSTITUTION:A field plate 20a used to prevent that the surface of a substrate is depleted and inverted directly under a metal interconnection 16 is located between the metal interconnection 16 and a substrate 2, and it is extended up to the upper part of a guard ring 12 from the upper part of a drain region 4. The field plate 20a is insulated from both the substrate 2 and the metal interconnection 16, and its base end part is connected to the drain region 4. A P-type low-concentration diffused region 22 which is connected to the guard ring 12 and whose conductivity type is the same as that of the guard ring 12 is formed on the surface of the substrate at the lower side of the field plate 20a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高耐圧MOSFETに関
するものである。高耐圧MOSFETは、他の半導体素
子とともに同じ半導体基板に集積化されて用いられた
り、電力用半導体装置などとして個別素子としても用い
られる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage MOSFET. The high breakdown voltage MOSFET is used by being integrated with other semiconductor elements on the same semiconductor substrate, or used as an individual element as a power semiconductor device or the like.

【0002】[0002]

【従来の技術】シリコン基板表面にソース領域とドレイ
ン領域が対向して形成された高耐圧MOSFETでは、
例えば高耐圧MOSトランジスタと低耐圧MOSトラン
ジスタとを1つの半導体基板に混載させる場合など、高
耐圧MOSトランジスタのソース領域につながる配線を
引き出したときにその配線はソース領域とドレイン領域
の基板上を横切る。ドレインに高電圧を印加したとき、
ソース配線直下の基板が空乏化し、ソースとドレインが
短絡することがある。そのような不具合を解消する1つ
の手段としてフィールドプレートを設けるのが有効であ
ることが知られている。
2. Description of the Related Art In a high breakdown voltage MOSFET in which a source region and a drain region are formed on a surface of a silicon substrate so as to face each other,
For example, when a high breakdown voltage MOS transistor and a low breakdown voltage MOS transistor are mixedly mounted on one semiconductor substrate, when a wiring connected to the source region of the high breakdown voltage MOS transistor is drawn, the wiring crosses the source region and the drain region on the substrate. . When a high voltage is applied to the drain,
The substrate directly under the source wiring may be depleted, causing a short circuit between the source and the drain. It is known that providing a field plate is effective as one means for solving such a problem.

【0003】図3はフィールドプレートを設けた高耐圧
MOSFETの一例を示す。誘電体で分離されたN型シ
リコン基板2に高耐圧MOSFETが形成されている。
基板2の側面及び底面には内側を取り囲むように高濃度
N型拡散領域によるドレイン領域4が形成されている。
基板2内には低濃度P型拡散領域6内に高濃度N型拡散
領域によるソース領域8が形成されている。10は領域
6のコンタクト領域である。基板表面にはチャネル領域
となるP型領域6を取り囲むように、高濃度P型拡散領
域からなり空乏層の伸長を防ぐためのガードリングと称
される拡散層12が形成されている。
FIG. 3 shows an example of a high breakdown voltage MOSFET provided with a field plate. A high breakdown voltage MOSFET is formed on an N-type silicon substrate 2 separated by a dielectric.
On the side surface and the bottom surface of the substrate 2, a drain region 4 formed of a high concentration N-type diffusion region is formed so as to surround the inside.
In the substrate 2, a source region 8 of a high concentration N type diffusion region is formed in a low concentration P type diffusion region 6. Reference numeral 10 is a contact region of the region 6. A diffusion layer 12 called a guard ring is formed on the surface of the substrate so as to surround the P-type region 6 serving as a channel region, the diffusion layer 12 being a high-concentration P-type diffusion region for preventing extension of the depletion layer.

【0004】基板2上にはゲート酸化膜を介してチャネ
ル領域上にゲート電極14が形成されている。16は基
板2ともゲート電極14とも絶縁されて層間絶縁膜18
上に形成されたメタル配線であり、層間絶縁膜18のコ
ンタクトホールを経てソース8及びコンタクト10に接
続されている。メタル配線16はこの高耐圧MOSFE
Tから他の半導体素子や外部に接続するために素子分離
された基板上部を横切っている。メタル配線16直下で
基板表面が空乏化して反転するのを防ぐ目的のフィール
ドプレート20がポリシリコン薄膜で形成され、フィー
ルドプレート20はドレイン領域4と接続されている。
A gate electrode 14 is formed on the substrate 2 on the channel region via a gate oxide film. Reference numeral 16 denotes an interlayer insulating film 18 which is insulated from both the substrate 2 and the gate electrode 14.
It is a metal wiring formed above and is connected to the source 8 and the contact 10 via the contact hole of the interlayer insulating film 18. The metal wiring 16 has this high withstand voltage MOSFE.
It traverses the upper part of the substrate, which is separated from the semiconductor element for connecting from T to another semiconductor element or the outside. A field plate 20 for preventing depletion and inversion of the substrate surface immediately below the metal wiring 16 is formed of a polysilicon thin film, and the field plate 20 is connected to the drain region 4.

【0005】[0005]

【発明が解決しようとする課題】図3のようにフィール
ドプレート20を設けた高耐圧MOSFETでは、フィ
ールドプレート20のソース側の端部では電界が集中
し、その部分でPN接合のブレイクダウンが生じる。そ
のため、電界が集中するこの部分の電界を緩和すること
が課題となっている。フィールドプレートによる電界集
中を緩和する1つの方法は、フィールドプレート先端か
ら他の電極までの間に抵抗材料シートを形成することで
ある。ただし、その方法はバイポーラトランジスタにつ
いて行なわれている(特公昭52−24833号公報参
照)。しかし、この引例の手段を本発明の対象とするM
OSFETに適用すれば、ソースとドレイン間にリーク
電流が流れる不都合が発生する。本発明は引例とは異な
る他の手段によってフィールドプレート先端部での電界
集中を緩和する手段を備えた高耐圧MOSFETを提供
することを目的とするものである。
In the high breakdown voltage MOSFET provided with the field plate 20 as shown in FIG. 3, the electric field is concentrated at the source side end portion of the field plate 20, and the breakdown of the PN junction occurs at that portion. . Therefore, there is a problem to alleviate the electric field in this portion where the electric field is concentrated. One way to mitigate the electric field concentration by the field plate is to form a sheet of resistive material between the tip of the field plate and the other electrode. However, the method is applied to a bipolar transistor (see Japanese Patent Publication No. 52-24833). However, the means of this reference is the subject of the present invention, M
If applied to the OSFET, there arises a problem that a leak current flows between the source and the drain. It is an object of the present invention to provide a high breakdown voltage MOSFET provided with means for relaxing the electric field concentration at the tip of the field plate by means other than the reference.

【0006】[0006]

【課題を解決するための手段】本発明では、ソース配線
直下でフィールドプレートのソース側の端部の基板表面
にはチャネル部と同じ導電型の高濃度拡散領域を設け、
この高濃度拡散領域よりドレイン側の部分にその高濃度
拡散領域と同じ導電型でその高濃度拡散領域につながる
低濃度拡散領域を設ける。本発明の他の態様では、ソー
ス配線直下でフィールドプレートのソース側の端部の基
板表面にはチャネル部と同じ導電型の高濃度拡散領域を
設け、この高濃度拡散領域よりドレイン側の部分にその
高濃度拡散領域と同じ導電型でその高濃度拡散領域から
離れた第2の拡散領域を設ける。好ましい態様では、こ
の第2の拡散領域は互いに離れてドレイン側の方向に配
列された2個以上の領域を含んでいる。
According to the present invention, a high-concentration diffusion region having the same conductivity type as that of a channel portion is provided on the substrate surface at the source-side end portion of the field plate immediately below the source wiring,
A low concentration diffusion region having the same conductivity type as the high concentration diffusion region and connected to the high concentration diffusion region is provided on the drain side of the high concentration diffusion region. In another aspect of the present invention, a high-concentration diffusion region of the same conductivity type as the channel portion is provided on the substrate surface at the source-side end portion of the field plate immediately below the source wiring, and a portion closer to the drain side than the high-concentration diffusion region is provided. A second diffusion region having the same conductivity type as the high concentration diffusion region and separated from the high concentration diffusion region is provided. In a preferred embodiment, the second diffusion region includes two or more regions which are arranged apart from each other in the drain side direction.

【0007】[0007]

【作用】ソース領域とドレイン領域の間で空乏層が両領
域間でつながるリーチスルーを防ぐためのガードリング
は従来から設けられているが、さらに高耐圧を図ろうと
した場合、ガードリングだけでは不十分である。本発明
ではガードリング又はガードリングと類似の役割を果た
す拡散領域の他に、その拡散領域とドレイン領域の間の
基板表面に更にチャネル部と同じ導電型の拡散領域を設
けることによって空乏層のドレイン方向への広がりを更
に抑える。
A guard ring has been conventionally provided to prevent a reach-through in which a depletion layer is connected between the source region and the drain region between both regions. However, if a higher breakdown voltage is to be achieved, the guard ring alone is not enough. It is enough. In the present invention, in addition to the guard ring or the diffusion region that plays a role similar to that of the guard ring, a drain region of the depletion layer is formed by providing a diffusion region of the same conductivity type as the channel portion on the substrate surface between the diffusion region and the drain region. Further suppress the spread in the direction.

【0008】[0008]

【実施例】図1は第1の実施例を表わす。図3と同一の
部分には同一の符号を用いる。図1で、誘電体で分離さ
れたN型シリコン基板2に高耐圧MOSFETが形成さ
れている。基板2の側面及び底面には内側を取り囲むよ
うに高濃度N型拡散領域によるドレイン領域4が形成さ
れており、基板2内では低濃度P型拡散領域6内に高濃
度N型拡散領域によるソース領域8が形成されている。
10は領域6のコンタクト領域である。基板表面にはチ
ャネル領域となるP型領域6を取り囲むように、高濃度
P型拡散領域からなり空乏層の伸長を防ぐためのガード
リング12が形成されている。基板2上にはゲート酸化
膜を介してチャネル領域上にゲート電極14が形成され
ている。16は基板2ともゲート電極14とも絶縁され
て層間絶縁膜18上に形成されたメタル配線であり、層
間絶縁膜18のコンタクトホールを経てソース8及びコ
ンタクト10に接続されている。メタル配線16はこの
高耐圧MOSFETから他の半導体素子や外部に接続す
るために素子分離された基板上部を横切っている。メタ
ル配線16直下で基板表面が空乏化して反転するのを防
ぐ目的のフィールドプレート20aがポリシリコン薄膜
で形成されている。フィールドプレート20aはメタル
配線16と基板2の間にあって、ドレイン領域4上から
ガードリング12上まで延びている。フィールドプレー
ト20aは基板2ともメタル配線16とも絶縁されてお
り、基端部はドレイン領域4と接続されている。フィー
ルドプレート20aの下側の基板表面ではガードリング
12とつながりガードリング12と同じ導電型のP型で
低濃度の拡散領域22が形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment. The same parts as those in FIG. 3 are designated by the same reference numerals. In FIG. 1, a high breakdown voltage MOSFET is formed on an N-type silicon substrate 2 separated by a dielectric. A drain region 4 of a high-concentration N-type diffusion region is formed on the side surface and the bottom surface of the substrate 2 so as to surround the inside, and a source of the high-concentration N-type diffusion region is formed in a low-concentration P-type diffusion region 6 in the substrate 2. Region 8 is formed.
Reference numeral 10 is a contact region of the region 6. On the surface of the substrate, a guard ring 12 is formed of a high-concentration P-type diffusion region so as to surround the P-type region 6 serving as a channel region and prevent the extension of the depletion layer. A gate electrode 14 is formed on the substrate 2 on the channel region via a gate oxide film. Reference numeral 16 denotes a metal wiring which is insulated from both the substrate 2 and the gate electrode 14 and is formed on the interlayer insulating film 18, and is connected to the source 8 and the contact 10 through the contact hole of the interlayer insulating film 18. The metal wiring 16 traverses the upper part of the substrate, which is separated from the high-voltage MOSFET to connect to other semiconductor devices and the outside. A field plate 20a for preventing depletion and inversion of the substrate surface immediately below the metal wiring 16 is formed of a polysilicon thin film. The field plate 20a is located between the metal wiring 16 and the substrate 2 and extends from above the drain region 4 to above the guard ring 12. The field plate 20a is insulated from both the substrate 2 and the metal wiring 16, and the base end portion is connected to the drain region 4. On the substrate surface below the field plate 20a, a low concentration diffusion region 22 which is connected to the guard ring 12 and has the same conductivity type as the guard ring 12 is formed.

【0009】図1の実施例では、ドレイン領域4に高電
圧が印加されてソース・ドレイン間が逆バイアスされた
ときに生じる空乏層は、拡散層12,22の周辺に広が
るが、拡散層22が存在することによって空乏層の曲率
半径が大きくなり、PN接合のブレイクダウン電圧が高
められる。
In the embodiment of FIG. 1, the depletion layer generated when a high voltage is applied to the drain region 4 and the source / drain is reversely biased spreads around the diffusion layers 12 and 22, but the diffusion layer 22. Is present, the radius of curvature of the depletion layer is increased, and the breakdown voltage of the PN junction is increased.

【0010】図2は第2の実施例を表わす。図1と同一
部分には同一の符号を用いて説明を省略する。図1の実
施例と比較すると、図1ではガードリング12につなが
る低濃度N型拡散領域22がフィールドプレート20a
の下部の基板表面に形成されているのに対し、図2では
メタル配線16及びフィールドプレート20aの直下の
基板表面にガードリング12と離れたP型高濃度拡散領
域24と26がガードリング12とレイン領域4の間に
設けられている。P型拡散領域24と26はガードリン
グ12と離れ、P型拡散領域24と26も互いに離れて
配置されている。P型拡散領域24と26は低濃度拡散
領域であってもよい。
FIG. 2 shows a second embodiment. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. As compared with the embodiment of FIG. 1, in FIG. 1, the low concentration N-type diffusion region 22 connected to the guard ring 12 is formed in the field plate 20a.
2, the P-type high concentration diffusion regions 24 and 26 separated from the guard ring 12 are formed on the substrate surface immediately below the metal wiring 16 and the field plate 20a. It is provided between the rain regions 4. P-type diffusion regions 24 and 26 are separated from guard ring 12, and P-type diffusion regions 24 and 26 are also arranged apart from each other. The P type diffusion regions 24 and 26 may be low concentration diffusion regions.

【0011】図2でもソースとドレイン間に逆バイアス
電圧が印加されたとき、空乏層が拡散領域12,24,
26まで広がってくるが、このときも空乏層の曲率半径
が大きくなって電界集中が緩和され、PN接合のブレイ
クダウン電圧が高められる。図2の実施例ではガードリ
ング12よりドレイン側に配列されたP型拡散領域は2
4と26で示される2個であるが、1個でもよく、3個
以上としてもよい。拡散領域24,26の数の多い方が
空乏層の曲率半径がより大きくなって電界集中がより緩
和される効果がある。
Also in FIG. 2, when a reverse bias voltage is applied between the source and the drain, the depletion layer causes diffusion regions 12, 24,
However, even at this time, the radius of curvature of the depletion layer is increased, the concentration of the electric field is relaxed, and the breakdown voltage of the PN junction is increased. In the embodiment of FIG. 2, the number of P-type diffusion regions arranged on the drain side of the guard ring 12 is 2.
Although it is two as shown by 4 and 26, it may be one or three or more. The larger the number of diffusion regions 24 and 26 is, the larger the radius of curvature of the depletion layer becomes, and the more the electric field concentration is relaxed.

【0012】[0012]

【発明の効果】本発明ではソース配線直下でフィールド
プレートのソース側の端部の基板表面にはチャネル部と
同じ導電型の高濃度拡散領域を設け、この高濃度拡散領
域よりドレイン側の部分にその高濃度拡散領域と同じ導
電型でその高濃度拡散領域につながる低濃度拡散領域を
設けたので、ソースとドレイン間に逆バイアス電圧が印
加されたときの空乏層の曲率半径が大きくなり、電界集
中によるPN接合のブレイクダウン電圧が高められて、
より高耐圧のMOSFETが実現できる。
According to the present invention, a high-concentration diffusion region of the same conductivity type as that of the channel portion is provided on the substrate surface of the end portion on the source side of the field plate immediately below the source wiring, and a portion closer to the drain side than the high-concentration diffusion region is provided. Since a low-concentration diffusion region having the same conductivity type as that of the high-concentration diffusion region and connected to the high-concentration diffusion region is provided, the radius of curvature of the depletion layer increases when a reverse bias voltage is applied between the source and the drain, and the electric field The breakdown voltage of the PN junction due to concentration is increased,
A higher breakdown voltage MOSFET can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】第1の実施例を示す図であり、(A)は要部平
面図、(B)はそのX−X’線位置での断面図である。
FIG. 1 is a diagram showing a first embodiment, (A) is a plan view of a main part, and (B) is a sectional view taken along line XX ′.

【図2】第2の実施例を示す図であり、(A)は要部平
面図、(B)はそのY−Y’線位置での断面図である。
2A and 2B are views showing a second embodiment, FIG. 2A is a plan view of a main part, and FIG. 2B is a sectional view taken along the line YY '.

【図3】従来の高耐圧MOSFETを示す図であり、
(A)は要部平面図、(B)はそのZ−Z’線位置での
断面図である。
FIG. 3 is a diagram showing a conventional high breakdown voltage MOSFET,
(A) is a plan view of a main part, and (B) is a cross-sectional view taken along the line ZZ '.

【符号の説明】[Explanation of symbols]

2 N型基板 4 ドレイン領域 6 チャネルとなるP型領域 8 ソース領域 12 ガードリングのP型拡散領域 14 ゲート電極 16 ソースにつながるメタル配線 20a フィールドプレート 22 低濃度P型拡散領域 24,26 高濃度拡散領域 2 N-type substrate 4 Drain region 6 P-type region to be a channel 8 Source region 12 P-type diffusion region of guard ring 14 Gate electrode 16 Metal wiring connected to the source 20a Field plate 22 Low-concentration P-type diffusion region 24, 26 High-concentration diffusion region

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面にソース領域とドレイン
領域が対向して形成され、ソース領域と接続された第1
の導電体配線の直下にドレイン領域と接続された第2の
導電体配線が前記基板及び第1の導電体配線とは絶縁体
を介して絶縁されて形成されており、第1の導電体配線
直下で第2の導電体配線のソース領域側の端部の基板表
面にはチャネル部と同じ導電型の高濃度拡散領域と、こ
の高濃度拡散領域よりドレイン領域側の部分でその高濃
度拡散領域と同じ導電型でその高濃度拡散領域につなが
る低濃度拡散領域が形成されていることを特徴とする高
耐圧半導体装置。
1. A first region in which a source region and a drain region are formed facing each other on a surface of a semiconductor substrate and connected to the source region.
The second conductor wiring connected to the drain region is formed immediately below the conductor wiring, and is insulated from the substrate and the first conductor wiring via an insulator, and the first conductor wiring is formed. Immediately below, on the substrate surface of the end portion of the second conductor wiring on the source region side, a high-concentration diffusion region of the same conductivity type as that of the channel portion, and the high-concentration diffusion region on the drain region side of the high-concentration diffusion region. A high-voltage semiconductor device having a low-concentration diffusion region connected to the high-concentration diffusion region of the same conductivity type as that of 1.
【請求項2】 半導体基板表面にソース領域とドレイン
領域が対向して形成され、ソース領域と接続された第1
の導電体配線の直下にドレイン領域と接続された第2の
導電体配線が前記基板及び第1の導電体配線とは絶縁体
を介して絶縁されて形成されており、第1の導電体配線
直下で第2の導電体配線のソース領域側の端部の基板表
面にはチャネル部と同じ導電型の高濃度拡散領域と、こ
の高濃度拡散領域よりドレイン領域側の部分でその高濃
度拡散領域と同じ導電型でその高濃度拡散領域から離れ
た第2の拡散領域が形成されていることを特徴とする高
耐圧半導体装置。
2. A first region having a source region and a drain region formed opposite to each other on a surface of a semiconductor substrate and connected to the source region.
The second conductor wiring connected to the drain region is formed immediately below the conductor wiring, and is insulated from the substrate and the first conductor wiring via an insulator, and the first conductor wiring is formed. Immediately below, on the substrate surface of the end portion of the second conductor wiring on the source region side, a high-concentration diffusion region of the same conductivity type as that of the channel portion, and the high-concentration diffusion region on the drain region side of the high-concentration diffusion region. A high withstand voltage semiconductor device having a second diffusion region of the same conductivity type as that of the second diffusion region separated from the high concentration diffusion region.
【請求項3】 前記第2の拡散領域は互いに離れてドレ
イン領域の方向に配列された2個以上の領域を含んでい
る請求項2に記載の高耐圧半導体装置。
3. The high breakdown voltage semiconductor device according to claim 2, wherein the second diffusion region includes two or more regions which are arranged apart from each other in the direction of the drain region.
JP24119792A 1992-08-17 1992-08-17 High voltage semiconductor device Expired - Fee Related JP3217484B2 (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24119792A JP3217484B2 (en) 1992-08-17 1992-08-17 High voltage semiconductor device

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JP3217484B2 JP3217484B2 (en) 2001-10-09

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0755072A1 (en) * 1995-07-20 1997-01-22 Siemens Aktiengesellschaft CMOS circuit with field plate and method of production

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2165610B1 (en) 2007-06-08 2013-03-27 Idemitsu Kosan Co., Ltd. Tympanites ventriculi-controlling agent for ruminant animals
BRPI1013053A2 (en) * 2009-06-08 2016-04-05 Idemitsu Kosan Co coccidiosis control agent for an animal, feed additive, method for raising an animal, and heated cashew nut and / or cardanol liquid

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0755072A1 (en) * 1995-07-20 1997-01-22 Siemens Aktiengesellschaft CMOS circuit with field plate and method of production

Also Published As

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