JP3233002B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly, to a high withstand voltage lateral field effect transistor.

[0002]

2. Description of the Related Art FIG. 2 shows an offset type lateral field effect transistor which is a structural example of a high breakdown voltage lateral field effect transistor.
This will be described with reference to FIG.

A p-well 2 in which p-type impurities are diffused at a higher concentration than the silicon substrate 1 is formed in a part of the main surface 1a of the p-type silicon substrate 1. An offset layer 3 in which n-type impurities are diffused at a low concentration and which increases the withstand voltage is formed on the surface in the p-well 2. On the surface in the offset layer 3, a drain 4 in which an n-type impurity is diffused at a high concentration is formed. On the surface in the p-well 2, a source 5 in which an n-type impurity is diffused at a high concentration is formed at a certain distance from the offset layer 3. On the surface near the source 5 in the p-well 2,
A contact layer 6 in which p-type impurities are diffused at a high concentration is formed.

A gate insulating film 7 is formed on p well 2 between source 5 and offset layer 3. A gate electrode 8 is formed on the gate insulating film 7. A source electrode 10 is formed on the contact layer 6 from the source 5, and a drain electrode 11 is formed on the drain 4. A field oxide film 9 is formed in a region where the electrodes 8, 10, and 11 are not formed.

In this structure, a low concentration impurity offset layer 3 is formed around the drain 4. When a reverse voltage is applied between the source 5 and the drain 4 having this structure, the electric field at the edge 3a of the offset layer increases. However, since the offset layer 3 has a low impurity concentration, the breakdown voltage is higher than that of the drain edge 4a having a high impurity concentration when the offset layer 3 is not formed.

As a structure for improving the breakdown voltage, there is a double RESURF type lateral field effect transistor. This structure will be described with reference to FIG.

On the main surface 21a of the p-type silicon substrate 21, n
An n-well 22 in which a type impurity is diffused is formed.
On the surface of n-well 22, p-well 23 in which p-type impurities are diffused is formed. On the surface of the p-well 23, a source 24 in which an n-type impurity is diffused at a high concentration is formed. On the surface of the n-well 22 at a certain distance from the p-well 23, a drain 25 in which an n-type impurity is diffused at a high concentration is formed. On the surface of the p-well 23, a contact layer 26 in which p-type impurities are diffused at a high concentration is formed. On the surface in the n-well 22 between the source 24 and the drain 25, a p-type diffusion layer 27 in which p-type impurities are diffused is formed. The p-type diffusion layer 27 is electrically connected to the p-type silicon substrate 21 (not shown) and has the same potential. The region of the n-well 22 sandwiched between the p-type diffusion layer 27 and the p-type substrate 21 is called an extended drain region 28. A gate insulating film 29 is formed on p well 23 between source 24 and n well 22. A gate electrode 30 on the gate insulating film 29;
Are formed. A source electrode 32 is formed over the source 24 and the contact layer 26, and a drain electrode 33 is formed on the drain 25. Electrodes 30, 3 on main surface 21a
A field oxide film 3 is formed in a region where no 2, 33 is formed.
1 is formed.

In this structure, the source 24 and the drain 25
To reduce the electric field between the source 24 and the drain 25
A p-type diffusion layer 27 is formed on the surface of the n-well 22 between them. Thus, when a reverse voltage is applied between the source 24 and the drain 25, the depletion layer spreads from the p-type silicon substrate 21 and the p-type diffusion layer 27 to the extended drain region 28 in the n-well 22, and finally the depletion layer Is connected. For this reason, the extended drain region 28 functions as an electric field relaxation layer, and the breakdown voltage is improved.

[0009]

In the structure of the offset type lateral field effect transistor, there is a problem that the resistance between the source 5 and the drain 4 is increased by the presence of the offset layer 3, and as a result, the on-resistance is increased.

In the structure of the double RESURF type lateral field effect transistor, the distance between the source 24 and the drain 25 is increased because the p-type diffusion layer 27 is present between the source 24 and the drain 25. The resistance between them increases. As a result, there is a problem that the on-resistance increases.

[0011]

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and has been proposed in which a well of another conductivity type formed on a main surface of a semiconductor substrate of one conductivity type and a surface inside the well of another conductivity type are provided. The formed one-conductivity-type well, the other-conductivity-type source formed on the surface in the one-conductivity-type well, and the offset layer over the other-conductivity-type well and the surface of the one-conductivity-type well.
A high-concentration other-conductivity-type drain formed without interposition, a gate electrode formed on a one-conductivity-type well between the source and the drain via a gate insulating film, a source electrode formed on the source, and formed on the drain And a field effect transistor having the drain electrode formed as described above. As a result, when the potential of the drain is increased, the well of one conductivity type becomes a depletion layer.
The on-resistance does not increase.

[0012] Further, another conductivity type well formed on the main surface of the one conductivity type semiconductor substrate, one conductivity type well formed on the surface in the other conductivity type well, and another one formed on the surface of the one conductivity type well. On the surface of a well of one conductivity type and one conductivity type
A high-concentration other-conductivity-type drain formed without an offset layer, a gate electrode formed on a well of one conductivity type between a source and a drain via a gate insulating film, and a source electrode formed on a main surface of the source And a field effect transistor having a drain electrode formed on the drain and electrically connected to the other conductivity type well. This is because the connection is made by wiring instead of forming the drain over the well of one conductivity type and the well of the other conductivity type, so that the same effect as the above effect can be obtained.

In the above description, the one conductivity type well sandwiched between the other conductivity type well and the drain under the drain is designed to be completely depleted when a reverse voltage is applied between the source and the drain. As a result, the depletion layer extends to the edge of the drain, so that the electric field strength at the edge of the drain is reduced, the breakdown voltage is improved, and the on-resistance does not increase.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lateral field effect transistor according to the present invention will be described with reference to FIG. One conductivity type, for example p
An n-well 42 is formed in a part of the main surface 41a of the silicon substrate 41 by ion implantation and thermal diffusion of an n-type impurity which is another conductivity type impurity. A p-well 43 is formed on the surface of the n-well 42 by ion implantation of a p-type impurity. A source 44 is formed on the surface of the p-well 43 by ion implantation of a high concentration n-type impurity. n-well 42
The drain 45 is formed by ion-implanting high-concentration n-type impurities. A contact layer 46 is formed near the source 44 on the surface of the p-well 43 by ion implantation of a high-concentration p-type impurity.

A p-well 4 between a source 44 and a drain 45
The gate insulating film 47 is formed on the substrate 3 by thermal oxidation.
A gate electrode 48 is formed by growing a polysilicon layer on the gate insulating film 47 by CVD. Gate electrode 4
Numeral 8 is diffused at a high concentration using an n-type impurity gas source to reduce the resistance. A source electrode 50 is formed over the source 44 and the contact layer 46, and a drain electrode 51 is formed on the drain 45 by sputtering. A field oxide film 49 is formed by thermal oxidation on the surface of the p-type silicon substrate 41 on which the electrodes 48, 50 and 51 are not formed.

In the lateral field effect transistor of the present invention,
When a voltage is applied between the source electrode 50 and the drain electrode 51 to increase the potential, the junction between the drain 45 and the p-well 43 and the n-well 42 and the p-well 43
The depletion layer expands at both the junctions. When a predetermined potential is reached between the source electrode 50 and the drain electrode 51, a depletion layer extending from the two junctions is connected, so that the p-well 43 between the drain bottom 45a and the p-well bottom 43b is completely formed. Depletion layer. As a result, the electric field intensity at the edge 45b of the drain 45 is reduced, and the breakdown voltage is improved. At this time, the structure between the source 44 and the drain 45 is the same as the structure having no offset of the lateral electric field transistor described in the related art, and does not increase the on-resistance.

Further, since the p-well 43 is formed in the n-well 42 having the same potential as the n-type drain 45, the p-well 43 having the same potential as the source 44 can be floated from the silicon substrate 41. Can be set freely.

This enables applications such as connecting a sense resistor between the p-type silicon substrate 41 and the source electrode 50 which are grounded during use.

In the above structure, although not shown, a drain is formed on the surface of the p-well, and a drain electrode formed on the drain is electrically connected to an electrode formed on the n-well 42. With.

[0020]

As described above, when a voltage is applied between the source electrode and the drain electrode to increase the potential, the drain and the p
The depletion layers expand at both the junction with the well and the junction between the n-well and the p-well. Then, when a predetermined potential is reached between the source electrode and the drain electrode, the depletion layers extending from the two junctions are connected, and the p-well is completely depleted. As a result, the electric field intensity at the edge of the drain is alleviated, and a high breakdown voltage lateral field effect transistor is obtained. At this time, the on-resistance is not increased.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a lateral field-effect transistor of the present invention.

FIG. 2 is a cross-sectional view of a conventional offset type lateral field effect transistor.

FIG. 3 is a cross-sectional view of a conventional double resurf type lateral field effect transistor.

[Explanation of symbols]

 41 One-conductivity-type semiconductor substrate (p-type silicon substrate) 41a Main surface 42 Other-conductivity-type well (n-well) 43 One-conductivity-type well (p-well) 44 Source 45 Drain 47 Gate insulating film 48 Gate electrode 50 Source electrode 51 Drain electrode

Claims (2)

(57) [Claims] 1. A well of another conductivity type formed on a main surface of a semiconductor substrate of one conductivity type, a well of one conductivity type formed on a surface of the well of another conductivity type, and a well formed on a surface of the well of one conductivity type. A source of another conductivity type, a high-concentration other conductivity type drain formed without interposing an offset layer over the surface of the other conductivity type well and the one conductivity type well, and the source and the source a gate electrode to which the formed via a gate insulating film on one conductive well between the drain and source electrodes formed on said source, and a drain electrode formed on said drain, said under the drain Other conductivity type well and the above
The one conductivity type well sandwiched between the drain and the source is
Completely depleted when a reverse voltage is applied between the
Field effect transistor to be layered . A second conductivity type well formed on a main surface of the one conductivity type semiconductor substrate; a first conductivity type well formed on a surface of the other conductivity type well; and a second conductivity type well formed on a surface of the one conductivity type well. A source of another conductivity type and a surface of the well of one conductivity type;
A high-concentration other-conductivity-type drain formed without an offset layer, a gate electrode formed on the one-conductivity-type well between the source and the drain via a gate insulating film,
A source electrode formed on said source, and a drain electrode connected said to other conductive well electrically so as to form on said drain, said other conductive under the drain
The one conductivity type well sandwiched between the electrical type well and the drain.
The well applied a reverse voltage between the source and the drain
A field effect transistor that is sometimes completely depleted .