JP2883779B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2883779B2 JP2883779B2 JP797193A JP797193A JP2883779B2 JP 2883779 B2 JP2883779 B2 JP 2883779B2 JP 797193 A JP797193 A JP 797193A JP 797193 A JP797193 A JP 797193A JP 2883779 B2 JP2883779 B2 JP 2883779B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- region
- semiconductor device
- conductivity type
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 76
- 238000002955 isolation Methods 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 15
- 238000000605 extraction Methods 0.000 claims description 14
- 230000005669 field effect Effects 0.000 claims description 5
- 230000005684 electric field Effects 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7812—Vertical DMOS transistors, i.e. VDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、誘電体分離基板を利
用した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a dielectric isolation substrate.
【０００２】[0002]
【従来の技術】従来、図５にみるように、ｐｎ接合構造
の半導体装置５１がある。半導体装置５１のｐｎ接合
は、誘電体分離基板（以下、適宜「ＤＩ基板」と言う）
５２の単結晶シリコンからなるｎ型分離島（半導体分離
島）５３に作り込まれている。ＤＩ基板は、通常、ポリ
シリコン層（支持体層）５５上に絶縁膜５４で電気的に
分離された複数のｎ型分離島５３が形成されてなる基板
であり、異なるｎ型分離島に作り込まれた半導体素子同
士の間では相互干渉が起こり難いという利点がある。2. Description of the Related Art Conventionally, as shown in FIG. 5, there is a semiconductor device 51 having a pn junction structure. The pn junction of the semiconductor device 51 is a dielectric isolation substrate (hereinafter, appropriately referred to as a “DI substrate”).
52 are formed in n-type isolation islands (semiconductor isolation islands) 53 made of single crystal silicon. The DI substrate is usually a substrate in which a plurality of n-type isolated islands 53 electrically separated by an insulating film 54 are formed on a polysilicon layer (support layer) 55, and formed on different n-type isolated islands. There is an advantage that mutual interference hardly occurs between the embedded semiconductor elements.
【０００３】半導体装置５１では、ｎ型分離島５３の表
面部分にはｐ型領域（第２導電型半導体領域）５８が形
成されていて、ｎ型分離島５３の底面部分と全側面部分
にはｎ+ 型領域５９が絶縁膜５４沿いに分離島表面まで
延びて露出するように形成されており、かつ、ｎ型分離
島５３表面では、ｐ型領域５８にコンタクトする電極６
１とｎ+ 型領域５９にコンタクトする電極６２のそれぞ
れが絶縁層５７を介して延びてゆき分離島外に引き出さ
れている。In the semiconductor device 51, a p-type region (second conductivity type semiconductor region) 58 is formed on the surface of the n-type isolation island 53, and is formed on the bottom surface and all side surfaces of the n-type isolation island 53. An n + type region 59 is formed so as to extend to the surface of the isolation island along the insulating film 54 and is exposed, and on the surface of the n type isolation island 53, the electrode 6 in contact with the p type region 58 is formed.
Each of the electrodes 62 contacting the 1 and n + -type regions 59 extends through the insulating layer 57 and is drawn out of the isolation island.
【０００４】しかしながら、この半導体装置５１はｐｎ
接合の耐圧が十分でない。これは、アルミニウム製の電
極６１がｎ+ 型領域５９の露出面（露出領域）と交差
（絶縁層を介して）しているからである。この状態だと
ｎ型分離島５３表面ではｐ型領域５８用の電極６１に沿
って空乏層がｎ+ 型領域５９に達して電界が集中し、余
り高くない電圧でもブレークダウンが起こるからであ
る。However, this semiconductor device 51 has a pn
The withstand voltage of the joint is not enough. This is because the aluminum electrode 61 intersects (via an insulating layer) the exposed surface (exposed region) of the n + type region 59. In this state, on the surface of the n-type isolation island 53, the depletion layer reaches the n + -type region 59 along the electrode 61 for the p-type region 58, the electric field is concentrated, and breakdown occurs even at a voltage that is not too high. .
【０００５】このような電極６１とｎ+ 型領域５９の交
差状態は誘電体分離基板５２の製造過程でｎ+ 型領域５
９を作り込むことに起因しているのであるが、電極６１
とｎ + 型領域５９の交差を回避することは中々困難であ
る。[0005] Such an electrode 61 and n+Intersection of mold area 59
The difference state is n during the manufacturing process of the dielectric isolation substrate 52.+Mold area 5
9 because the electrodes 61
And n +It is very difficult to avoid the intersection of the mold regions 59.
You.
【０００６】[0006]
【発明が解決しようとする課題】この発明は、上記事情
に鑑み、分離島外に引き出されるコンタクト用の電極と
第１導電型不純物高濃度領域の交差に起因する耐圧低下
が交差解消を伴わずに回避できている高耐圧の半導体装
置を提供することを課題とする。SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to reduce the breakdown voltage caused by the intersection between the contact electrode drawn out of the isolated island and the first conductive type impurity high concentration region without eliminating the intersection. It is an object of the present invention to provide a high breakdown voltage semiconductor device which can be avoided.
【０００７】[0007]
【課題を解決するための手段】前記課題を解決するた
め、この発明にかかる半導体装置では、支持体層上に絶
縁膜で電気的に分離された第１導電型半導体分離島が形
成されてなる誘電体分離基板を備え、前記半導体分離島
の表面部分に第２導電型半導体領域が形成されていて、
前記半導体分離島の底面部分と側面部分には第１導電型
不純物高濃度領域が絶縁膜沿いに分離島表面まで延びて
露出するように形成されており、かつ、前記分離島表面
では、前記第２導電型半導体領域にコンタクトする電極
と前記第１導電型不純物高濃度領域にコンタクトする電
極のそれぞれが絶縁層を介して分離島外に引き出されて
いる半導体装置において、前記第２導電型半導体領域用
の電極の下方の絶縁層中に電極の引出方向に沿って複数
個のフローティング電極が飛び飛びに設けられていると
ともに、このフローティング電極は第２導電型半導体領
域用の電極よりも幅広で同電極の両縁からはみ出した状
態となっている構成を特徴とする。In order to solve the above-mentioned problems, in a semiconductor device according to the present invention, a first conductive type semiconductor isolated island electrically separated by an insulating film is formed on a support layer. A dielectric isolation substrate, wherein a second conductivity type semiconductor region is formed on a surface portion of the semiconductor isolation island;
A first conductivity type impurity high-concentration region is formed on a bottom portion and a side portion of the semiconductor isolation island so as to extend to the surface of the isolation island along the insulating film and to be exposed. In the semiconductor device, each of an electrode contacting the two-conductivity-type semiconductor region and an electrode contacting the first-conductivity-type high-concentration impurity region is led out of the isolation island via an insulating layer. A plurality of floating electrodes are provided at intervals in the insulating layer below the electrode for use in the lead-out direction of the electrode, and the floating electrode is wider and wider than the electrode for the second conductive type semiconductor region. Is characterized in that it protrudes from both edges.
【０００８】この発明の場合、第１導電型がｎ型である
場合は第２導電型がｐ型であり、第１導電型がｐ型であ
る場合は第２導電型がｎ型である。この発明の半導体装
置の具体的な種類としては、ｐｎ接合構造（ダイオー
ド）や絶縁ゲート型電界効果構造などが挙げられるが、
これ以外の種類のものであってもよいことは言うまでも
ない。この発明の半導体装置のフローティング電極用の
材料としては、例えば、ポリシリコンが挙げられるが、
これに限らない。In the present invention, when the first conductivity type is n-type, the second conductivity type is p-type, and when the first conductivity type is p-type, the second conductivity type is n-type. Specific types of the semiconductor device of the present invention include a pn junction structure (diode) and an insulated gate field effect structure.
It goes without saying that other types may be used. Examples of the material for the floating electrode of the semiconductor device of the present invention include polysilicon.
Not limited to this.
【０００９】この発明において、半導体装置が第２導電
型半導体領域をチャネル形成用とする絶縁ゲート型電界
効果半導体装置である場合、前記第２導電型半導体領域
の表面部分にソース領域用の第１導電型半導体領域が形
成されており、第１導電型不純物高濃度領域がドレイン
領域用であって、かつ、分離島表面では、ゲート電極が
絶縁層を介して設けられていて、第２導電型半導体領域
用の電極はソース領域用の第１導電型半導体領域にもコ
ンタクトしてソース電極となっており、かつ、前記ゲー
ト電極の引出電極が絶縁層を介して分離島外に引き出さ
れていて、前記引出電極の下方の絶縁膜中にも電極の引
出方向に沿って複数個のフローティング電極が飛び飛び
に設けられているとともに、このフローティング電極も
引出電極よりも幅広で引出電極の両縁からはみ出した状
態となっている形態が有用である。In the present invention, when the semiconductor device is an insulated gate field effect semiconductor device using the second conductivity type semiconductor region for forming a channel, a first portion for a source region is provided on a surface portion of the second conductivity type semiconductor region. A conductive type semiconductor region is formed, the first conductive type impurity high concentration region is for a drain region, and a gate electrode is provided on an isolated island surface via an insulating layer. The electrode for the semiconductor region is also in contact with the first conductivity type semiconductor region for the source region to serve as a source electrode, and the lead electrode of the gate electrode is led out of the isolation island via an insulating layer. In the insulating film below the extraction electrode, a plurality of floating electrodes are provided at intervals along the extraction direction of the electrode, and the floating electrode is also wider than the extraction electrode. Form in a state of protruding from both edges of the lead electrode in are useful.
【００１０】[0010]
【作用】この発明の半導体装置では、第１導電型不純物
高濃度領域と交差している第２導電型半導体領域用の電
極の下方の絶縁層中には幅広のフローティング電極が飛
び飛びに設けられており、長く延びてゆく電極の各位置
に応じて電界が非常に旨く緩和されるためにブレークダ
ウンが起こり難くなる。フローティング電極は第２導電
型半導体領域用の電極よりも幅広で同電極の両縁からは
み出した状態でないと必要な電界緩和作用を発揮するこ
とができない。また、フローティング電極が飛び飛びで
なく全体でひとつの電極になっていたとすると、長く延
びてゆく電極の各位置に応じた適切な電界緩和作用を発
揮することができない。この結果、第１導電型不純物高
濃度領域と第２導電型半導体領域用の電極との交差が解
消されなくても耐圧が向上するようになる。In the semiconductor device according to the present invention, a wide floating electrode is provided in the insulating layer below the electrode for the second conductivity type semiconductor region intersecting with the high impurity concentration region of the first conductivity type. In addition, the electric field is remarkably relaxed in accordance with each position of the electrode extending long, so that breakdown is unlikely to occur. The floating electrode is wider than the electrode for the second conductivity type semiconductor region and cannot exert the necessary electric field relaxation action unless it is protruded from both edges of the electrode. Also, if the floating electrode is not one step but one electrode as a whole, it is not possible to exert an appropriate electric field relaxation action according to each position of the electrode extending long. As a result, the breakdown voltage is improved even if the intersection between the first conductivity type impurity high concentration region and the electrode for the second conductivity type semiconductor region is not eliminated.
【００１１】この発明において半導体装置が第２導電型
半導体領域をチャネル形成用とする絶縁ゲート型電界効
果半導体装置である場合、ゲート電極用の引出電極もソ
ース電極と余り変わらない電位となる上に第１導電型不
純物高濃度領域と交差もしており、ゲート電極用の引出
電極の下方の絶縁層中にも幅広のフローティング電極が
飛び飛びに設けられていれば、ゲート電極用の引出電極
に関しても上の場合と同様にブレークダウンが起こり難
くなる。In the present invention, when the semiconductor device is an insulated gate field effect semiconductor device using the second conductivity type semiconductor region for forming a channel, the potential of the extraction electrode for the gate electrode is not much different from that of the source electrode. It also intersects with the first conductivity type impurity high concentration region, and if a wide floating electrode is provided in the insulating layer below the gate electrode lead electrode, the gate electrode lead electrode is also raised. As in the case of the above, breakdown is unlikely to occur.
【００１２】[0012]
【実施例】以下、この発明の半導体装置にかかる実施例
を図面を参照しながら詳しく説明する。勿論、この発明
は下記の実施例に限らない。 −実施例１− 図１は、実施例１の半導体装置の要部構成を断面した状
態であらわし、図２は、実施例１の半導体装置の要部構
成を上方より絶縁層は透視して見た状態であらわす。実
施例１はダイオード等に用いられるｐｎ接合構造を有す
る半導体装置である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a semiconductor device according to the present invention; Of course, the present invention is not limited to the following embodiments. Example 1 FIG. 1 shows a cross-sectional view of a main part configuration of a semiconductor device of a first embodiment, and FIG. 2 shows a main part configuration of the semiconductor device of the first embodiment viewed through an insulating layer from above. It is expressed in a state. Example 1 is a semiconductor device having a pn junction structure used for a diode or the like.
【００１３】実施例１の半導体装置１のｐｎ接合は、Ｄ
Ｉ基板２の単結晶シリコンからなるｎ型分離島３に作り
込まれている。ＤＩ基板２は、ポリシリコン層（支持体
層）５上に絶縁膜４で電気的に分離された複数のｎ型分
離島３が形成されてなる基板である。半導体装置１にお
けるｎ型分離島３の表面部分にｐ型領域６が形成されて
いて、ｐｎ接合構造になっており、さらに、ｎ型分離島
３の底面部分と側面部分には全面的にｎ+ 型領域（第１
導電型不純物高濃度領域）１３が絶縁膜４沿いに分離島
表面まで延びて露出するように形成されている。一方、
ｎ型分離島３表面では、ｐ型領域（第２導電型半導体領
域）６にコンタクトするアルミニウム製の電極１１とｎ
+ 型領域１３にコンタクトするアルミニウム製の電極１
２とが絶縁層７を介して分離島外に引き出されている。The pn junction of the semiconductor device 1 of the first embodiment
The n-type isolation island 3 made of single-crystal silicon of the I-substrate 2 is formed. The DI substrate 2 is a substrate in which a plurality of n-type isolation islands 3 electrically separated by an insulating film 4 are formed on a polysilicon layer (support layer) 5. The p-type region 6 is formed on the surface of the n-type isolation island 3 in the semiconductor device 1 to form a pn junction structure. + Type region (first
A conductive impurity high concentration region (13) is formed so as to extend to the surface of the isolation island along the insulating film 4 and to be exposed. on the other hand,
On the surface of the n-type isolation island 3, an aluminum electrode 11 which contacts the p-type region (second conductivity type semiconductor region) 6 and n
Aluminum electrode 1 contacting + type region 13
2 are drawn out of the isolated island via the insulating layer 7.
【００１４】そして、図１にみるように、ｐ型領域６用
の電極１１の下方の絶縁層７中には電極の延びる方向に
沿って複数個のポリシリコン製のフローティング電極１
８，１８・・が飛び飛びに設けられており、各フローテ
ィング電極１８は、図２にみるように、電極１１よりも
幅広で電極１１の両縁からはみ出した状態となってい
て、ｐ型領域６用の電極１１とｎ+ 型領域１３の交差状
態が解消されずとも、電極１１が負の電位となるように
電圧が印加された場合、前述の如くに電界が緩和され電
極１１の直下のｐ型領域６−ｎ+ 型領域１３の間の電界
分布が均一化されて耐圧が高まることになるのである。As shown in FIG. 1, a plurality of polysilicon floating electrodes 1 are provided in the insulating layer 7 below the electrode 11 for the p-type region 6 along the direction in which the electrodes extend.
. Are provided at intervals, and each floating electrode 18 is wider than the electrode 11 and protrudes from both edges of the electrode 11 as shown in FIG. Even if the crossing state between the electrode 11 and the n + -type region 13 is not resolved, when a voltage is applied so that the electrode 11 has a negative potential, the electric field is relaxed as described above and p The electric field distribution between the mold regions 6-n + -type regions 13 is made uniform, and the breakdown voltage is increased.
【００１５】−実施例２− 図３は、実施例２の半導体装置にかかるDMOS-FETの要部
構成を断面した状態であらわし、図４は実施例２のDMOS
-FETの要部構成を上方より絶縁層は透視して見た状態で
あらわす。DMOS-FET２０は、ＤＩ基板２における単結晶
シリコンのｎ型分離島（半導体分離島）３に作り込まれ
ている。ＤＩ基板２は、通常、ポリシリコン層（支持体
層）５上に絶縁膜４で電気的に分離された複数のｎ型分
離島３が形成されてなる基板である。Embodiment 2 FIG. 3 shows a cross-sectional view of a main part configuration of a DMOS-FET according to a semiconductor device of Embodiment 2, and FIG.
-Represents the configuration of the main part of the FET as viewed through the insulating layer from above. The DMOS-FET 20 is formed in an n-type isolated island (semiconductor isolated island) 3 of single crystal silicon in the DI substrate 2. The DI substrate 2 is usually a substrate in which a plurality of n-type isolation islands 3 electrically separated by an insulating film 4 are formed on a polysilicon layer (support layer) 5.
【００１６】DMOS-FET２０は、ＤＩ基板２のｎ型分離島
３の表面部分にチャネル形成用のｐ型領域（第２導電型
半導体領域）２１が形成され、このｐ型領域２１の表面
部分にソース領域用のｎ型領域２２が形成され、ｎ型分
離島３の底面部分と側面部分にはドレイン領域用のｎ+
型領域（第１導電型不純物高濃度領域）２４が絶縁膜４
沿いに分離島表面まで延びて露出するように形成されて
いる。一方、ｎ型分離島３の表面では、ｐ型領域２１の
一部とソース領域であるｎ型領域２２の両方にコンタク
トしているソース電極３１とｎ+ 型領域２４にコンタク
トするドレイン電極３３とが絶縁層２７を介して分離島
外に引き出された構成になっているのに加えて、ゲート
電極２６がゲート絶縁膜２７ａを介して設けられている
とともにゲート電極２６の引出電極３３が絶縁層２７を
介して分離島外に引き出されていいる。電極３１〜３３
はアルミニウム製である。In the DMOS-FET 20, a p-type region (second conductivity type semiconductor region) 21 for forming a channel is formed on the surface of the n-type isolation island 3 of the DI substrate 2, and the surface of the p-type region 21 is formed on the surface. An n-type region 22 for the source region is formed, and n +
Mold region (first conductivity type impurity high concentration region) 24 is insulating film 4
It is formed so as to extend along the island to the surface of the isolated island. On the other hand, on the surface of the n-type isolation island 3, a source electrode 31 in contact with both a part of the p-type region 21 and the n-type region 22 as a source region and a drain electrode 33 in contact with the n + -type region 24 are provided. Is drawn out of the isolated island via the insulating layer 27, the gate electrode 26 is provided via the gate insulating film 27a, and the lead electrode 33 of the gate electrode 26 is connected to the insulating layer. It is drawn out of the isolated island via 27. Electrodes 31-33
Is made of aluminum.
【００１７】DMOS-FET２０ではゲート電極２６の電圧を
制御することにより、ｐ型領域２１の表面でチャネルの
生成・消滅が起こるようになっていることは従来の通り
である。そして、このDMOS-FET２０の場合、図３にみる
ように、ｐ型領域２１用の電極であるソース電極３１の
下方の絶縁層２７中には電極の延びる方向に沿って複数
個のポリシリコン製のフローティング電極２８，２８・
・が飛び飛びに設けられており、このフローティング電
極２８は、図４にみるように、ソース電極３１よりも幅
広であってソース電極３１の両縁からはみ出した状態と
なっていて、ソース電極３１とｎ+ 型領域２４が交差状
態であっても、ソース電極３１が負の電位となるように
電圧が印加された場合、前述の如く電界が緩和されソー
ス電極３１の直下のｐ型領域２１−ｎ+ 型領域２４の間
の電界分布が均一化されて耐圧が高まる。さらに、この
DMOS-FET２０の場合、図３にみるように、ゲート電極２
６用の引出電極３３の下方の絶縁層２７中にも電極の延
びる方向に沿って複数個のポリシリコン製のフローティ
ング電極２９，２９・・が飛び飛びに設けられており、
このフローティング電極２９は、図４にみるように、引
出電極３３よりも幅広であって引出電極３３の両縁から
はみ出した状態となっていて、引出電極３３とｎ+ 型領
域２４が交差状態であっても、引出電極３３が負の電位
となるように電圧が印加された場合、やはり電界が緩和
され引出電極３３の直下のｐ型領域２１−ｎ+ 型領域２
４の間の電界分布が均一化されて耐圧低下の心配がない
のである。実施例２のように、フローティング電極２９
がポリシリコ製である場合には、フローティング電極２
９ゲート電極２６の同時形成が可能であるという利点が
ある。In the DMOS-FET 20, by controlling the voltage of the gate electrode 26, a channel is generated and annihilated on the surface of the p-type region 21 as in the prior art. In the case of this DMOS-FET 20, as shown in FIG. 3, a plurality of polysilicon layers are formed in the insulating layer 27 below the source electrode 31 which is the electrode for the p-type region 21 along the direction in which the electrodes extend. Floating electrodes 28, 28
4, the floating electrode 28 is wider than the source electrode 31 and protrudes from both edges of the source electrode 31, as shown in FIG. Even when the n + -type regions 24 are in a crossing state, when a voltage is applied so that the source electrode 31 has a negative potential, the electric field is relaxed as described above, and the p-type regions 21-n just below the source electrode 31 are reduced. The electric field distribution between the + type regions 24 is made uniform, and the breakdown voltage is increased. Furthermore, this
In the case of the DMOS-FET 20, as shown in FIG.
A plurality of polysilicon floating electrodes 29, 29,... Are also provided in the insulating layer 27 below the extraction electrode 33 for 6 in the direction in which the electrodes extend.
As shown in FIG. 4, the floating electrode 29 is wider than the extraction electrode 33 and protrudes from both edges of the extraction electrode 33, and the extraction electrode 33 and the n + -type region 24 intersect each other. Even when the voltage is applied such that the extraction electrode 33 has a negative potential, the electric field is also relaxed and the p-type region 21-n + type region 2 immediately below the extraction electrode 33 is applied.
4, the electric field distribution is uniformed, and there is no fear of a decrease in breakdown voltage. As in the second embodiment, the floating electrode 29
Is made of polysilico, the floating electrode 2
There is an advantage that simultaneous formation of the nine gate electrodes 26 is possible.
【００１８】[0018]
【発明の効果】以上に述べたように、この発明にかかる
半導体装置の場合、第１導電型不純物高濃度領域と交差
している第２導電型半導体領域用の電極やゲート電極用
の引出電極の下方の絶縁層中に飛び飛びに設けられた幅
広のフローティング電極により、長く延びてゆく電極の
各位置に合わせて電界がうまく緩和されるためにブレー
クダウンが起こり難くなり、第１導電型不純物高濃度領
域と第２導電型半導体領域用の電極やゲート電極用の引
出電極との交差を解消せずとも、耐圧向上が図れるの
で、この発明は非常に有用である。As described above, in the case of the semiconductor device according to the present invention, the electrode for the second conductivity type semiconductor region and the extraction electrode for the gate electrode crossing the first conductivity type high impurity concentration region. Wide floating electrodes are provided in the insulating layer below the gate electrode, so that the electric field is appropriately relaxed in accordance with each position of the elongated electrode, so that breakdown is unlikely to occur, and the first conductivity type impurity The present invention is very useful because the withstand voltage can be improved without eliminating the intersection between the concentration region and the electrode for the second conductivity type semiconductor region or the extraction electrode for the gate electrode.
【図１】実施例１の半導体装置の要部構成をあらわす断
面図。FIG. 1 is a cross-sectional view illustrating a configuration of a main part of a semiconductor device according to a first embodiment.
【図２】実施例１の半導体装置の要部構成をあらわす平
面図。FIG. 2 is a plan view illustrating a configuration of a main part of the semiconductor device according to the first embodiment.
【図３】実施例２の半導体装置の要部構成をあらわす断
面図。FIG. 3 is a cross-sectional view illustrating a main part configuration of a semiconductor device according to a second embodiment.
【図４】実施例２の半導体装置の要部構成をあらわす平
面図。FIG. 4 is a plan view illustrating a configuration of a main part of a semiconductor device according to a second embodiment.
【図５】従来の半導体装置の要部構成をあらわす断面
図。FIG. 5 is a cross-sectional view illustrating a configuration of a main part of a conventional semiconductor device.
【符号の説明】 １ 半導体装置 ２ ＤＩ基板（誘電体分離基板） ３ ｎ型分離島（半導体分離島） ４ 絶縁膜 ５ ポリシリコン層（支持体層） ６ ｐ型領域（第２導電型半導体領域） ７ 絶縁層 １１ 電極 １２ 電極 １３ ｎ+ 型領域（第１導電型不純物高濃度領域） １８ フローティング電極 ２０ DMOS-FET（絶縁ゲート型電界効果半導体装置） ２１ チャネル領域用のｐ型領域 ２２ ソース領域用のｎ型領域 ２４ ドレイン領域用のｎ+ 型領域（第１導電型不純物
高濃度領域） ２６ ゲート電極 ２８ フローティング電極 ２９ フローティング電極 ３１ ソース電極 ３２ ドレイン電極 ３３ 引出電極[Description of Symbols] 1 semiconductor device 2 DI substrate (dielectric isolation substrate) 3 n-type isolation island (semiconductor isolation island) 4 insulating film 5 polysilicon layer (support layer) 6 p-type region (second conductivity type semiconductor region) 7) Insulating layer 11 Electrode 12 Electrode 13 N + type region (first conductivity type impurity high concentration region) 18 Floating electrode 20 DMOS-FET (Insulated gate type field effect semiconductor device) 21 P type region for channel region 22 Source region N-type region 24 n + -type region for drain region (first conductive type impurity high concentration region) 26 gate electrode 28 floating electrode 29 floating electrode 31 source electrode 32 drain electrode 33 extraction electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉浦 義幸 大阪府門真市大字門真1048番地松下電工 株式会社内 (56)参考文献 特開 平２−248078（ＪＰ，Ａ) 特開 平４−260373（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 29/06 H01L 29/78 H01L 29/861 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yoshiyuki Sugiura 1048 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd. (56) References JP-A-2-248078 (JP, A) JP-A-4-260373 ( JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 29/06 H01L 29/78 H01L 29/861
Claims (2)
た第１導電型半導体分離島が形成されてなる誘電体分離
基板を備え、前記半導体分離島の表面部分に第２導電型
半導体領域が形成されていて、前記半導体分離島の底面
部分と側面部分には第１導電型不純物高濃度領域が絶縁
膜沿いに分離島表面まで延びて露出するように形成され
ており、かつ、前記分離島表面では、前記第２導電型半
導体領域にコンタクトする電極と前記第１導電型不純物
高濃度領域にコンタクトする電極のそれぞれが絶縁層を
介して分離島外に引き出されている半導体装置におい
て、前記第２導電型半導体領域用の電極の下方の絶縁層
中に電極の引出方向に沿って複数個のフローティング電
極が飛び飛びに設けられているとともに、このフローテ
ィング電極は第２導電型半導体領域用の電極よりも幅広
で同電極の両縁からはみ出した状態となっていることを
特徴とする半導体装置。1. A semiconductor device according to claim 1, further comprising a dielectric isolation substrate having a first conductive type semiconductor isolation island electrically separated by an insulating film formed on the support layer, wherein a second conductivity type semiconductor isolation island is provided on a surface portion of the semiconductor isolation island. A semiconductor region is formed, a first conductivity type impurity high concentration region is formed on a bottom surface portion and a side surface portion of the semiconductor isolation island so as to extend to the isolation island surface along the insulating film and to be exposed; In the semiconductor device, on the surface of the isolated island, each of an electrode contacting the second conductivity type semiconductor region and an electrode contacting the first conductivity type impurity high concentration region is drawn out of the isolation island via an insulating layer. A plurality of floating electrodes are provided in the insulating layer below the electrode for the second conductivity type semiconductor region in a drawing direction of the electrodes, and the floating electrodes are formed of the second conductive type. A semiconductor device characterized by being wider than an electrode for a mold semiconductor region and protruding from both edges of the electrode.
ャネル形成用とする絶縁ゲート型電界効果半導体装置で
あり、前記第２導電型半導体領域の表面部分にソース領
域用の第１導電型半導体領域が形成されており、第１導
電型不純物高濃度領域がドレイン領域用であって、か
つ、分離島表面では、ゲート電極が絶縁層を介して設け
られていて、第２導電型半導体領域用の電極はソース領
域用の第１導電型半導体領域にもコンタクトしてソース
電極となっており、かつ、前記ゲート電極の引出電極が
絶縁層を介して分離島外に引き出されていて、前記引出
電極の下方の絶縁膜中にも電極の引出方向に沿って複数
個のフローティング電極が飛び飛びに設けられていると
ともに、このフローティング電極も引出電極よりも幅広
で引出電極の両縁からはみ出した状態となっている請求
項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor device is an insulated gate field effect semiconductor device using a second conductivity type semiconductor region for forming a channel, and a first conductivity type semiconductor for a source region is provided on a surface portion of the second conductivity type semiconductor region. A region is formed, the first-conductivity-type high-concentration impurity-concentration region is for a drain region, and a gate electrode is provided on the surface of the isolation island via an insulating layer, and The first electrode is also in contact with the first conductivity type semiconductor region for the source region to serve as a source electrode, and the extraction electrode of the gate electrode is extended out of the isolation island via an insulating layer. In the insulating film below the electrodes, a plurality of floating electrodes are provided at intervals in the direction in which the electrodes are drawn, and this floating electrode is also wider than the lead electrodes and extends from both edges of the lead electrodes. 2. The semiconductor device according to claim 1, wherein the semiconductor device protrudes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP797193A JP2883779B2 (en) | 1993-01-20 | 1993-01-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP797193A JP2883779B2 (en) | 1993-01-20 | 1993-01-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06216231A JPH06216231A (en) | 1994-08-05 |
| JP2883779B2 true JP2883779B2 (en) | 1999-04-19 |
Family
ID=11680356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP797193A Expired - Lifetime JP2883779B2 (en) | 1993-01-20 | 1993-01-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2883779B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4906281B2 (en) * | 2005-03-30 | 2012-03-28 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device |
| JP5565309B2 (en) | 2010-12-29 | 2014-08-06 | 三菱電機株式会社 | Semiconductor device |
-
1993
- 1993-01-20 JP JP797193A patent/JP2883779B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06216231A (en) | 1994-08-05 |
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