JP3152290B2 - Method for manufacturing semiconductor device including capacitive element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitive coupling field plate for improving a breakdown voltage of a field effect transistor in a semiconductor device including an insulated gate field effect transistor and another semiconductor element. .

[0002]

2. Description of the Related Art One semiconductor substrate may be provided with both an insulated gate field effect transistor and another semiconductor element for controlling the field effect transistor.
Another semiconductor element is arranged close to the field effect transistor in order to reduce the size. In order to prevent a depletion layer generated due to the operation of the field effect transistor from affecting another semiconductor element, a buried region for blocking a depletion layer is formed in a portion of the semiconductor substrate corresponding to a region below another semiconductor element formation region. May be provided. When the buried region for blocking the depletion layer is provided, the depletion layer spreads so as to have a step portion, and the smoothness deteriorates. Therefore, a field plate effect is used to smoothly change the depletion layer. When the field plate is coupled to the drain electrode, it may be coupled via a capacitance (capacitor). In this case, by controlling the position of the field plate (conductor layer), the shape of the depletion layer formed based on the field plate can be controlled, and a depletion layer having a desired shape for improving the breakdown voltage can be obtained.

[0003]

As a method of forming a field plate connected by a capacitance, the method shown in FIGS. 1 to 4 can be considered. In this method, first, as shown in FIG. 1, a silicon oxide layer 2 is formed on a silicon semiconductor substrate 1 including various semiconductor regions for an insulated gate field effect transistor by a thermal oxidation method. Next, as shown in FIG. 2, a polysilicon (polycrystalline silicon) layer 3 to which an impurity is added for giving conductivity is formed on the silicon oxide layer 2 according to the shape of the field plate. The polysilicon layer 3 is obtained by forming the entire upper surface of the silicon oxide layer 2 and then etching it into a predetermined pattern. Next, the surface region of the polysilicon layer 3 is thermally oxidized to obtain the silicon oxide layer 4 shown in FIG. Next, a pair of polysilicon layers 5 and 6 to which impurities giving conductivity are added are formed on the silicon oxide layers 2 and 4. The pair of polysilicon layers 5 and 6 are formed all over the substrate 1, and the isolation region 6 is provided by etching. Further, one polysilicon layer 5 is connected to, for example, a drain electrode, and the other polysilicon layer 6 is connected to ground via another capacitive coupling field plate. In FIG. 4, the polysilicon layers 3, 5, and 6 function as conductive layers, and the silicon oxide layer 4 functions as a dielectric layer.
Therefore, the silicon oxide layer 4, the lower polysilicon layer 3, and the upper polysilicon layers 5, 6 constitute two capacitive elements. By the way, in the method shown in FIGS. 1 to 4, the silicon oxide layer 4 becomes thinner on the side surface than the upper surface of the polysilicon layer 3, and the side surface of the polysilicon layer 3 jumps up. It is difficult to reliably increase the breakdown voltage between the silicon layer 3 and the pair of polysilicon layers 5 and 6 on the silicon oxide layer 4 with reliability. When the polysilicon layer 3 is thermally oxidized, not only the upper surface and the side surface of the polysilicon layer 3 but also the lower surface near the side surface are oxidized. This is considered to be caused by the lifting action caused by the further progress of the oxidation of the silicon oxide layer 2 on the surface of the substrate 1. In order to solve the above problem, it is conceivable that the polysilicon layer 3 is strongly oxidized to form a thick silicon oxide layer 4. However, when the thickness of the silicon oxide layer 4 is increased, the step between the upper surface of the silicon oxide layer 4 and the surface of the lower silicon oxide layer 2 is increased, and the upper polysilicon layers 5 and 6 or the Processing accuracy due to etching of the conductor layer or the insulating layer other than the above is reduced. The silicon oxide layer 4
When the thickness of the polysilicon layer 3 increases, the capacitance between the lower polysilicon layer 3 and the upper polysilicon layers 5 and 6 decreases, and the fixing of the potential of the polysilicon layer 3 becomes unstable.

The object of the present invention is to provide a method of the capacitive coupling fields plates that are included in the semiconductor device can be manufactured with a high manufacturing yield.

[0005]

According to the present invention, there is provided a semiconductor device comprising: a first semiconductor region of a first conductivity type ;
A first conductivity type having a second conductivity type opposite to the first conductivity type;
Is arranged adjacent to a part of one main surface of the region; and
The first semiconductor region is reduced in thickness to reduce the thickness of the first semiconductor region.
The second half formed so as to bite into one semiconductor region
A conductive region; and a second semiconductor region having a second conductivity type.
A semiconductor region having a lower impurity concentration than the region,
When adjacent to the one main surface of the first semiconductor region,
So that the second semiconductor region becomes a buried layer.
Third semiconductor region also adjacent to second semiconductor region
And drain for insulated gate field effect transistor
Region having a second conductivity type and the third semiconductor type.
The second semiconductor having a higher impurity concentration than the body region;
Region, and the bottom surface and the side surfaces thereof are the third region.
A fourth semiconductor region adjacent to the semiconductor region;
At a position spaced apart from the second semiconductor region
When the first semiconductor region is adjacent to one main surface,
The fifth semiconductor region also adjacent to the side surface of the third semiconductor region
A semiconductor region and a second for the field effect transistor.
A source region having a conductivity type, wherein the fifth semiconductor is
Front so as to face the third semiconductor region via the region.
The sixth semiconductor formed in the fifth semiconductor region
Region and a semiconductor element different from the field effect transistor
Forming the second semiconductor region
, And the bottom surface and the side surfaces thereof are the third semiconductor.
Semiconductor region with a seventh semiconductor region adjacent to the body region
Body substrate, at least the third semiconductor region and the sixth semiconductor region.
Covering the surface of the fifth semiconductor region with the semiconductor region of
The insulating film formed as described above and the fourth semiconductor region.
The formed drain electrode is formed in the sixth semiconductor region.
The source electrode thus formed and a gate formed on the insulating film.
And a ground electrode formed in the fifth semiconductor region.
And a fourth semiconductor region of the third semiconductor region.
On the surface of the region between the region and the fifth semiconductor region
Device having a capacitively coupled field plate
Manufacturing method, wherein said capacitively coupled field play
Forming a first semiconductor layer on the third semiconductor region;
Forming a silicon oxide layer, and the first silicon
Impurities were introduced on the oxide layer to obtain conductivity
Forming a polysilicon layer, the polysilicon layer
Is thermally oxidized on the surface side of the
Forming a silicon oxide layer, and the polysilicon
Forming an anti-oxidation mask of a predetermined pattern on said in order to to leave the layer in a predetermined pattern a second silicon oxide layer, partial thermal oxidation which is not covered by the oxidation preventing mask of the polysilicon layer A third silicon oxide layer, a step of removing the antioxidant mask, and a step of opposing the polysilicon layer on the second silicon oxide layer via the second silicon oxide layer. Forming a pair of conductive layers, and connecting one of the pair of conductive layers to the drain electrode,
Connecting the other of the pair of conductive layers to the ground electrode directly or through another capacitively-coupled field plate. It is desirable that a layer having conductivity as illustrated in claim 2, polysilicon layer.

[0006]

Effects of the Invention According to the invention of each claim, the polysilicon layer leaving not removed by etching, so other than the portion to be used as the conductive layer of the full I over field plate is converted into a silicon oxide layer by oxidation, polysilicon Since the silicon oxide layer is sufficiently present on the side surfaces of the conductive layer made of a layer, a capacitive coupling field plate having a high withstand voltage can be provided, and furthermore, the surfaces of the second and third silicon oxide layers can be interconnected. The step between them can be reduced. Further, since a mask is provided on the portion where the conductive layer of polysilicon is to be obtained and thermal oxidation is performed, the second silicon oxide layer on the polysilicon layer as the conductive layer is kept relatively thin,
Large capacity can be obtained. According to the second aspect of the present invention, the capacitive coupling field plate can be formed easily and well.

[0007]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to the drawings.

FIG. 5 shows a semiconductor device 7 according to an embodiment of the present invention.
And a part corresponding to the left half of the line AA in FIG. 6 is shown. The semiconductor device 7 includes a first insulated gate field effect transistor (hereinafter, referred to as a first FET) 8 as a first semiconductor element having a relatively large power capacity, and an insulated gate as a second semiconductor element. Type field effect transistor (hereinafter, referred to as a second FET) 9. The second FET 9 controls or drives the first FET 8, and is a small-signal (low-power) semiconductor element having an extremely small current capacity as compared with the first FET 8.

A common silicon semiconductor substrate or silicon semiconductor substrate 10 for forming the first and second FETs 8 and 9 includes a P-type (first conductivity type) first semiconductor region 11 as a substrate, An N-type (second conductivity type) second semiconductor region 12 as a buried layer, and a first FET 8
The third semiconductor region 13 of N-type as the drain region and the isolation region of the second FET 9, the fourth semiconductor region 1 of N ⁺ form of the drain electrode formation region of the first FET8
4, a P-type fifth semiconductor region 15 for forming a channel of the first FET 8, an N ^{+ -type} sixth semiconductor region 16 as a source region of the first FET 8, and a channel of the second FET 9 A P-type seventh semiconductor region 17 as a region,
The second FET 9 has N-type eighth and ninth semiconductor regions 18 and 19 as source and drain formation regions.

The first semiconductor region 11 is a portion serving as a substrate for epitaxial growth, and has a size of 2.5 ×
It has an impurity concentration of about 10 ¹⁴ cm ⁻³ and is provided on the entire lower side of the substrate 10. The second semiconductor region 12 is the first
Is provided substantially at the center of one main surface of the semiconductor region 11 by diffusion of an N-type impurity, and has a shape in which it penetrates below the one main surface of the first semiconductor region 11 in the thickness direction. . This second semiconductor region 12
As is apparent from FIG. 6, the seventh, eighth and ninth semiconductor regions 17, 18, 1
9 and a fourth semiconductor region 14 for the first FET 8
And below it in the cross section of FIG. This second semiconductor region 12
It has a function of preventing a depletion layer generated based on the operation of the first FET 8 from extending to the P-type seventh semiconductor region 17 of the second FET 9, and has an impurity concentration of the third semiconductor region 13. It has an impurity concentration (for example, 6 × 10 ¹⁵ cm ⁻³ ) higher than (for example, 1 × 10 ¹⁵ cm ⁻³ ). The N-type third semiconductor region 13 is a region epitaxially grown on the P-type first semiconductor region 11, and has a lower surface in contact with the first and second semiconductor regions 11 and 12. This third
Semiconductor region 13 functions as a drain region of the first FET 8 and also functions as an isolation region of the second FET 9 by a PN junction, has a portion exposed on the surface of the substrate 10, and And a portion interposed between the seventh semiconductor region 17 and the second semiconductor region 12.

The N ^{+ type} fourth semiconductor region 14 has a first F
A region formed by impurity diffusion in the N-type third semiconductor region 13 for connection of the drain electrode of the ET 8, having a higher impurity concentration than the third semiconductor region 13, It is arranged above the area 12. That is, it is formed in an annular shape so as to fit in the second semiconductor region 12 when viewed in plan. Note that the fourth semiconductor region 14 is exposed on the surface of the substrate 10, and the bottom surface and side surfaces are surrounded by the third semiconductor region 13. The fourth semiconductor region 14 concentrically surrounds the seventh, eighth, and ninth semiconductor regions 17, 18, and 19 for the second FET 9 in plan view. The P-type fifth semiconductor region 15 as a channel forming region or a body region of the first FET 8 is a region formed by diffusing a P-type impurity into the N-type third semiconductor region 13, and First from the surface of 10
And is arranged so as to annularly surround the third semiconductor region 13 and the sixth semiconductor region 16 in plan view. Therefore, the N-type third
The side surface of the semiconductor region 13 is a P-type fifth semiconductor region 15.
Is in contact with N as a source region of the first FET 8
^{The + -type} sixth semiconductor region 16 is formed in a ring shape by diffusing an N-type impurity into the P-type fifth semiconductor region 15, and the fifth semiconductor region 15 for obtaining a channel region is formed. And the third semiconductor region 13 functioning as a drain region.

The P-type seventh semiconductor region 17 serving as a channel region or a body region of the second FET 9 having a smaller current capacity and power capacity than the first FET 8 has a P-type conductivity from the surface side of the third semiconductor region 13. Region formed by diffusing an impurity in the shape of
It is formed annularly inside the fourth semiconductor region 14 for T8, and is arranged on the second semiconductor region 12 in the cross-sectional view of FIG. The PN junction between the P-type seventh semiconductor region 17 and the N-type third semiconductor region 13 has a function of electrically separating the second FET 9 from the first FET 8. Eighth semiconductor region 18 of second FET 9
Is a portion that functions as a source region, and the ninth semiconductor region 19 is a portion that functions as a drain region. The ninth semiconductor region 19 is formed by diffusing an N-type impurity into the seventh semiconductor region 17. It has an annular planar pattern as shown.

To form the first FET 8, a drain electrode 21, a ground electrode 22, and a source electrode 23 are formed on the surface of the semiconductor substrate 10, ie, on the fourth, fifth and sixth semiconductor regions 14, 15, and 16. Are provided annularly. Further, the N ^{+ type} sixth semiconductor region 16 and the N type third
P-type fifth semiconductor region 15 between semiconductor region 13 of FIG.
A gate electrode 25 is provided annularly on the surface of the substrate with an insulating film 24 interposed therebetween.

In order to obtain a good field plate effect, first silicon is provided on the surface of the third semiconductor region 13 at the portion between the N ^{+ -type} fourth semiconductor region 14 and the fifth semiconductor region 15. An oxide layer 26 is provided on which the first, second, and third field plate conductor layers 27a,
27b and 27c are arranged. Each of the field plate conductor layers 27a, 27b, 27c is formed in an annular shape as shown by a chain line in FIG. On each of the field plate conductor layers 27a, 27b and 27c, a second silicon oxide layer 28 is provided as a dielectric layer for capacitive coupling. Field plate conductor layer 27a,
The side surfaces of 27b and 27c are covered with a third silicon oxide layer 29. Second and third silicon oxide layers 28, 29
Are substantially integrated, and the first, second, third and fourth upper conductor layers 30 are formed thereon so as to have portions facing the field plate conductor layers 27a, 27b and 27c.
a, 30b, 30c, and 30d are arranged. One end of the first upper conductor layer 30a is connected to the drain electrode 21, and the other end is opposed to the field plate conductor layer 27a via the second silicon oxide layer 28. One end of the second upper conductor layer 30b is connected to the first field plate conductor layer 2
7a, and the other end faces the second field plate conductor layer 27b. One end of the third upper conductor layer 30c faces the second field plate conductor layer 27b, and the other end faces the third field plate conductor layer 27c. One end of the fourth upper conductor layer 30d faces the third field plate conductor layer 27c, and the other end is connected to the ground electrode 22. Therefore, six capacitors are connected in series between the drain electrode 21 and the ground electrode 22. The connection of the fourth upper conductor layer 30d to the ground electrode 22 is performed via the metal layer 31. Upper conductor layers 30a, 30b, 30c, 3
0d is covered with an insulating protective film 32.

To configure the second FET 9 for small signals, a source electrode 33 is provided in the eighth semiconductor region 18, a drain electrode 34 is provided in the ninth semiconductor region 19, and the eighth and ninth semiconductor regions 19 are provided. A gate electrode 36 is provided on the surface of the seventh semiconductor region 17 between the semiconductor regions 18 and 19 via an insulating film 35.

A PN junction 37 is provided between the drain electrode 21 and the ground electrode 22 or the source electrode 23 of the first FET 8.
Is applied, a P-type first semiconductor region 11 and an N-type third semiconductor region 13 are applied.
The depletion layer 38 spreads along the PN junction formed at the interface as shown by the dotted line in FIG. The field plate conductor layers 27a, 27b, and 27c have a function of smoothing the depletion layer 38 and a function of stabilizing the charge on the surface of the third semiconductor region 13, and provide a function between the drain electrode 21 and the gate electrode 25. It contributes to the improvement of withstand voltage.

Incidentally, the first, second and third field plate conductor layers 27a, 27b and 27c and the first, second, third and fourth upper conductor layers 30a, 30b and 30 are provided.
It is also required that the breakdown voltage between c and 30d be high. FIG.
In the present embodiment, the first, second and third field plate conductor layers 27a, 27b and 27c are sufficiently covered with a relatively thick third silicon oxide layer 29, and the first and second field plate conductor layers 27a, 27b and 27c are sufficiently covered. Since the end of the second and third field plate conductor layers 27a, 27b, and 27c does not have a jumping phenomenon, each of the field plate conductor layers 27a,
The withstand voltage between the upper conductor layers 7b and 27c and the upper conductor layers 30a to 30d increases. The second and third silicon oxide layers 2
Since the steps of the irregularities on the surfaces of the surfaces 8 and 29 are relatively low and the flatness is good, the processing accuracy of the upper conductor layers 30a to 30d by etching can be improved.

Next, the field plate conductor layers 27a to 27a
27c, the first, second and third silicon oxide layers 26, 2
8, 29 and the method of forming the upper conductor layers 30a to 30d are shown in FIG.
This will be described with reference to FIGS. However, the first half formed by the right half of the first field plate conductor layer 27a, the second silicon oxide layer 28, and the first upper conductor layer 30a.
And the left half of the first field plate conductor layer 27a, the second and third field plate conductor layers 27b and 27c, and the second, third,
Since the method of forming the second to sixth capacitance elements formed by the fourth upper conductor layers 30b, 30c, and 30d is substantially the same, FIGS. Only shown.

First, as shown in FIG. 7, a third semiconductor region 13 made of N-type silicon having a flat surface is prepared, heated in an oxidizing atmosphere, and this surface is oxidized to obtain a structure shown in FIG. As shown, a first silicon oxide layer 26 of SiO2 is formed.

Next, as shown in FIG. 9, a first polysilicon layer 27 doped with impurities to give conductivity is formed on the first silicon oxide layer 26 by a known CVD (chemical vapor deposition). ) Method. This first polysilicon layer 27 finally becomes the first, second and third field plate conductor layers 27a, 27b, 27 shown in FIG.
c.

Next, the upper surface region is oxidized by heat-treating the polysilicon layer 27 in an oxidizing atmosphere to form a thin second silicon oxide layer 28a made of SiO ₂ as shown in FIG. The second silicon oxide layer 28a finally becomes the second silicon oxide layer 28 and the third silicon oxide layer 29 as the capacitively coupled dielectric layer of FIG.
Become a part of.

Next, after a silicon nitride film is formed on the upper surface of the second silicon oxide layer 28a by the CVD method, this is selectively etched to form a silicon nitride film mask 40 shown in FIG. This mask 40 is shown in FIG.
Are arranged corresponding to the field plate conductor layers 27a, 27b and 27c.

Next, a mask 40 made of a silicon nitride film is used.
The portion of the polysilicon layer 27 which is not covered with the mask 40 is thermally oxidized to be converted into silicon oxide made of SiO2 by using the method shown in FIG. 12, which is integrated with the second silicon oxide layer 28a of FIG. A third silicon oxide layer 29 as shown is obtained. The second silicon oxide layer 28a shown in FIG.
The oxidation of the underlying polysilicon layer 27 can be obtained by a known local oxidation method. Since the volume increases when the conductive polysilicon layer 27 is oxidized, the height position of the upper surface of the third silicon oxide layer 29 is slightly higher than the height position of the upper surface of the second silicon oxide layer 28, and 40
Edge jumps up a little. Conductive polysilicon layer 2 of FIG.
The portions not oxidized by the local oxidation of 7 become the first to third field plate conductor layers 27a to 27c in FIG. In addition, a portion of the second silicon oxide layer 28a below the mask 40 in FIG. 11 becomes the second silicon oxide layer 28 as a dielectric layer of the first to third field plate conductor layers 27a to 27c.

Next, after the mask 40 is removed by etching, as shown in FIG. 13, a conductive second polysilicon layer 30 is formed on the upper surfaces of the second and third silicon oxide layers 28 and 29 by the CVD method. Formed by This polysilicon layer 30 is a layer whose conductivity has been increased by the introduction of impurities, similarly to the polysilicon layer 27, and is for obtaining the upper conductor layers 30a to 30d of FIG.

Next, the second polysilicon layer 30 shown in FIG.
5 and FIG. 1 by selectively etching
First to fourth upper conductive layers 30a to 30d made of conductive polysilicon shown in FIG. At this time, since the steps of the second and third silicon oxide layers 28 and 29 are not so large and the surfaces of both are good in flatness, the second polysilicon layer 3
0 can improve the etching accuracy.

Finally, FIG. 5 and FIG.
An insulating protective layer 32 made of silicon oxide (SiO2) is formed as shown in FIG.

According to this embodiment, the upper and side surfaces of the end portions of the field plate conductor layers 27a to 27c are covered with the third silicon oxide layer 29 which is thicker than the second silicon oxide layer 28. Field plate conductor layer 27a
-27c and upper conductor layers 30a-30d are no longer limited by third silicon oxide layer 29 at the ends of lower field plate conductor layers 27a-27c,
High breakdown voltage between the two and improvement in reliability of electrical insulation are achieved. Further, since the thickness of the second silicon oxide layer 28 as the dielectric layer of the capacitor can be kept small, the capacitance between the two can be made relatively large, and the potential can be fixed satisfactorily. Further, the second silicon oxide layer 28
Is relatively thin, and the second and third silicon oxide layers 2
8 and 29, the upper conductor layer 30a
To 30d, and each of the electrodes 21, 22, 23, 25, 33,
Fine processing by etching such as 34 and 36 can be performed favorably.

[0028]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The number of field plate conductor layers 27a to 27c can be increased or decreased. (2) The upper conductor layers 30a to 30d can be metal layers. (3) The small signal FET 9 can be a bipolar transistor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a silicon semiconductor substrate on which a silicon oxide layer is formed for forming a capacitively-coupled field plate in a conventional semiconductor device.

FIG. 2 is a cross-sectional view showing a polysilicon layer formed on the silicon oxide layer of FIG.

FIG. 3 is a cross-sectional view showing an oxidized surface of the polysilicon layer of FIG. 2;

FIG. 4 is a cross-sectional view showing a structure in which a polysilicon layer as a conductor layer is provided on the silicon oxide layer of FIG. 3;

FIG. 5A of the semiconductor device according to the embodiment of the present invention;
It is sectional drawing which shows the part corresponding to a part of -A line.

FIG. 6 is a plan view showing a surface of a semiconductor substrate of the semiconductor device of FIG. 5;

7 is a cross-sectional view of a third semiconductor region for describing a method of manufacturing a field plate conductor layer and a capacitive coupling portion of the semiconductor device of FIG. 5;

8 is a cross-sectional view showing a third semiconductor region of FIG. 7 in which a first silicon oxide layer is formed.

9 is a cross-sectional view showing a polysilicon layer formed on the silicon oxide layer of FIG.

FIG. 10 is a sectional view showing a structure in which a second polysilicon layer is formed on the surface of the polysilicon layer of FIG. 9;

FIG. 11 is a sectional view showing a state where a mask is formed on the second silicon oxide layer of FIG. 10;

FIG. 12 is a cross-sectional view showing a locally oxidized polysilicon layer of FIG. 11;

FIG. 13 is a cross-sectional view showing a second polysilicon layer formed on the second and third silicon oxide layers of FIG. 12;

FIG. 14 is a cross-sectional view showing a state where the second polysilicon layer of FIG. 13 is selectively etched.

FIG. 15 is a cross-sectional view showing a structure in which a protective layer is provided on the second polysilicon layer of FIG.

[Explanation of symbols]

 26 first silicon oxide layer 27a-27c field plate conductor layer 28 second silicon oxide layer 29 third silicon oxide layer 30a-30d upper conductor layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 29/78 H01L 29/06 H01L 27/06 H01L 27/108

Claims (2)

(57) [Claims] 1. A first semiconductor region having a first conductivity type, a second conductivity type opposite to the first conductivity type, and adjacent to a part of one main surface of the first semiconductor region. And a second semiconductor region formed so as to bite into the first semiconductor region so as to reduce the thickness of the first semiconductor region, and having a second conductivity type, and A semiconductor region having an impurity concentration lower than that of the second semiconductor region, wherein the second semiconductor region is adjacent to the one main surface of the first semiconductor region and the second semiconductor region is a buried layer. A third semiconductor region also adjacent to the region, and a drain region for an insulated gate field effect transistor having a second conductivity type and having a higher impurity concentration than the third semiconductor region. And disposed above the second semiconductor region. A fourth semiconductor region having a bottom surface and a side surface adjacent to the third semiconductor region; and a first semiconductor region having a first conductivity type and spaced apart from the second semiconductor region. A fifth semiconductor region adjacent to one of the main surfaces and also adjacent to a side surface of the third semiconductor region; and a source region having a second conductivity type for the field effect transistor. A sixth semiconductor region formed in the fifth semiconductor region so as to face the third semiconductor region via the fifth semiconductor region, and a semiconductor different from the field effect transistor. A semiconductor substrate for forming an element, comprising: a seventh semiconductor region disposed above the second semiconductor region and having a bottom surface and side surfaces adjacent to the third semiconductor region. And at least the third An insulating film formed so as to cover a surface of the fifth semiconductor region between the semiconductor region and the sixth semiconductor region; a drain electrode formed in the fourth semiconductor region; A source electrode formed in a semiconductor region, a gate electrode formed on the insulating film, a ground electrode formed in the fifth semiconductor region, and a fourth semiconductor region of the third semiconductor region A method of manufacturing a semiconductor device comprising: a capacitively coupled field plate provided on a surface of a region between the first and fifth semiconductor regions. Forming a first silicon oxide layer on the third semiconductor region; forming a polysilicon layer doped with impurities for obtaining conductivity on the first silicon oxide layer; Poly A step of thermally oxidizing a surface side portion of the silicon layer to form a second silicon oxide layer only on the surface side portion; and a step of forming a second silicon oxide layer on the second silicon oxide layer to leave the polysilicon layer in a predetermined pattern. Forming an oxidation-prevention mask having a predetermined pattern on the substrate, a step of converting a portion of the polysilicon layer that is not covered with the oxidation-prevention mask into a third silicon oxide layer by thermal oxidation, and removing the oxidation-prevention mask. Forming a pair of conductive layers respectively facing the polysilicon layer via the second silicon oxide layer on the second silicon oxide layer, and forming the pair of conductive layers on the second silicon oxide layer. One of the conductive layers is connected to the drain electrode, and the other of the pair of conductive layers is connected to the ground electrode directly or via another capacitively coupled field plate. The method of manufacturing a semiconductor device characterized by a step of. Wherein the layer having the conductive manufacturing method of a semiconductor device according to claim 1, wherein the polysilicon layer.