JP3160544B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having a high withstand voltage characteristic used as a switch for loads of various electric devices and the like.

[0002]

2. Description of the Related Art In recent years, MOSFETs having high withstand voltage characteristics have been used as switches for loads of electric devices. Such a MOSFET is configured such that when a high voltage is applied to the drain electrode due to a back electromotive force generated by an inductive load, the concentration of the electric field in the semiconductor substrate is reduced, thereby preventing the breakdown of the semiconductor device. Have been.

FIG. 5 shows one example of various techniques conventionally used to alleviate this electric field concentration. For example, a horizontal type having a high withstand voltage characteristic described in Japanese Patent Application Laid-Open No. Hei 6-77470. MOSFET (Horizontal DMOSFET)
FIG. 3 is a cross-sectional view showing the structure of FIG. As shown in FIG. 1, a P-type semiconductor substrate 12 for forming a channel is formed in an N- type semiconductor substrate 12.
A + type region 13, an N + type region 14 serving as a source, and an N + type region 15 serving as a drain are formed. Also,
On the semiconductor substrate 12, an oxide film 16 and a conductive plate 17 made of polycrystalline silicon are sequentially formed. One of the conductive plates 17 is the gate electrode 1
7a. Further, an interlayer insulating film 1 is formed on the substrate.
8 and a drain electrode 19 made of aluminum wiring. The conductive plate 17 other than the gate electrode 17a is in an electrically floating state.

The operation of the semiconductor device configured as described above will be described below. A high potential is applied to the N + -type region 15 and the semiconductor substrate 12 via the drain electrode 19, and a low potential of about several volts is normally applied to the gate electrode 17a. On the other hand, as described above, the potential of the conductive plate 17 except for the gate electrode 17a is in a floating state. The potential of the conductive plate 17 in a floating state depends on the capacitance between the semiconductor substrate and the conductive plate sandwiching the oxide film 16, the capacitance between the gate electrode and the conductive plate sandwiching the interlayer insulating film 18 in the horizontal direction, and It is determined by the capacitance between the drain electrode and the conductive plate sandwiching the film 17 in the lateral direction. The capacitance is optimized by appropriately adjusting the interval between the conductive plates 17, and each conductive plate 1
It is configured to be able to evenly distribute the potential difference between 7 from a high potential to a low potential. By optimizing the potential distribution in each conductive plate, the local electric field is not concentrated near the surface of the semiconductor substrate, thereby improving the breakdown voltage characteristics of the lateral DMOSFET.

[0005]

However, there is a problem that a sufficient effect of improving the withstand voltage characteristics cannot always be obtained with the structure of the above-mentioned conventional lateral DMOSFET. Then, as a result of pursuing the cause, the following knowledge was obtained.

FIG. 6 is an enlarged sectional view of a part of FIG. However, the figure is not isotropically enlarged, but is a figure in which a specific portion is enlarged only in a specific direction so that a problem can be easily understood. Since the conductive plate 17 is processed to a required size by dry etching or the like after being deposited on the entire surface of the oxide film 16, the cross-sectional shape of the conductive plate 17 becomes a trapezoid having a wide bottom surface. Then, the equipotential lines are distributed along the side surface shape of the conductive plate 17,
Due to such a shape of the conductive plate 17, the potential distribution becomes denser nearer to the surface of the semiconductor substrate 12, and becomes sparser as farther away. That is, the potential distribution near the surface of the semiconductor substrate 12 becomes dense immediately below the gap between the conductive plates 17 and becomes sparse just below the conductive plates 17. For this reason,
In practice, the distribution of the equipotential lines is unbalanced as shown in FIG. 6, and the electric field is locally concentrated. Since the dielectric breakdown of the oxide film 16 and the like easily occurs in the portion where the electric field is locally concentrated, an excessively high voltage cannot be applied to the drain region, and a high withstand voltage characteristic may not be exhibited. is there.

Further, the interlayer insulating film 18 is formed in a manufacturing process.
Since the film is deposited over both the oxide film 16 and the conductive plate 17, the state shown in FIG.
As shown in the figure, there is a step on the surface of the interlayer insulating film 18 due to the difference in height between the surface of the oxide film 16 and the surface of the conductive plate 17. Therefore, a drain electrode 19 made of aluminum or the like formed on the interlayer insulating film 18 is formed.
May cause disconnection due to the step. Therefore,
In a general manufacturing process, the interlayer insulating film 18 is etched back to flatten the surface of the interlayer insulating film 18, and then a subsequent process is performed. However, by performing such an etchback, the thickness and the shape of the interlayer insulating film 18 vary among products. As described above, the capacitance value determined by the thickness and the shape of the interlayer insulating film 18 varies between products. As a result, even if the dimensions of each part are designed so that the distance between the conductive plates 17 is optimized, the When the capacitance value of the insulating film 18 changes, the potential difference between the conductive plates 17 deviates from the optimum value. FIG. 7 also shows the non-uniform state of the conductive plates 17 and the potentials between the conductive plates caused by such variations in the thickness and shape of the interlayer insulating film 18.

That is, even if the thickness and the shape of the interlayer insulating film 18 vary, a location where the electric field is locally concentrated near the surface of the semiconductor substrate 12 is generated. And the breakdown voltage characteristics are not stable.

The present invention has been made in view of the above points, and an object of the present invention is to improve a breakdown voltage characteristic of a semiconductor device by taking measures for avoiding local electric field concentration near the surface of a semiconductor substrate. And stabilization.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
A semi-conductor substrate, an active region configured to operate in accordance with a voltage applied from the outside is formed on the main surface of the semiconductor substrate, it is formed on the outside or inside of the active region in the above semiconductor substrate A protection region for alleviating an electric field of the active region, an insulating film formed at least on the protection region, and formed at a predetermined interval on an upper surface of the insulating film so as to face the protection region. a plurality of recesses, are embedded in the in each recess, e Bei and a plurality of electrical conductors potential is configured so as to be distributed from the high potential to the low potential when a voltage is applied from the outside, the side surface of the recess Are inclined with respect to a direction perpendicular to the upper surface of the insulating film, and the conductor has an inverted trapezoidal cross section. As described in claim 1, a semiconductor substrate, an active region formed on a main surface side of the semiconductor substrate and configured to operate in response to a voltage applied from the outside, and an active region in the semiconductor substrate. A protection region formed outside or inside the active region to reduce the electric field of the active region, an insulating film formed at least on the protection region, and an insulating film facing the protection region. A plurality of recesses formed at predetermined intervals on an upper surface; and a plurality of conductive members embedded in each of the recesses and configured so that a potential when an external voltage is applied is distributed from a high potential to a low potential. And body.

Thus, even when a high voltage is applied from the outside, the potential distribution of each conductor is sequentially distributed from a high potential to a low potential, so that the action of alleviating the electric field in the protection region is reliably obtained. Moreover, since the conductor is embedded in the concave portion of the insulating film, a large step does not occur between the upper surface of the conductor and the upper surface of the insulating film as in the case where the conductor is formed on the insulating film. Therefore, even when a dielectric film such as an interlayer insulating film is formed on the insulating film or the conductor, it is not necessary to flatten the dielectric film, so that the thickness and the shape of the dielectric film are substantially uniform. That is, variation in the potential distribution of each conductor between products is suppressed. That is, it is possible to reliably exhibit the withstand voltage characteristic according to the design value.

A semiconductor device according to the present invention comprises: a semiconductor substrate; an active region formed on a main surface side of the semiconductor substrate and configured to operate in response to an externally applied voltage; A protection region formed outside or inside the active region for relaxing the electric field of the active region; an insulating film formed at least on the protection region; and an upper surface of the insulating film facing the protection region. And a plurality of conductors embedded in each of the recesses and configured such that the potential when an external voltage is applied is distributed from a high potential to a low potential. e Bei the door, the conductors, the area of the upper surface is wider than the area of the bottom surface.

[0013] More to this, the potential lines generated in the insulating film along the side surface of the conductive body is a shape that extends downward, the local concentration of the electric field near the surface of the semiconductor substrate is reduced. Therefore, the voltage that can be applied to both poles of the active region can be further increased. That is, the breakdown voltage characteristics of the semiconductor device are improved.

[0014] It is preferable that in a common plane with the upper surface of the upper surface and the insulating film of the upper Kishirube collector.

[0015] The upper SL active region, and disposed at both ends of the source and drain regions containing a high concentration first conductivity type impurity,
And a channel region containing a second conductivity type impurity is provided adjacent to the source region, and the protection region is formed by introducing a low concentration first conductivity type impurity between the drain region and the channel region. In this case, an insulating gate can be provided at least on the channel region.

As a result, a high-breakdown-voltage field effect transistor having the above function can be obtained.

The semi-conductor device of the present invention includes a semiconductor substrate, an active region configured to operate in accordance with a voltage applied from the outside is formed on the main surface of the semiconductor substrate, the active region A first impurity diffusion region formed by introducing a first conductivity type impurity into a region, and a channel formed by introducing a second conductivity type impurity into a region adjacent to the first impurity diffusion region in the active region. A second impurity diffusion region functioning as a region, a reverse conductivity type layer formed in a region surrounded by the first impurity diffusion region and containing a low-concentration second conductivity type impurity, and The formed insulating film, a plurality of concave portions formed at predetermined intervals on the upper surface of the insulating film facing the opposite conductivity type layer, and embedded in each of the concave portions, and a voltage was externally applied. When the potential is high to low In a plurality of electrical conductors configured to distributed, in a state in which voltage is externally applied, PN between the first impurity diffusion region and the opposite conductivity type impurity diffusion layer
The depletion layer is configured to extend from the junction , the side surface of the concave portion is inclined with respect to a direction perpendicular to the upper surface of the insulating film, and the conductor has an inverted trapezoidal cross section.

[0018] Thereby, the first portion existing below the conductor is formed.
The electric field in the active region is alleviated by the impurity diffusion region, but since the potential distribution of each conductor is sequentially distributed from a high potential to a low potential, the electric field in the first impurity diffusion region similar to claim 1 is reduced. The mitigation action is reliably obtained. In addition, while a voltage is applied to the active region, the depletion layer spreads from the PN junction between the first impurity diffusion region and the opposite conductivity type impurity diffusion layer, and a potential difference is generated in the depletion layer. Therefore,
By appropriately adjusting the potential of each conductor, the concentration of the electric field near the surface of the semiconductor substrate is reduced.

Further, the equipotential lines generated in the insulating film by the conductor embedded in the concave portion can be appropriately adjusted.
It is possible to obtain an optimum withstand voltage characteristic.

The semi-conductor device of the present invention includes a semiconductor substrate, an active region configured to operate in accordance with a voltage applied from the outside is formed on the main surface of the semiconductor substrate, the active region A first impurity diffusion region formed by introducing a first conductivity type impurity into a region, and a channel formed by introducing a second conductivity type impurity into a region adjacent to the first impurity diffusion region in the active region. A second impurity diffusion region functioning as a region, a reverse conductivity type layer formed in a region surrounded by the first impurity diffusion region and containing a low-concentration second conductivity type impurity, and The formed insulating film, a plurality of concave portions formed at predetermined intervals on the upper surface of the insulating film facing the opposite conductivity type layer, and embedded in each of the concave portions, and a voltage was externally applied. When the potential is high to low In a plurality of electrical conductors configured to distributed, in a state in which voltage is externally applied, PN between the first impurity diffusion region and the opposite conductivity type impurity diffusion layer
Is configured to a depletion layer extends from the junction, the upper Kishirubedentai, the area of the upper surface is wider than the area of the bottom surface.

[0021] More to this, the potential lines generated in the insulating film along the side surface of the conductive body is a shape that extends downward, the local concentration of the electric field near the surface of the semiconductor substrate is reduced. Therefore, the voltage that can be applied to both poles of the active region can be further increased. That is, the breakdown voltage characteristics of the semiconductor device are improved.

[0022] It is preferable that in a common plane with the upper surface of the upper surface and the insulating film of the upper Kishirube collector.

[0023] The upper SL active region, and disposed at both ends of the source and drain regions containing a high concentration first conductivity type impurity,
And a second region adjacent to the source region and serving as the channel region.
The first impurity diffusion region may be provided adjacent to the drain region, and the insulating gate may be provided at least above the channel region.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a sectional view of a high breakdown voltage semiconductor device according to this embodiment. As shown in FIG. 1, an active region which operates as a MOSFET is provided in a P- type semiconductor substrate 1, and in the active region, a bipolar portion receiving a voltage, that is, a source region and a drain region ( Alternatively, two N + regions 5 functioning as drain contact regions are formed. An N- type region 2 serving as a protection region for relaxing an electric field generated in the semiconductor substrate due to a voltage between the two N + regions 5 is provided between the two N + regions 5.
And a P- type region 4 functioning as a channel region. On the semiconductor substrate 1 between the two N + regions 5, an oxide film 6 formed by thermal oxidation is formed.
Is provided. A gate electrode 8 made of polycrystalline silicon containing impurities is formed in a region extending from the end on the source side on oxide film 6 to the side surface of oxide film 6 and semiconductor substrate 1. Further, a first interlayer insulating film 9a is deposited on the substrate, and the first interlayer insulating film 9a
A drain electrode 10 and a source electrode 11 are formed on the substrate, and the drain electrode 10 and the source electrode 11
It is connected to each of the N + regions 5 which are a drain region and a source region via contact holes formed in the interlayer insulating film 9a. The drain electrode 10 is connected to one conductive plate 7 adjacent to the source via a contact hole formed in the first interlayer insulating film 9a. Note that a second interlayer insulating film 9b is deposited on the first interlayer insulating film 9a.

The first feature of the present embodiment is that a plurality of conductive plates 7 made of polycrystalline silicon containing impurities are buried in the vicinity of the surface of oxide film 6 at regular intervals. The upper surface of the oxide film 6 and the upper surface of the oxide film 6 are flattened, and the side surface of the conductive plate 7 is inclined so as to narrow downward. In other words, the conductive plate 7 has an inverted trapezoidal shape in which the top of the trapezoid is located below and the bottom is located above in the section parallel to the channel direction (section shown in FIG. 1). In other words,
The gap region between the respective conductive plates 7 formed of the oxide film 6 is enlarged downward.

The second feature of the present embodiment is that a low-concentration P-type impurity (for example, boron) is added to a region of the N − region 2 near the surface of the semiconductor substrate 1 located below the oxide film 6.
Is formed, and the opposite conductivity type layer 3 is grounded.

In the present embodiment, the following advantageous effects can be obtained by the above structural features as compared with the above-mentioned conventional DMOSFET.

First, since the conductive plate 7 is formed in an inverted trapezoid, a high potential is applied to the drain electrode 10.
When a low potential is applied to the source electrode 11, the conductive plate 7 embedded in the oxide film 6 is brought into a floating state, whereby the potential distribution can be stabilized as in the conventional DMOSFET, and The potential distribution in oxide film 6 below 7 can be made more uniform.

FIG. 2 is a cross-sectional view showing a part of FIG. 1 in an enlarged manner in order to explain the action of making the potential distribution uniform by the conductive plate 7. As shown in FIG. As described above, since the equipotential lines are distributed along the side surface shape of the conductive plate 7, the equipotential lines are distributed so as to spread downward in the oxide film 6.
Therefore, the equipotential lines near the surface of the semiconductor substrate 1 are:
The distribution is substantially uniform from immediately below the gap between the respective conductive plates 7 to immediately below the conductive plate 7, and the above-described conventional DM
As in the case of the structure of the OSFET (see FIG. 6), in the region near the surface of the semiconductor substrate 1, the voltage is not locally concentrated only in the region below the gap region of the conductive plate 7 and in a part thereof. Therefore, the potential distribution near the surface of the semiconductor substrate 1 can be made uniform,
Therefore, the breakdown voltage characteristics of the DMOSFET can be improved.

However, each conductive plate 7 does not necessarily need to have an inverted trapezoidal shape. If the conductive plate 7 is configured so that the cross-sectional area increases downward, equipotential lines distributed along the side surfaces are formed on the surface of the semiconductor substrate. Since it spreads toward the surface, the concentration of the electric field near the surface of the semiconductor substrate 1 can be reduced to some extent as compared with the conventional structure.

The following effects can be obtained by making the surface of the conductive plate 7 and the surface of the oxide film 6 flat at the same height. That is, the above-mentioned conventional DMOSFE
According to the structure of T, in the manufacturing process, polycrystalline silicon as a conductive plate is deposited on an insulating film formed of a thermal oxide film, and then interlayer insulation is provided for insulation with an aluminum electrode as another wiring. It must be performed in the procedure of forming a film. At this time, the step of the surface of the interlayer insulating film between the place where polycrystalline silicon is deposited and the place where polycrystalline silicon is not deposited (see FIG. 6) does not occur in the structure of the present embodiment. That is, in the structure of this embodiment, since the upper surfaces of the oxide film 6 and the conductive plate 7 are flattened, the thickness of the first interlayer insulating film 9a on the oxide film 6 is uniform. This eliminates the need for the etchback for flattening performed by the above-mentioned conventional DMOSFET in order to eliminate the step, so that the thickness of the first interlayer insulating film 9a on the conductive plate 7 does not decrease. The capacitance value of the first interlayer insulating film 9a in the direction does not decrease. As a result, as compared with the case where the interlayer insulating film 9a is etched back, the potential difference that can be insulated between the polycrystalline silicon is increased, and the withstand voltage characteristics are improved. further,
Since the etching step is unnecessary, variations in the thickness and shape of the interlayer insulating film 9a are eliminated, and variations in characteristics are also eliminated.

However, the upper surfaces of the conductive plate 7 and the oxide film 6 need not be completely flattened. Even if only the conductive plate 7 is embedded in the concave portion of the oxide film 6,
Since the step between the conductive plate 7 and the oxide film 6 is reduced, the necessity of flattening the first interlayer insulating film 9a is also reduced. Therefore, also in this case, the above effects can be exerted to some extent.

Further, in the present embodiment, the conductive plate 7
P- type reverse conductivity type layer 3 in N- type region 2 underneath.
, The following effects can be exerted. The P- type reverse conductivity type layer 3 and the semiconductor substrate 1
Is set to the ground potential, the N− type region 2
When a high voltage is applied through the N + -type region 5 on the drain side, the PN formed between the two regions 2 and 3 and between the two
The depletion layer spreads from the junction surface of the junction. In particular, the P- type reverse conductivity type layer 3 is almost completely depleted. And area 1,
A large depletion layer is formed between the region 2 and the semiconductor substrate 1 by combining the depletion layer between the region 2 and the depletion layer between the regions 2 and 3. In this depletion layer, a potential difference corresponding to the difference between the high voltage applied to region 2 via region 5 and the ground potential applied to semiconductor substrate 1 is generated. That is, compared with the case where the opposite conductivity type layer 3 is not present, the spread of the depletion layer near the surface of the semiconductor substrate 1 is increased, so that the electric field concentration near the surface is reduced. As a result, the withstand voltage characteristics are improved. Further, the presence of the conductive plate 7 thereabove reduces the electric field concentration near the surface of the semiconductor substrate 1, so that the electric field concentration alleviation effect due to the expansion of the depletion layer and the electric field concentration alleviation effect due to the conductive plate are reduced. Accordingly, a remarkable effect of improving the withstand voltage characteristics can be obtained, and thus the reliability can be improved.

FIG. 3 shows a DMOSFET according to the present embodiment.
3 shows the state of the potential distribution with respect to the distance of the conductive plate 7 of FIG. The conductive plate 7 has an inverted trapezoidal shape, and the conductive plate 7
P− type reverse conductivity type layer 3 in N− region 2 located below
Is formed, a uniform potential distribution between the conductive plates 7 can be obtained.

In the present embodiment, the conductive plate 7 is made of polycrystalline silicon to which impurities are added, but the present invention is not limited to such an embodiment. The conductive plate 7 may be made of a conductor other than polycrystalline silicon, for example, a metal such as aluminum. Also,
In the present embodiment, the oxide film 6 is composed of a thermal oxide film, but it goes without saying that the oxide film 6 may be composed of an oxide film formed by a CVD method.

Next, the manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS.

First, in the step shown in FIG. 4A, phosphorus ions are implanted and thermally diffused into the P-type semiconductor substrate 1 using a resist mask (not shown) in which a drain formation region is opened. An N @-type region 2 functioning as a drain region is formed at a predetermined interval from each other. Further, boron ions are implanted into the N − region 2 and heat diffusion is performed into the N − region 2 using a resist mask (not shown) having an opening in the region for forming the opposite conductivity type layer, thereby forming the P − type opposite conductivity type layer 3. Form. However,
Thermal diffusion for activating the impurities, including the subsequent steps, may be performed simultaneously for each region.

Thereafter, in the step shown in FIG.
In the semiconductor substrate 1 located between the mold regions 2, boron ions are implanted to form a P @-region 3 serving as a channel region. Further, thermal oxidation is performed to grow oxide film 6 on P − type region 3 to a thickness of about 1000 nm.

Then, in a step shown in FIG. 4C, a resist mask is formed and wet etching is performed to form an oxide film 6.
Then, a tapered concave portion having a depth of about 500 nm and narrowing downward is formed. Thereafter, an impurity-added polycrystalline silicon film is deposited on the substrate, a resist film is formed and the polycrystalline silicon film is etched to form a conductive plate 7 in which recesses are filled with polycrystalline silicon, and an oxide film. A gate electrode 8 is formed so as to extend from the edge of the upper surface of 6 to the side surface and the semiconductor substrate 1. By this step, the surface heights of the oxide film 6 and the conductive plate 7 are the same. Also,
The embedded conductive plate 7 has an inverted trapezoid whose surface area is larger than the bottom area. That is, as compared with the conductive plate 17 (see FIG. 6) in the conventional DMOSFET, the angle between the bottom surface and the side surface of the conductive plate 7 formed in the manufacturing process of this embodiment is obtuse in the cross section shown in FIG. It is a major feature that the step portion is eliminated.

Then, in the step shown in FIG. 4D, the N @-region 2 and the P @-region 2 are formed using a resist mask (not shown) having openings in the drain contact formation region and the source formation region.
Arsenic ions are implanted into region 4 to form each N + type region 5; Next, a glass layer doped with phosphorus is formed to a thickness of about 1.5 μm on the substrate to form a first interlayer insulating film 9a, on which each N + region 5 and a specific A connection hole reaching the conductive plate 7 is formed. Then, after forming an aluminum film filling the contact hole and extending on the first interlayer insulating film 9a, the aluminum film is patterned to form a drain electrode 10 and a source electrode 11. After that, a second interlayer insulating film 9b is formed on the substrate.

Through the above manufacturing steps, the semiconductor device shown in FIG. 1 can be easily formed.

In the above embodiment, the semiconductor device is a D
Although the case of a MOSFET has been described, the present invention is not limited to such an embodiment, and any semiconductor device having an active region to which a high voltage is applied may be a DMOS.
The present invention is also applicable to semiconductor devices other than FETs.

[0044]

According to the semiconductor device of the present invention , an insulating film is provided on a protection region for relaxing an electric field in an active region in a semiconductor substrate, and a plurality of recesses formed on the upper surface of the insulating film have conductors. Is provided so that the potential of this conductor is distributed from a high potential to a low potential when a high voltage is applied from the outside, so that the step difference between the insulating film and the conductor reduces the variation in characteristics between products. , The withstand voltage characteristics of the semiconductor device can be improved.

According to the semiconductor device of the present invention, a PN junction configured so that a depletion layer expands in a state where a voltage is applied to the active region is provided in a region for relaxing an electric field in the active region in the semiconductor substrate. Therefore, the concentration of the electric field on the surface of the semiconductor substrate can be reduced, and the withstand voltage characteristics of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a DMOSFET according to a first embodiment.

FIG. 2 is an enlarged sectional view showing a part of FIG. 1;

FIG. 3 is a diagram for explaining uniformity of potential distribution in each conductive plate of the semiconductor device of the present invention.

FIG. 4 is a cross-sectional view showing a process for manufacturing the DMOSFET according to the first embodiment.

FIG. 5 is a sectional view of a conventional DMOSFET.

FIG. 6 is an enlarged sectional view showing a part of FIG. 6;

FIG. 7 is a diagram for explaining variation in potential distribution in a conductive plate of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 N- type region (protective region, first impurity diffusion region) 3 reverse conductivity type layer 4 P- type region (second impurity diffusion region) 5 N + type region (source region, drain region) 6 Oxide film (insulating film) 7 Conductive plate (conductor) 8 Insulating gate 9a First interlayer insulating film 9b Second interlayer insulating film 10 Drain electrode 11 Source electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/336 H01L 29/78 H01L 29/41

Claims (8)

(57) [Claims] A semiconductor substrate; an active region formed on a main surface side of the semiconductor substrate and configured to operate in response to a voltage applied from the outside; and an outside or an outside of the active region in the semiconductor substrate. A protection region formed therein for alleviating an electric field of the active region; an insulating film formed at least on the protection region; and a predetermined interval on an upper surface of the insulating film facing the protection region. a plurality of recesses formed have, embedded in the in each recess, e Bei and a plurality of electrical conductors potential is configured so as to be distributed from the high potential to the low potential when a voltage is applied from the outside, A semiconductor device, wherein a side surface of the concave portion is inclined with respect to a direction perpendicular to an upper surface of the insulating film, and a cross-sectional shape of the conductor is an inverted trapezoid. 2. A semiconductor substrate, an active region formed on a main surface side of the semiconductor substrate and configured to operate in response to a voltage applied from outside, and an outside or outside of the active region in the semiconductor substrate. A protection region formed therein for alleviating an electric field of the active region; an insulating film formed at least on the protection region; and a predetermined interval on an upper surface of the insulating film facing the protection region. a plurality of recesses formed have, embedded in the in each recess, e Bei and a plurality of electrical conductors potential is configured so as to be distributed from the high potential to the low potential when a voltage is applied from the outside, A semiconductor device, wherein the conductor has an upper surface area larger than a bottom surface area. 3. The semiconductor device according to claim 1 , wherein an upper surface of the conductor and an upper surface of the insulating film are in a common plane. 4. The semiconductor device according to claim 1, 2 or 3, wherein said active region, a source region and a drain region comprising a high concentration first conductivity type impurity and disposed at both ends, and adjacent to the source region The protection region is formed by introducing a low-concentration first conductivity type impurity between the drain region and the channel region. A semiconductor device, wherein an insulating gate is provided at least on the channel region. 5. A semiconductor substrate, an active region formed on a main surface side of the semiconductor substrate and configured to operate in response to a voltage applied from the outside, and a first conductivity type in a region in the active region. A first impurity diffusion region formed by introducing an impurity, and a second impurity region formed by introducing a second conductivity type impurity into a region adjacent to the first impurity diffusion region in the active region and functioning as a channel region. An impurity diffusion region, a reverse conductivity type layer formed in a region surrounded by the first impurity diffusion region and containing a low-concentration second conductivity type impurity, and an insulating film formed on the reverse conductivity type layer. A plurality of recesses formed at predetermined intervals on the upper surface of the insulating film so as to face the opposite conductivity type layer, and embedded in each of the recesses, and the potential when an external voltage is applied is high. From low to low potential And a plurality of conductor constituted, in a state in which voltage is externally applied, is configured as a depletion layer extends from the PN junction between the first impurity diffusion region and the opposite conductivity type impurity diffusion layer And a side surface of the concave portion is inclined with respect to a direction perpendicular to an upper surface of the insulating film, and a cross-sectional shape of the conductor is an inverted trapezoid. 6. A semiconductor substrate, an active region formed on a main surface side of the semiconductor substrate and configured to operate in response to an externally applied voltage, and a first conductivity type formed in a region in the active region. A first impurity diffusion region formed by introducing an impurity, and a second impurity region formed by introducing a second conductivity type impurity into a region adjacent to the first impurity diffusion region in the active region and functioning as a channel region. An impurity diffusion region, a reverse conductivity type layer formed in a region surrounded by the first impurity diffusion region and containing a low-concentration second conductivity type impurity, and an insulating film formed on the reverse conductivity type layer. A plurality of recesses formed at predetermined intervals on the upper surface of the insulating film so as to face the opposite conductivity type layer, and embedded in each of the recesses, and the potential when an external voltage is applied is high. From low to low potential And a plurality of conductor constituted, in a state in which voltage is externally applied, is configured as a depletion layer extends from the PN junction between the first impurity diffusion region and the opposite conductivity type impurity diffusion layer cage, the conductors, the semiconductor device area of the upper surface is equal to or larger than the area of the bottom surface. 7. The semiconductor device according to claim 5 , wherein an upper surface of the conductor and an upper surface of the insulating film are in a common plane. 8. The semiconductor device according to claim 5 , wherein the active region has a source region and a drain region containing a high-concentration first-conductivity-type impurity at both ends, and is adjacent to the source region. And a second impurity diffusion region serving as the channel region is provided. The first impurity diffusion region is provided adjacent to the drain region, and at least an insulating layer is provided on the channel region. A semiconductor device provided with a gate.