JPH06232149A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide the semiconductor device capable of making the enhancement of breakdown voltage and integration compatible. CONSTITUTION:Within a dielectric separation type bipolar transistor wherein the sides of a buried collector region 3 and the sides of collector breakdown region 4 are insulation-separated from adjacent semiconductor regions (polysilicon trench buried region 8 or N-region 11 in a trench T2) by the first side separating insulator region (silicon oxide film) 9a held between the regions 3 and 4, the second side separating insulator region (silicon oxide film) 9b reaching the surface part of the buried collector region 3 is formed between a base region 5 and a surface collector region 7. Resultantly, even if the horizontal distance between the base region 5 and the surface collector region 7 is shortened, the electrical insulation between the base region 5 and the surface collector region 7 can be secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar transistor (BPT) whose dielectric is separated at least on its side surface.

[0002]

2. Description of the Related Art In a vehicle-mounted semiconductor device such as a microcomputer for controlling a vehicle engine used in a high noise environment, it is important to improve the withstand voltage even if it suffers from the disadvantages of a slight decrease in the degree of integration and an increase in the manufacturing process. Dielectric isolation structure or full-distance (side and bottom) dielectric isolation structure (JP-A-48-10008)
The transistor integrated circuit of Japanese Patent No. 1) is suitable.

[0003]

In such a bipolar integrated circuit, in order to reduce the transistor size and improve the degree of integration, the horizontal distance from the base region to the side surface isolation insulating film (that is, in the base region). It is necessary to reduce the width W of the outer collector breakdown voltage region. However,
When the horizontal distance W is reduced, the integration degree is improved but the collector breakdown voltage BVceo is lowered.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a bipolar semiconductor device capable of improving both breakdown voltage and integration degree.

[0005]

The semiconductor device of the present invention comprises:
A high-concentration first-conductivity-type buried collector region that is insulated from the semiconductor substrate, and a low-concentration first-conductivity-type collector breakdown voltage region formed on the buried collector region;
A first side surface isolation insulator region that insulates and separates side faces of the island-shaped regions, a second conductivity type base region formed on a surface portion of the island-shaped collector breakdown voltage region, and the island-shaped collector breakdown voltage. A high-concentration first-conductivity-type surface collector region formed on the surface of the region away from the base region; a high-concentration first-conductivity-type emitter region formed on the surface of the base region; In a semiconductor device including an adjacent semiconductor region adjacent to the island-shaped semiconductor breakdown voltage region with a side surface isolation insulator region interposed therebetween, the base region and the surface collector region are insulated and separated from each other, and a surface portion of the buried collector region is provided. It is characterized in that it has a reaching second side surface isolation insulator region.

Here, the second side surface isolation insulator region does not have to come into contact with the surface portion of the buried collector region, but only needs to reach the vicinity thereof. For example, the effective depth of the collector withstand voltage region from the bottom of the base region to the surface of the buried collector region is 8
It is sufficient that the second side surface isolation insulator region is formed in an amount of 0% or more. In a preferred embodiment, the first side surface isolation insulator region is in contact with a side surface of the base region.

In a preferred aspect, a potential closer to the potential of the emitter region than the potential of the surface collector region is applied to the adjacent semiconductor region. In a preferred embodiment,
The adjacent semiconductor region is composed of a polysilicon trench filling region that surrounds the base region with the first and second side surface isolation insulator regions interposed therebetween. In a preferred aspect, the same potential as the potential of the emitter region is applied to the adjacent semiconductor region.

[0008]

In the dielectric isolation type bipolar transistor in which the side surfaces of the buried collector region and the collector breakdown voltage region are insulated and separated from the adjacent semiconductor region by the first side face isolation insulator region, the base region and the surface collector region are provided. A second side surface isolation insulator region reaching the surface of the buried collector region is formed between the first and second sides.

As a result, even if the horizontal distance between the base region and the surface collector region is shortened, the electrical insulation between the base region and the surface collector region is ensured by the second side surface isolation insulator region. Since the second side surface isolation insulator region does not divide the buried collector region like the first side surface isolation insulator region, the conduction between the buried collector region immediately below the base region and the surface collector region is secured. It

That is, in the semiconductor device of the present invention, the shallow second side surface isolation insulator region insulates and separates the base region and the surface collector region without dividing the buried collector region. The distance from the surface collector region can be shortened, and the transistor size can be reduced without lowering the breakdown voltage. In particular, when adjacent semiconductor regions (for example, polysilicon trench filling regions) are adjacent to the base region with both-side isolation insulator regions sandwiched therebetween, and a low potential such as an emitter potential is applied to the adjacent semiconductor regions, both-side isolation insulation is performed. Since the bending of the collector depletion layer formed in the portion of the collector withstand voltage region close to the object region is suppressed, the electric field concentration is relieved, and the breakdown in this part is suppressed, so that the base region is the first, Even if the size of the transistor is reduced by making direct contact with the second side surface isolation insulator region, it is possible to obtain the excellent effect of suppressing the breakdown voltage reduction.

[0011]

EXAMPLE 1 A high breakdown voltage NPN bipolar transistor having a full dielectric isolation structure will be described below as an example of a semiconductor device of the present invention. 1 is a P ⁻ silicon substrate (semiconductor substrate), 2 is a silicon oxide film for bottom insulation, 3 is N ⁺
Buried collector region, 4 is N ^- collector breakdown voltage region, 5
Is a P ⁺ base region, 6 is an N ⁺ emitter region, 7 is an N ⁺ surface collector region, 8 is a polysilicon trench filling region for trench filling (adjacent semiconductor region), 9a is an island-like buried collector region 3 and immediately above it. , A silicon oxide film (first side surface isolation insulator area) surrounding the side surface of the collector breakdown voltage area 4,
Reference numeral b is a silicon oxide film (second side surface isolation insulator region) that surrounds the side surface of the base region 5 and separates the base region 5 and the surface collector region 7.

Numeral 10 is a silicon oxide film on the surface, E, B, and C are emitter contact electrodes, base contact electrodes, and collector contact electrodes made of aluminum, respectively, and 12 is a bipolar film sandwiching the silicon oxide film 9a. Reference numeral 13 denotes an N ⁺ contact region formed on the surface of the N ⁻ region 11 surrounding the side surface of the transistor, and 13 denotes the contact electrode.

In this embodiment, both ends of the polysilicon groove filling region 9b are connected to the polysilicon groove filling region 9a and are grounded together with the contact electrode 13. A ground potential or a potential close to the ground potential is applied to the emitter electrode E. The manufacturing process of this transistor will be described below. First, as shown in FIG. 2, a mirror-polished N ⁻ -type (100) single crystal silicon substrate 40 having a specific resistance of 3 to 5 Ω · cm was prepared, and antimony was diffused to a surface of 3 μm by a vapor phase diffusion method. To form the N ⁺ diffusion layer 30.
Separately, one principal surface of the P ⁻ substrate 1 is mirror-polished and then thermally oxidized to form a silicon oxide film 2 having a thickness of about 1.0 μm. These silicon substrate 1 and silicon substrate 40
Was heated at H ₂ 0 ₂ -H ₂ SO ₄ mixed solution, subjected to a hydrophilic treatment, bonding at room temperature clean atmosphere, Celsius 1100
Heat treatment was performed for 2 hours in a N ₂ atmosphere to bond them. Subsequently, the substrate 40 was mirror-polished to a predetermined thickness to a thickness of 14 μm to manufacture an SOI substrate.

Next, as shown in FIG. 3, a field oxide film of about 0.5 μm is formed on the surface of this SOI substrate by thermal oxidation, and a silicon nitride film of 0.1 μm is formed thereon by LPCVD. Next, a resist mask is formed on the silicon nitride film, and plasma etching with a fluorine-based etching gas, hydrofluoric acid etching, and reactive ion etching with a fluorine-based etching gas are performed to remove the vapor.
A silicon oxide film 2 around the area where the transistor is to be formed
To form a silicon oxide film 9a by oxidizing the surface of the trench T1. Subsequently, the polysilicon is deposited by the LPCVD method to fill the trench region T1. Next, the polysilicon on the surface of the silicon nitride film is removed, the surface of the polysilicon exposed from the trench T1 is oxidized, and then the silicon nitride film is removed by dry etching. As a result, a polysilicon groove filling region 8 surrounded by the silicon oxide film 9a is formed inside the trench T1. This polysilicon trench filling region is doped with N ⁺ . Then, the silicon oxide film 9a separates and forms the island-shaped N ⁺ buried collector region 3 and the N ⁻ collector breakdown voltage region 4 from the N ⁺ diffusion layer 30 and the N ⁻ region 40.

Next, as shown in FIG. 4, the trench T is formed.
1, the trench T2, the silicon oxide film 9b, and the polysilicon trench filling region 8 in the trench T2 are formed by the same process as the process of forming the polysilicon trench filling region 8 in the silicon oxide film 9a and the trench T1. Incidentally, the trench T
2 is formed between the planned base region and the surface collector region until the surface of the buried collector region 3 is reached. Both polysilicon trench-filled regions 8 of the trenches T1 and T2 are in contact and electrically. It is conducted.

Next, as shown in FIG. 1, P ⁺ base region 5, N ⁺ emitter region 6, N ⁺ surface collector region 7, N
^{+ The} contact region 12 is formed by a photolithography process, an ion implantation process, and a drive-in process, and then the oxide film 1 is formed.
0 is opened to form each electrode E, B, C, 13. Although not shown, a predetermined area of the polysilicon groove filling region 8
A contact electrode that contacts the location is also formed in the same manner.

All side surfaces of the base region 5 are formed in contact with the silicon oxide films 9a and 9b, and all side surfaces of the surface collector region 7 are formed in contact with the silicon oxide films 9a and 9b. As a result, all side surfaces of the N ⁻ collector breakdown voltage region 4 directly below the base region 5 are also formed in contact with the silicon oxide films 9a and 9b. If you do this,
Since the side surface of the silicon region 5 is formed directly in contact with the side surfaces of the silicon oxide films 9a and 9b without the N ⁻ collector breakdown voltage region 4 interposed therebetween, the planar dimension of the transistor can be reduced accordingly and the integration degree can be reduced. Can be improved. By the way,
When the planar dimensions of the region 5 are made equal, the area can be reduced to 1/8 as compared with the conventional junction separation type bipolar transistor.

Further, the breakdown voltage can be improved by grounding the polysilicon groove filling region 8. In addition, the polysilicon trench filling region 8 is made to have a floating potential or depleted,
The N ⁺ region 12 may be grounded as an adjacent semiconductor region in the present invention. An example of parameters of each part will be described. N ^-
The impurity concentration of the collector breakdown voltage region 4 is 1 × 10 ¹⁵ atoms / c.
The impurity concentration on the surface of the m ³ P ⁺ base region is 3 ×
10 ¹⁸ atoms / cm ³ , the impurity concentration on the surface of the N ⁺ emitter region 6 is 1 × 10 ²⁰ atoms / cm ³ , the base region 5
Collector withstand voltage region 4 between the gate and the buried collector region 3
Has a thickness of 4 μm, the impurity concentration of the polysilicon groove filling region 8 is 1 × 10 ²⁰ atoms / cm ³ , its lateral width is 1 μm, the thickness of the silicon oxide films 9a and 9b is 0.7 μm, and the base region 5 has The thickness was 3 μm. Next, the description will be given of how the breakdown voltage is improved by grounding the polysilicon trench filling region 8 with reference to the transistor model of FIG. 5 and FIGS. 6 to 8 showing the relationship between the planar shape of the base region 5 and the breakdown voltage. explain.
The transistor of FIG. 5 is formed by omitting the trench T2 from the transistor of FIG. 1 and separating the base region 5 from the silicon oxide film 9a.

However, the emitter region 6 and the N ⁺ contact region 13 (equal potential to the N ⁻ region 11) are grounded, and +50 V is applied to the N ⁺ buried collector region 3. It is assumed that the polysilicon groove filling region 8 is an N ⁻ region and is substantially an insulator together with the silicon oxide film 9a. 6 to 8 are vertical cross sections of the collector depletion layer when the horizontal width W of the N ⁺ collector breakdown voltage region 4 between the side edge of the base region 5 and the silicon oxide film 9a is 15 μm, 10 μm, 5 μm. The shape is shown. The horizontal width W is the value of the resist mask opening pattern. The edge of the opening pattern of the mask is displaced by 2.5 μm with respect to the edge on the surface of the base region 5.

From FIGS. 6-7, the grounded N ^- region 11 is shown.
The equipotential lines of the depletion layer formed in the N ⁺ collector breakdown voltage region 4 between the side edge of the base region 5 and the silicon oxide film 9a are bent less as the horizontal width is reduced. It can be seen that the shape is approximately flat in the horizontal direction. When this bending is small, the breakdown voltage of the transistor is improved due to the electric field concentration.

FIG. 9 shows a simulation result of how the maximum electric field strength in the collector breakdown voltage region 4 changes when the horizontal distance W is actually changed. From FIG. 9, the distance W
It can be seen that the maximum electric field strength decreases with decreasing. That is, since the silicon region 11 has a low potential, the low potential of the silicon region 11 is changed to the silicon oxide film 9a.
(Including the polysilicon trench filling region 8. In this case, it is assumed that the polysilicon trench filling region 8 at the floating potential has a low impurity concentration and is depleted, or the polysilicon trench filling region 8 is replaced with a silicon oxide film. The discussion will be made on the assumption that the collector withstand voltage region 4 in the vicinity of the side surface of the base region 5 is electrostatically influenced (by electrostatically lowering the potential) via The depletion layer electric field in collector withstand voltage region 4 near the side surface of region 5 is relaxed. As a result, the electric field concentration is the strongest, and the depletion layer electric field near the corner of the base region 5 where the avalanche collapse first occurs is relaxed, and the breakdown voltage is improved.

FIG. 10 shows a simulation result of the collector-emitter breakdown voltage BVCEO at base open when the distance W between the base region 5 and the silicon oxide film 9a is changed and the other conditions are the same as above. At this time, the width of the depletion layer is 9 μm. It is understood that when the depletion layer reaches the side surface isolation insulator region 9, BVCEO is improved.

FIG. 11 shows the simulation result of BVCEO when the impurity concentration and W of the N ⁻ collector breakdown voltage region 4 are variously changed in the model of FIG. It can be seen that a breakdown voltage of 120 to 130 V can be realized under the best conditions. The above data are N ^- region 11
Was grounded, and the polysilicon trench filling region 8 was depleted, but almost the same data was obtained under the condition that the polysilicon trench filling region 8 had a high impurity concentration and was grounded. .

Next, collector voltage +50 is applied to the N ⁻ region 11.
FIG. 12 shows the state of the depletion layer when V is applied, the polysilicon trench filling region 8 is N ⁺ (about 1 × 10 ²⁰ atoms / cm ³ ), and 0 V or +50 V is applied to the polysilicon trench filling region 8. ~ Shown in FIG. FIG. 12 shows the case where the collector depletion layer does not reach the silicon oxide film 9a (W = 13.
5 μm) and in this case BVCEO was 54V. In FIG. 13, the collector depletion layer reaches the silicon oxide film 9a (W = about 3 μm), and the +
BVCEO was 55V when 50V was applied.
FIG. 14 shows the case where the collector depletion layer reaches the silicon oxide film 9a (W = about 3 μm) and 0V is applied to the polysilicon groove filling region 8, and BVCEO was 75V.

It can be seen from FIG. 14 that the breakdown voltage can be significantly improved by grounding the polysilicon trench filling region 8. Another mode is shown in FIG. (A) In the above embodiment (FIG. 1), the polysilicon groove filling region 8 is grounded, but the polysilicon groove filling region 8 may be floating and the N ⁻ region 11 outside thereof may be grounded. Also, the polysilicon trench filling region 8 and the N ⁻ region 11 are formed.
Both may be grounded. In this case, if the polysilicon groove filling region 8 has a low concentration, it will be depleted and function as a dielectric, and if it has a high concentration, it will settle to some potential due to leakage. Therefore, when the polysilicon trench filling region 8 is floated (when no electrode contact is made), it is preferable that the polysilicon trench filling region 8 has a low impurity concentration, and a potential close to the emitter potential is applied through electrode contact. In this case, it is preferable that the impurity concentration be such that a portion that is not depleted remains.

However, if the polysilicon groove filling region 8 (that is, the trench T2) between the P ⁺ base region 5 and the N ⁺ surface collector region 7 is floating,
Since the influence of the N ⁺ surface collector region 7 bends the depletion layer of the N ⁻ collector breakdown voltage region 4 directly below the P ⁺ base region 5,
It is preferable that at least the polysilicon groove filling region 8 of the trench T2 has a high impurity concentration and is fixed to the ground potential or a potential close thereto to block the electrostatic influence from the surface collector region 7.

Of course, in the first embodiment, the polysilicon groove filling region 8 may be depleted and the N ⁻ region 11 adjacent to the silicon oxide film 9a may be grounded. Even in this case, the withstand voltage can be improved in the collector withstand voltage region other than the silicon oxide film 9b. (B) In the above embodiment (FIG. 1), the polysilicon groove filling region 8 in the trench T1 and the polysilicon groove filling region 8 in the trench T2 have the same impurity concentration, but they may be changed. For example, only the trench T2 may have a high impurity concentration and a ground potential, the polysilicon groove filling region 8 of the trench T1 may have a low impurity concentration, and the N ⁻ region 11 outside the trench T1 may be grounded. (C) In the above embodiment, only one bipolar transistor is shown, but with this bipolar transistor, CMOS, lateral PNP bipolar transistor,
Of course, IIL and the like can be integrated. (Embodiment 2) Another embodiment is shown in FIG.

In this embodiment, the base region 5 is completely surrounded by the trench T2, that is, the silicon oxide film 9b,
Moreover, the polysilicon groove filling region 8 in the trench T2 has a high impurity concentration and is grounded. By doing so, the polysilicon groove filling region 8 in the trench T1 can be made to have a low impurity concentration, the collector parasitic capacitance of the transistor can be reduced, and the frequency characteristic can be improved while lowering the breakdown voltage and reducing the size. . (Embodiment 3) Another embodiment is shown in FIG.

In this embodiment, the lateral width of the polysilicon groove filling region 8 of the trench T2 separating the base region 5 and the surface collector region 7 is made larger than the lateral width of the polysilicon trench filling region 8 of the trench T1. Is. In this way, the polysilicon groove filling region 8 in the trench T2 is
Even if the impurity concentration is low, the influence of the high potential of the surface collector region 7 is less likely to reach the collector breakdown voltage region 4 immediately below the base region 5, and the bending of the collector depletion layer can be reduced, thus improving the breakdown voltage. To do.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing a process of Example 1.

FIG. 3 is a cross-sectional view showing a process of Example 1.

FIG. 4 is a cross-sectional view showing a process of Example 1.

FIG. 5 is a plan view showing a transistor model for explaining a function and effect of the semiconductor device of the first embodiment.

6 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

7 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

8 is a sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

9 is a characteristic diagram showing the relationship between the maximum electric field strength and the lateral width W of the collector breakdown voltage region on the outer side in the horizontal direction of the base region of the transistor of FIG.

10 is a characteristic diagram showing the relationship between the lateral width W and the collector / emitter breakdown voltage of the transistor of FIG.

11 is a characteristic diagram showing the relationship between the lateral width W of the transistor of FIG. 5, the collector / emitter breakdown voltage, and the impurity concentration of the collector breakdown voltage region.

12 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

13 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

14 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

FIG. 15 is a cross-sectional view showing a semiconductor device of Example 2.

FIG. 16 is a sectional view showing a semiconductor device of Example 3;

[Explanation of symbols]

1 is an N ⁺ silicon substrate (semiconductor substrate), 2 is a silicon oxide film, 3 is an N ⁺ buried collector region, 4 is an N ⁻ collector breakdown voltage region, 5 is a P ⁺ base region, 6 is an N ⁺ emitter region, 7 Is an N ⁺ surface collector region, 8 is a polysilicon region (adjacent semiconductor region), 9a is a first side surface isolation insulator region,
9b is a second side surface isolation insulator region.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Osamu Ishihara 1-1, Showa-cho, Kariya city, Aichi Nihon Denso Co., Ltd.

Claims (5)

[Claims] 1. A high-concentration first-conductivity-type buried collector region isolated from a semiconductor substrate, a low-concentration first-conductivity-type collector breakdown voltage region formed on the buried collector region, and an island-shaped one. A first side surface isolation insulator region that insulates and separates side faces of both regions, a second conductivity type base region formed on a surface portion of the island-shaped collector breakdown voltage region, and a surface portion of the island-shaped collector breakdown voltage region. A high-concentration first-conductivity-type surface collector region formed separately from the base region, a high-concentration first-conductivity-type emitter region formed on the surface of the base region, and the first side surface isolation insulator In a semiconductor device comprising an adjacent semiconductor region adjacent to the island-shaped semiconductor breakdown voltage region with a region sandwiched therebetween, the base region and the surface collector region are insulated and separated from each other, and the surface of the buried collector region is separated. The semiconductor device, characterized in that it comprises a second side isolation insulator region reached. 2. The semiconductor device according to claim 1, wherein the first side surface isolation insulator region is in contact with a side surface of the base region. 3. The semiconductor device according to claim 2, wherein a potential closer to the potential of the emitter region than the potential of the surface collector region is applied to the adjacent semiconductor region. 4. The adjacent semiconductor region is formed of the first and second semiconductor regions.
4. The semiconductor device according to claim 3, comprising a polysilicon groove filling region surrounding the base region with a side surface isolation insulator region interposed therebetween. 5. The semiconductor device according to claim 4, wherein the same potential as that of the emitter region is applied to the polysilicon trench filling region.