JP3052975B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar transistor (BPT) whose at least one side is dielectrically separated.

[0002]

2. Description of the Related Art In a semiconductor device mounted on a vehicle such as a microcomputer for controlling a vehicle engine used in a high noise environment, it is important to improve the withstand voltage even if the disadvantages of a slight decrease in the degree of integration and an increase in the number of manufacturing processes are accepted. Dielectric isolation structure and whole-surface (side and bottom) dielectric isolation structure (Japanese Patent Laid-Open No. 48-10008)
No. 1) is suitable.

[0003]

In such a bipolar integrated circuit, in order to reduce the transistor size and improve the integration degree, the horizontal distance from the base region to the side-surface isolation insulating film (that is, the base region). It is necessary to reduce the width (W) of the outer collector breakdown voltage region. However,
When the horizontal distance W is reduced, the degree of integration is improved, but the collector breakdown voltage BVceo is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a bipolar semiconductor device capable of improving both breakdown voltage and integration degree.

[0005]

According to the present invention, there is provided a semiconductor device comprising:
A buried collector region of high impurity concentration in the first conductivity type formed on a substrate, a collector withstand voltage region of low impurity concentration first conductivity type formed in an upper portion of the buried collector region, a surface of the collector withstand voltage region its inside is formed from the base from the collector of the second conductivity type base region forming a PN junction with the withstand voltage region, the surface of the base region and the collector withstand voltage region in contact with the entire circumference side of
Than source region is deeply formed, the a predetermined region and the base <br/> region enclose side isolation insulator region immediately under the base region, the table of the base region of the collector withstand voltage region
An emitter region of the first conductivity type formed in surface portion, said co
A collector surface contact region of high impurity concentration in the first conductivity type formed apart from said base region in a surface of the collector withstand voltage region, surrounds the predetermined area through a side surface separation insulator region, the collector breakdown voltage Area, embedding
Also insulated and separated from one of the collector region and the collector surface contact region, said collector surface contact region
And an adjacent semiconductor region to which a potential closer to the potential of the emitter region than the potential of the emitter region is applied.

Here, the side-surface isolation insulator region is embedded.
It is only necessary to reach the vicinity without contacting the surface of the collector region. For example, this embedded from the emitter region bottom
80 real depth of the collector withstand voltage region to Kuta area surface
% Or more as long as the side surface isolation insulator region is formed.

[0007] According to a preferred embodiment, Kore embedding substrate
Which has a bottom isolation region between the Kuta area,
The side isolation insulator region reaches the bottom isolation region except for a region between the predetermined region and the collector surface contact region. According to a preferred aspect, the adjacent semiconductor region is
At least in a region between the predetermined region and the collector surface contact region, the region is formed of a high impurity concentration polysilicon region filled in the side surface isolation insulator region .
According to a preferred aspect, the same potential as that of the emitter region is applied to the adjacent semiconductor region.

[0008]

[Action and effect of the invention] Buried in the insulator area
The side surfaces of the collector region and the collector breakdown voltage region are adjacent semiconductor regions.
-Separated bipolar transistor insulated from metal
The star is in contact with and surrounding the base region
Side isolation between base and surface collector regions
An object region is formed.

[0009] As a result, base - an electrically insulating the side surface isolation insulator region of this between the source region and the surface collector region area - horizontal distance shortened even base between the source region and the surface collector region It is ensured, and, since the side surface isolation insulator region does not divide the buried collector region as described above insulator region, base - conduction between the buried collector region and the surface collector region immediately below source region is ensured.

[0010] That is, the semiconductor device of the present invention, the side surface isolation insulator region, base without dividing the buried collector region - since isolation of the source region and the surface collector region, base - source region and the surface collector The distance between the transistor and the region can be shortened, and the transistor size can be reduced without lowering the breakdown voltage. In particular, base - across the side surface isolation insulator region source region is adjacent the adjoining semiconductor regions (for example, polysilicon trench fill area), applying a low potential such as this in the adjacent semiconductor region eg emitter potential, aspects isolation bending of the collector depletion layer formed in a portion of the collector withstand voltage region close to the object region is suppressed, whereby the electric field concentration is relaxed, so the yield is suppressed at this portion, base - the entire circumference of the source region can be obtained an excellent effect of also aim to reduce the transistor size in direct contact with the side surface isolation insulator region can suppress the breakdown voltage decrease.

[0011]

(Embodiment 1) Hereinafter, a high breakdown voltage NPN bipolar transistor having an entire dielectric isolation structure will be described as one embodiment of a semiconductor device of the present invention. 1 P- silicon substrate (substrate), 2 is a silicon oxide film for bottom insulation, 3 N + buried collector area, 4 N- collector withstand voltage area, 5 P + base area, the 6 N +
An emitter region, 7 is an N + surface collector region ( collector surface contact region), 8 is a polysilicon trench filling region (adjacent semiconductor region) for filling a trench, and 9a is an island-like buried collector region 3 and its A silicon oxide film surrounding the side surface of the collector breakdown voltage region 4 immediately above, and a silicon oxide film 9b surrounding the side surface of the base region 5 and separating the base region 5 and the surface collector region 7 (side surface isolation insulator region) It is.

Numeral 10 denotes a silicon oxide film on the surface, E, B, and C denote emitter contact electrodes, base contact electrodes, and collector contact electrodes made of aluminum, respectively. Numeral 12 denotes a bipolar electrode sandwiching the silicon oxide film 9a. An N ⁺ contact region formed on the surface of the N ⁻ region 11 surrounding the side surface of the transistor, and 13 is a contact electrode thereof.

In this embodiment, both ends of the polysilicon groove filling region 9b are connected to the polysilicon groove filling region 9a, and are grounded together with the contact electrode 13. A ground potential or a potential close to the ground potential is applied to the emitter electrode E. The manufacturing process of this transistor will be described below. First, as shown in FIG. 2, an N ^- type (100) single crystal silicon substrate 40 having a mirror-polished specific resistance of 3 to 5 Ω · cm is prepared, and 3 μm of antimony is diffused on the surface thereof using a vapor phase diffusion method. To form an N ⁺ diffusion layer 30.
Separately, one principal surface of the P ^- substrate 1 is mirror-polished and then thermally oxidized to form a silicon oxide film 2 having a thickness of about 1.0 μm. These silicon substrate 1 and silicon substrate 40
Is heated in a H ₂ O ₂ —H ₂ SO ₄ mixture, subjected to a hydrophilic treatment, and bonded together in a clean atmosphere at room temperature.
Heat treatment was performed for 2 hours in an atmosphere of N _{2 for} bonding. Subsequently, the substrate 40 was mirror-polished to a predetermined thickness to a thickness of 14 μm to produce an SOI substrate.

Next, as shown in FIG. 3, a field oxide film of about 0.5 μm is formed on the surface of this SOI substrate by thermal oxidation, and a 0.1 μm silicon nitride film is formed thereon by LPCVD. Next, a resist mask is formed on the silicon nitride film, and plasma etching using a fluorine-based etching gas, hydrofluoric acid etching, and reactive ion etching using a fluorine-based etching gas are performed.
Silicon oxide film 2 around the region where the transistor is to be formed.
Is formed, and the surface of the trench T1 is oxidized to form a silicon oxide film 9a. Subsequently, polysilicon is deposited by the LPCVD method to bury the trench region T1. Next, the polysilicon on the surface of the silicon nitride film is removed, the surface of the polysilicon exposed from the trench T1 is oxidized, and then the silicon nitride film is removed by dry etching. As a result, a polysilicon trench filling region 8 surrounded by the silicon oxide film 9a is formed inside the trench T1. This polysilicon trench filling region is doped with N ⁺ . Then, island-shaped N ⁺ buried collector region 3 and N ⁻ collector breakdown voltage region 4 are formed separately from N ⁺ diffusion layer 30 and N ⁻ region 40 by silicon oxide film 9a.

Next, as shown in FIG.
1, the trench T2, the silicon oxide film 9b, and the polysilicon trench filling region 8 in the trench T2 are formed by the same process as the formation process of the silicon oxide film 9a and the polysilicon trench filling region 8 in the trench T1. The trench T
2 is formed between the expected base region and the surface collector region until the surface of the buried collector region 3 is reached, and both polysilicon trench filling regions 8 and 8 of the trenches T1 and T2 are brought into contact and electrically connected. Conducted.

Next, as shown in FIG. 1, a P ⁺ base region 5, an N ⁺ emitter region 6, an N ⁺ surface collector region 7, an N <sup>+
+ A</sup> contact region 12 is formed by a photolithography process, an ion implantation process, and a drive-in process.
Opening 0, the electrodes E, B, C and 13 are formed. Although not shown, a predetermined 1
A contact electrode that contacts the location is formed similarly.

Incidentally, all side surfaces of base region 5 are formed in contact with silicon oxide films 9a and 9b, and all side surfaces of surface collector region 7 are also formed in contact with silicon oxide films 9a and 9b. As a result, all side surfaces of N ⁻ collector breakdown voltage region 4 immediately below base region 5 are also formed in contact with silicon oxide films 9a and 9b. In this way, the base
Since the side surface of the source region 5 is formed directly in contact with the side surfaces of the silicon oxide films 9a and 9b without passing through the N ⁻ collector breakdown voltage region 4, the planar dimensions of the transistor can be reduced by that much, and the integration degree can be reduced. Can be improved. By the way,
When the planar dimensions of the source region 5 were made equal, the area could be reduced to 1/8 of that of the conventional junction separation type bipolar transistor.

In addition, by grounding the polysilicon trench filling region 8, the withstand voltage can be improved. The polysilicon trench filling region 8 is made floating potential or depleted,
The N ⁺ region 12 may be grounded as an adjacent semiconductor region in the present invention. An example of the parameters of each unit will be described. N ^-
The impurity concentration of the collector breakdown voltage region 4 is 1 × 10 ¹⁵ atoms / c.
m ³ , the impurity concentration at the surface of the P ⁺ base region is 3 ×
10 ¹⁸ atoms / cm ³ , the impurity concentration on the surface of the N ⁺ emitter region 6 is 1 × 10 ²⁰ atoms / cm ³ , and the base region 5
Withstand voltage region 4 between gate electrode 3 and buried collector region 3
Is 4 μm, the impurity concentration of the polysilicon trench filling region 8 is 1 × 10 ²⁰ atoms / cm ³ , the width is 1 μm, the thickness of the silicon oxide films 9a and 9b is 0.7 μm, and the base region 5 is The thickness was 3 μm. Next, the fact that the breakdown voltage is improved by grounding the polysilicon trench filling region 8 will be described with reference to the transistor model of FIG. 5 and the relationship between the planar shape of the base region 5 and the breakdown voltage with reference to FIGS. explain.
The transistor of FIG. 5 is formed by omitting the trench T2 and separating the base region 5 from the silicon oxide film 9a in the transistor of FIG.

However, it is assumed that the emitter region 6 and the N ⁺ contact region 13 (having the same potential as the N ⁻ region 11) are grounded, and +50 V is applied to the N ⁺ buried collector region 3. It is assumed that the polysilicon groove filling region 8 is an N ⁻ region and is substantially an insulator together with the silicon oxide film 9a. 6 to 8 show vertical cross sections of the collector depletion layer when the horizontal width W of the N ⁺ collector breakdown voltage region 4 between the side edge of the base region 5 and the silicon oxide film 9a is 15 μm, 10 μm, and 5 μm. Show the shape. Note that the horizontal width W is a value of the resist mask opening pattern. The edge of the opening pattern of the mask is displaced by 2.5 μm with respect to the edge on the surface of the base region 5.

6 and 7 show that the grounded N ^- region 11
Of the depletion layer formed in the N ⁺ collector breakdown voltage region 4 between the side edge of the base region 5 and the silicon oxide film 9a due to the potential influence of It can be seen that the shape becomes approximately flat in the horizontal direction. When the bending is small, the breakdown voltage of the transistor is improved due to electric field concentration.

FIG. 9 shows a simulation result of how the maximum electric field intensity in the collector breakdown voltage region 4 changes when the horizontal distance W is variously changed. From FIG. 9, the distance W
It can be seen that the maximum electric field intensity decreases as the value decreases. That is, since the silicon region 11 has a low potential, the low potential of the silicon region 11 is
(Includes the polysilicon filling region 8. In this case, it is assumed that the impurity concentration of the polysilicon filling region 8, which is a floating potential, is low and depleted, or the polysilicon filling region 8 is replaced with a silicon oxide film. And the collector breakdown region 4 near the side surface of the base region 5 is electrostatically influenced (electrostatically set to a low potential). The electric field in the depletion layer in the collector breakdown voltage region 4 near the side surface of the region 5 is reduced. As a result, the depletion layer electric field in the vicinity of the corner of the base region 5 where the avalanche collapse occurs at the highest concentration of the electric field and the avalanche collapse occurs first is reduced, and the withstand voltage is improved.

FIG. 10 shows a simulation result of the collector-emitter breakdown voltage BVCEO when the base is opened when the distance W between the base region 5 and the silicon oxide film 9a is changed and the other conditions are the same as above. The width of the depletion layer at this time is 9 μm. It is understood that BVCEO is improved when the depletion layer reaches the side isolation region 9.

FIG. 11 shows a simulation result of BVCEO when the impurity concentration and W of the N ⁻ collector breakdown voltage region 4 are variously changed in the model of FIG. It can be seen that a breakdown voltage of 120 to 130 V can be realized under the best conditions. Each of the above data is in the N ^- region 11
Were grounded and the polysilicon trench-filled region 8 was depleted, but almost the same data was obtained under the condition that the impurity concentration of the polysilicon trench-filled region 8 was high and grounded. .

Next, the collector voltage +50 is applied to the N ⁻ region 11.
FIG. 12 shows the state of the depletion layer when V is applied, the polysilicon trench filling region 8 is set to N ⁺ (about 1 × 10 ²⁰ atoms / cm ³ ), and 0 V or +50 V is applied to the polysilicon trench filling region 8. To FIG. FIG. 12 shows a case where the collector depletion layer does not reach the silicon oxide film 9a (W = 13.
BVCEO was 54 V in this case. FIG. 13 shows that the collector depletion layer reaches the silicon oxide film 9a (W = about 3 μm) and the polysilicon depletion region 8 has +
When applying 50V, BVCEO was 55V.
FIG. 14 shows a case where the collector depletion layer reaches the silicon oxide film 9a (W = approximately 3 μm) and 0 V is applied to the polysilicon trench filling region 8, and BVCEO is 75V.

From FIG. 14, it can be seen that grounding the polysilicon trench filling region 8 achieves a remarkable improvement in withstand voltage. Another embodiment is shown in FIG. (A) In the above embodiment (FIG. 1), the polysilicon trench filling region 8 is grounded. However, the polysilicon trench filling region 8 may be floating, and the N ⁻ region 11 outside thereof may be grounded. Also, the polysilicon trench filling region 8 and the N ⁻ region 11
May be grounded. In this case, if the polysilicon trench filling region 8 is low in concentration, it is depleted and functions as a dielectric, and if the concentration is high, it is settled at some potential due to leakage. Therefore, when the polysilicon trench filling region 8 is to be floating (when no electrode contact is made), it is preferable that the polysilicon trench filling region 8 has a low impurity concentration, and a potential close to the emitter potential is applied by electrode contact. In such a case, it is preferable that the impurity concentration be such that a portion that is not depleted remains.

However, if the polysilicon trench filling region 8 between the P ⁺ base region 5 and the N ⁺ surface collector region 7 (that is, of the trench T2) is floating,
Since the influence of the N ⁺ surface collector region 7 causes the depletion layer of the N ⁻ collector breakdown voltage region 4 immediately below the P ⁺ base region 5 to be bent,
It is preferable that at least the polysilicon trench filling region 8 of the trench T2 has a high impurity concentration and is fixed to the ground potential or a potential close to the ground potential, so that the electrostatic effect from the surface collector region 7 is cut off.

Of course, in the first embodiment, the polysilicon trench filling region 8 may be depleted, and the N ⁻ region 11 adjacent to the silicon oxide film 9a may be grounded. Even in this case, the withstand voltage can be improved in the collector withstand voltage region other than the silicon oxide film 9b. (B) In the above embodiment (FIG. 1), the polysilicon trench filling region 8 in the trench T1 and the polysilicon trench filling region 8 in the trench T2 have the same impurity concentration, but may be changed. For example, only the inside of the trench T2 may be set to the high impurity concentration and the ground potential, the polysilicon trench filling region 8 of the trench T1 may be set to the low impurity concentration, and the N ⁻ region 11 outside the trench T1 may be grounded. (C) In the above embodiment, only one bipolar transistor is shown, but together with this bipolar transistor, CMOS, lateral PNP bipolar transistor,
Of course, IIL and the like can be integrated. (Embodiment 2) Another embodiment is shown in FIG.

In this embodiment, the periphery of the base region 5 is completely surrounded by the trench T2, that is, the silicon oxide film 9b.
Further, the polysilicon trench filling region 8 in the trench T2 has a high impurity concentration and is grounded. By doing so, the polysilicon trench filling region 8 in the trench T1 can be made to have a low impurity concentration, the collector parasitic capacitance of the transistor can be reduced, and the frequency characteristics can be improved while reducing the breakdown voltage and the size. . (Embodiment 3) Another embodiment is shown in FIG.

In this embodiment, the width of the polysilicon trench filling region 8 of the trench T2 separating the base region 5 and the surface collector region 7 is formed larger than the width of the polysilicon trench filling region 8 of the trench T1. It is. In this manner, the polysilicon trench filling region 8 in the trench T2 is formed.
Even if the impurity concentration is low, the influence of the high potential of the surface collector region 7 is unlikely to reach the collector breakdown voltage region 4 immediately below the base region 5, the bending of the collector depletion layer can be reduced, and the breakdown voltage can be improved. I do.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing a process of Example 1.

FIG. 3 is a cross-sectional view showing a process of the first embodiment.

FIG. 4 is a cross-sectional view showing a process in the first embodiment.

FIG. 5 is a plan view showing a transistor model for describing the operation and effect of the semiconductor device of the first embodiment.

6 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

7 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

8 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor in FIG.

9 is a characteristic diagram showing a relationship between a lateral width W of a collector breakdown voltage region horizontally outside a base region of the transistor of FIG. 5 and a maximum electric field intensity.

FIG. 10 is a characteristic diagram showing a relationship between the lateral width W and the collector / emitter breakdown voltage of the transistor of FIG.

11 is a characteristic diagram showing a relationship between the lateral width W, the collector / emitter breakdown voltage, and the impurity concentration of a collector breakdown region of the transistor of FIG.

12 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor in FIG.

13 is a cross-sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

14 is a sectional view showing a potential distribution of a collector depletion layer of the transistor of FIG.

FIG. 15 is a cross-sectional view illustrating a semiconductor device according to a second embodiment.

FIG. 16 is a cross-sectional view illustrating a semiconductor device according to a third embodiment.

[Explanation of symbols]

1 N + silicon substrate (board), 2 silicon oxide film,
3 is an N + buried collector region, 4 is an N- collector breakdown voltage region, 5 is a P + base region, 6 is an N + emitter region, 7
The N + surface collector region, 8 is a polysilicon region (adjoining semiconductor region), 9a are Insulator region, 9b are side faces isolation insulator region.

Continuation of the front page (72) Inventor Osamu Ishihara 1-1-1 Showa-cho, Kariya-shi, Aichi Japan Inside Denso Co., Ltd. (56) References JP-A-2-207568 (JP, A) JP-A-63-175440 (JP) , A) JP-A-61-174741 (JP, A) JP-A-60-1771738 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 21/762 H01L 29/73

Claims (5)

(57) [Claims] A buried collector region of a first conductivity type and a high impurity concentration formed on a substrate; a collector breakdown voltage region of a first conductivity type and a low impurity concentration formed on the buried collector region; Formed from the surface of the collector breakdown voltage region to the inside thereof,
Forming a PN junction with the collector breakdown voltage region;
Conductivity type base region and the said contact with the entire peripheral side portion of the base region from the surface of the collector withstand voltage region base region deeper formed than the predetermined region immediately under the base region of the collector withstand voltage region and and said base region to enclose side isolation insulator region, Emi the first conductivity type formed in a surface portion of said base region
A collector region and a surface of the collector breakdown voltage region separated from the base region.
A collector surface contact region of high impurity concentration in the first conductivity type formed Te, and <br/> both surrounding the predetermined area through a side surface separation insulator region, the collector withstand voltage region, the buried collector region and A semiconductor device, comprising: an adjacent semiconductor region that is insulated and separated from any of the collector surface contact regions, and to which a potential closer to the potential of the emitter region than the potential of the collector surface contact region is applied. 2. The semiconductor device according to claim 1, further comprising a bottom insulating isolation region between said substrate and said buried collector region, wherein said side isolation insulator region except for a region between said predetermined region and said collector surface contact region. 2. The semiconductor device according to claim 1, wherein the semiconductor device reaches the bottom insulating isolation region. 3. The high-impurity-concentration polysilicon region filled in the side-surface isolation insulator region at least in a region between the predetermined region and the collector surface contact region. the semiconductor device according to claim 1 or 2, wherein the. 4. The method according to claim 1, wherein the adjacent semiconductor region has the emitter voltage.
Claim, characterized in that position the same potential is applied 3
13. The semiconductor device according to claim 1. 5. The first conductivity type is N-type, and the second conductivity type is
Is a P-type, and the adjacent semiconductor region is grounded.
The semiconductor according to any one of claims 1 to 4, wherein
Body device .