JPH03104284A - Insulated gate bipolar transistor - Google Patents

Abstract

PURPOSE:To decrease resistance component of a P-type well region and suppress occurrences potential difference at a PN junction part by forming channel parts along sidewalls of a 1st trench and a 2nd trench and providing an emitter electrode which is in contact with each N<+> type emitter region and each P-type well region. CONSTITUTION:One of the sides of an N<+> type emitter region 19, faces the sidewall of a 3rd trench 18 and is in contact with an emitter electrode 20 and the other side of its region faces the sidewalls of a 1st trench 14 and a 2nd trench 15. In a P-type well region 13 which is sandwiched between the N<+> type emitter 19 and an N-type layer 12, when control voltage is applied to gate electrodes 17, inversion layers are formed along the 1st trench 14 and the 2nd trench 15 and then, such parts are formed into channel parts 21. In PN junction which is formed by the N<+> type emitter region 19 and the P-type well region 13, the distance from the part with which the emitter electrode 20 is in contact to a part of the PN junction, in other words, to the PN junction in the vicinity of each channel part 21 can be shortened. The value (r) of resistance component in the lateral direction of the P-type well region 13 is thus reduced as compared with conventional values.

Description

[Detailed description of the invention] <A> Industrial application field The present invention relates to an insulated gate bibolar transistor (IG
BT), particularly regarding prevention of parasitic rhinoceros latch-up. (Example) Conventional technology In general, IGBT devices operate in a bibolar manner, so they can provide lower voltage and larger current capacity than power MOS devices, but they have a parasitic PNPN thyristor structure, which causes latch-up problems. For example, there is a device that improves this latch-up described in Japanese Patent Application Laid-Open No. 1-125979. Its structure is shown in Figure 2. In the figure, (1) is P+
type semiconductor substrate, (2> is an N-type semiconductor layer, (3> is an N-type semiconductor layer (2) has a P-well region formed on the surface, (4> is a P-well region (3> is an N+-type emitter formed on the surface) (5) is a gate insulating film (7) on the channel part (6).
The gate electrode (8> is provided through the P well region (3)
), (9) is the trench (8)
This is an emitter electrode that is embedded in the N+ type emitter region (4) and electrically connects the P-well region (3). According to this structure, the lateral resistance r of the P-well region (3) is This suppresses the potential difference between the P well region (3) and the N+ type emitter region <4> from expanding.
'' type emitter region (4) as collector, P well region (
A parasitic NPN transistor having 3) as a base and the N-type semiconductor layer (2> as an emitter) becomes less likely to be ONL, and as a result, a si-risk operation becomes less likely to occur.

(c) Problems to be Solved by the Invention However, even in the structure shown in FIG. 2, the resistance r of the P well region (3) has not disappeared, and especially
8) In the PN junction near the lower channel part (6>) which is the farthest from the gate electrode (5>), a potential difference is still likely to occur due to the resistance r, which has the disadvantage of causing a si-risk operation.

(2) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks of the conventional art.
15), sandwich the other side with the third trench (l8),
The first and second trenches (14) (15) are provided with an insulating film (l).
6) By providing the gate electrode (17) through the channel part (21), the first and second trenches (14) (
A third trench (18) is formed along the side wall of the
has an N” type emitter region (19) and a P well region (13).
By providing an emitter electrode (20) in contact with both of the above, an insulated gate bipolar transistor is provided which eliminates the conventional drawbacks.

(*> Function) According to the present invention, the PN junction formed by the N4'' type emitter region (19) and the P well region (13) is connected to the first and second trenches (14), (15) and the third trench. (18) are sandwiched between the emitter electrode (20) and the channel part (21).
), the resistance r of the P-well region (13) decreases, making it possible to suppress the generation of potential difference at the PN junction.

(F) Example An example of the present invention will be described below in detail with reference to the drawings.

Figure 1 shows the cross-sectional structure of the insulated gate bibolar transistor according to this example. In the same figure, (11) is P
+ type silicon single crystal substrate, (12) is an N type semiconductor layer formed by epitaxial growth on the surface of substrate (11), (1
3> is a P-well region that is diffused and formed on the surface of the N-type semiconductor layer (12), and (14) and (15) are N-type semiconductors that penetrate from the surface of the N-type semiconductor layer (12) through the P-well region (l3). The first and second trenches reach the layer (12), and the gate insulator (16) is made of silicon oxide film (SiOm) etc. buried along the inner walls of the first and second trenches (14) and (15). The membrane (17) is the first and second trench (14) (
(13) is a gate electrode made of bonosilicon or the like embedded with an insulating film (16) in between; (18) is an N-type semiconductor layer (12) between the first and second trenches (14) and (15);
) A third trench (19) is provided on the surface and is dug halfway into the P-well region (13), and (19) is a connection between the first and second trenches (14), (15) and the third trench (18). The N0 type emitter region (20) formed on the surface of the P well region (13) sandwiched between is buried in the third trench (18), and the N+ type emitter region is formed on the inner wall of the third trench (18). It is an emitter electrode that is in close contact with both the region (19) and the P-well region (13).

One side of the N+ type emitter region (19) faces the side wall of the third trench (18) and is in contact with the emitter electrode (20), and the other side faces the side wall of the third trench (18) and contacts the emitter electrode (20).
15) facing the side wall. A gate electrode (13) is sandwiched between an N0 type emitter region (19) and an N type semiconductor layer (12).
When a control voltage is applied to 7), an inversion layer is formed along the side walls of the first and second trenches (14) (Is), and this portion becomes a channel portion (21).

The third trench (18) is preferably deep from the viewpoint of latch-up prevention, but the element breakdown voltage is
It is determined by the junction breakdown voltage between 〉 and N-type semiconductor layer 〈12〉,
Bottom of third trench (18) and N-type semiconductor layer 12>
The thickness of the P-well region (13) sandwiched between
The depth of 8〉 must be determined taking the above into account. According to this configuration, in the PN junction formed by the N1 type emitter region (19) and the P well region (13), the PN
Since the farthest part of the junction, that is, the distance to the PN junction near the channel part (21) can be shortened, the value of the lateral resistance component r of the P well region <13> can be reduced compared to the conventional one. As a result, the potential difference between the NI type emitter region (19) and the P well region (13) is prevented from expanding, and the thyristor operation is triggered from the P well region (13) to the N+ type emitter region (19). Since it is possible to prevent the base current from flowing, it is possible to prevent the element from falling into a silica operation.Although this embodiment refers to an IGBT, in a vertical MOSFET using a P+ type silicon single crystal substrate as an N type substrate, Vertical MO
This can also be applied to SFET. (G) Effect of the invention As explained above, according to the invention, the P well region (1
The lateral resistance component r of 3> is reduced, and the potential difference between the N1 type emitter region (19> and P well region
Since it prevents the current from spreading beyond v, it has the advantage of preventing the trigger current from flowing and preventing the risk operation. In addition, channel portions (21) are formed in the vertical direction in the first and second trenches (14) and (15), and in the third trench
18) increases the contact area with the N-type emitter region (19), which has the advantage of reducing chip size or increasing current capacity.

[Brief explanation of drawings]

Claims (2)

[Claims] (1) A semiconductor substrate of one conductivity type, a semiconductor layer of an opposite conductivity type on the surface thereof, a semiconductor layer of one conductivity type formed on the main surface of the semiconductor substrate, and the semiconductor layer of the one conductivity type formed on the surface of the semiconductor substrate. first and second trenches penetrating the conductive type semiconductor layer;
a control electrode embedded in the trench via an insulating film; and a third control electrode that does not penetrate the semiconductor layer of one conductivity type formed on the surface of the semiconductor substrate between the first trench and the second trench. a trench, a semiconductor layer of an opposite conductivity type formed on the surface of the semiconductor layer of one conductivity type sandwiched between the first or second trench and the third trench, and a semiconductor layer of an opposite conductivity type formed in the surface of the semiconductor layer of the one conductivity type, which is buried in the third trench. 1. An insulated gate bipolar transistor comprising: an electrode which makes ohmic contact with both the semiconductor layer of one conductivity type and the semiconductor layer of the opposite conductivity type on its sidewall. (2) The insulated gate bipolar transistor according to claim 1, wherein the third trench is shallower than the first and second trenches.