JP2002158356A - MIS semiconductor device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To improve the trade-off relationship between on-voltage / turn-off loss of a MOS semiconductor device such as an IGBT, increase latch-up withstand voltage, and reduce leakage current when a reverse voltage is applied. . A gate electrode is formed on a semiconductor substrate with an insulating film interposed therebetween.
Then, a p base region 6 and an n ⁺ emitter region 7 are formed in the thin film semiconductor layer 11 formed on the gate electrode 3 via the insulating film 5. By making the emitter layer thinner, the emitter structure can be miniaturized, and the p base region 6 can be formed.
By keeping the hole current in the transistor away from n ⁺ emitter region 7, the latch-up tolerance is increased. At the same time, the impurity concentration of the p base region 6 is reduced to reduce leakage current when a reverse voltage is applied, thereby enabling operation as a bidirectional device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a metal-insulating film.
The present invention relates to a MIS semiconductor device having a gate structure made of a semiconductor, and more particularly to a vertical MIS semiconductor device having an emitter structure using a thin film semiconductor layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art As one type of a high voltage MIS semiconductor device, an insulated gate bipolar transistor (Insulated Gate Bip) is used.
olar Transistor (hereinafter referred to as IGBT) is known. FIG. 15 is a cross-sectional view of a unit cell that is a unit structure of a planar IGBT of a conventional IGBT. This IGBT is of a non-punch-through type, and has a collector electrode 29, a p ⁺ collector layer 28, an n ⁻ drift layer 21, a p base region 26, and a p ⁺ contact region 26a from the bottom of the figure.
, N ⁺ emitter region 27, gate insulating film 25, gate electrode 2
3 and the emitter electrode 30.

FIG. 16 is a sectional view of a unit cell of another conventional IGBT, that is, a trench gate type vertical IGBT. This IGBT is of a non-punch-through type, and has a collector electrode 39, a p ⁺ collector layer 38, an n ⁻ drift layer 31, a p base region 36, a p ⁺ contact region 36a,
It comprises an n ⁺ emitter region 37 and an emitter electrode 40. In this IGBT, a gate electrode 33 is embedded in a trench 46 via a gate insulating film 35.

[0004]

However, the conventional IGBT as shown in FIG. 15 has three disadvantages. One is that miniaturization is difficult because the gate electrode 23 is formed on the surface of the semiconductor substrate. Therefore, it is difficult to reduce the on-state voltage, and it is difficult to improve the trade-off between the on-state voltage and the turn-off loss.

Second, a hole current flows through the p base region 26 around the n ⁺ emitter region 27. Due to the voltage drop due to the hole current, a parasitic thyristor including the n ⁺ emitter region 27, the p base region 26, the n ⁻ drift layer 21, and the p ⁺ collector layer 28 latches up, and the current cannot be controlled by the gate signal. There's a problem. Third, when a reverse voltage is applied as a bidirectional device, p ⁺
There is a problem that a large amount of holes are injected from the contact region 26a into the n ^- drift layer 21 and a large leakage current flows. To solve this third problem, the p ⁺ contact region 26a
If the impurity concentration is lowered, there is a problem that the above-mentioned parasitic thyristor is more likely to latch up.

[0006] In the trench gate IGBT of FIG. 16 as well, the problem of latch-up of the parasitic thyristor and the problem of reverse leakage current described above are similar, and both the p ⁺ contact region 36a and the n ⁺ emitter region 37 Since the contacting emitter electrode 40 is formed on the surface of the semiconductor substrate, there is a problem that miniaturization is difficult. Therefore, it is difficult to reduce the on-state voltage, and it is difficult to improve the trade-off between the on-state voltage and the turn-off loss.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, improve the trade-off between on-voltage and turn-off loss, prevent a parasitic thyristor from latching up, and reduce the leakage current when a reverse voltage is applied to a MIS semiconductor device. And a method for manufacturing the same.

[0008]

In order to achieve the above object, a MIS semiconductor device according to the present invention is to make the emitter portion thinner and finer. First, a gate electrode formed on a first conductive type semiconductor substrate via an insulating film, an insulating film covering side and top surfaces of the gate electrode, and a first conductive type thin film formed on the insulating film on the gate electrode A semiconductor layer, a connecting semiconductor portion connecting the semiconductor substrate and the first conductive type thin film semiconductor layer along a side portion of the gate electrode, and forming a portion of the thin film semiconductor layer on the gate electrode so as to cross the thin film semiconductor layer The second conductivity type base region, the first conductivity type emitter region formed at the end of the thin film semiconductor layer far from the connection semiconductor portion, the first conductivity type emitter region and the second conductivity type base region. An emitter electrode provided in contact with each other and a collector electrode formed on the back surface side of the semiconductor substrate are provided.

That is, since the second conductivity type base region and the first conductivity type emitter region are formed in the thin film semiconductor layer on the gate electrode wrapped with the insulating film, it becomes easy to apply fine processing. It can be miniaturized and the on-voltage can be reduced. Further, if the first conductivity type emitter region of the emitter portion is formed in contact with the second conductivity type base region,
Since the component of the current flowing in the base region along the boundary between the first conductivity type emitter region and the second conductivity type base region is reduced, the voltage drop is reduced and the parasitic thyristor is less likely to latch up.

Furthermore, since the parasitic thyristor is unlikely to latch up, the impurity concentration of the second conductivity type base region can be reduced. As a result, the amount of the second conductivity type carriers injected from the second conductivity type base region into the first conductivity type semiconductor substrate when a reverse voltage is applied is reduced, and the reverse leakage current can be reduced. The connecting semiconductor portion may be a semiconductor thin film layer or a part of a semiconductor substrate.

If a fourth electrode is provided on the surface of the thin film semiconductor layer near the connection semiconductor portion with an insulating film interposed therebetween, a voltage is applied to the fourth electrode when a forward voltage is applied, whereby the connection semiconductor portion is formed. By increasing the potential, electric field concentration caused by the corner of the gate electrode can be reduced. If the corner of the gate electrode is rounded, electric field concentration due to the corner of the gate electrode can be avoided.

An emitter electrode formed on the first conductive type semiconductor substrate via an insulating film; an insulating film covering side surfaces of the opposed emitter electrode; and a first conductive type thin film semiconductor formed on the emitter electrode A connecting semiconductor portion connecting the semiconductor substrate and the first conductive type thin film semiconductor layer along the side of the emitter electrode and the thin film semiconductor layer from the surface of the semiconductor substrate to a part of the thin film semiconductor layer on the emitter electrode; A second conductivity type base region formed as a first conductivity type emitter region formed at an end of the thin film semiconductor layer farther from the narrow portion,
An MIS semiconductor device including a gate electrode provided on the second conductivity type base region via an insulating film, and a collector electrode formed on the back surface side of the semiconductor substrate.

That is, the second conductivity type base region and the first conductivity type emitter region are formed in a thin film semiconductor layer on the emitter electrode, and a gate electrode is provided on the thin film semiconductor layer via an insulating film. This makes it easier to apply microfabrication, makes the cell width narrower, and lowers the on-voltage. Also in this case, the connecting semiconductor portion may be a thin film semiconductor layer or a part of the semiconductor substrate.

If the corner of the emitter electrode is rounded, electric field concentration due to the corner of the emitter electrode can be avoided. If the width W of the connecting semiconductor portion of the thin film semiconductor layer is 10 μm or less,
The on-voltage can be reduced by reducing the cell width. In forming the thin film semiconductor layer, a lateral epitaxial growth technique (Epitaxial Layer Overgrowth, hereinafter referred to as ELO) is applied. Specific methods include molecular beam epitaxy (Molecular Beam Epitaxy or MBE), chemical vapor deposition (Chemical Vaper Deposition or CVD), and liquid phase epitaxy (Liquid Phase).
Epitaxy, hereinafter referred to as LPE) can be used.

When MBE is used, the straightness of a molecular beam having uniform directivity is used. By irradiating the molecular beam at an angle close to the horizontal (for example, 10 degrees with respect to the horizontal plane), irradiating the side of the thin film with more molecular beams, and conversely, the molecular beam is hardly supplied to the surface of the thin film. Can be epitaxially grown in the lateral direction. When using CVD or LPE, anisotropic growth is used. Depending on the orientation of the crystal, there are two types: a surface that is stable, flattened and has a slow growth rate, and a surface that is rough and unstable and has a high growth rate where atoms are actively incorporated. Use. MBE can also utilize anisotropic growth.

The anisotropy of crystal growth differs depending on the material. In the case of silicon, the (111) plane is easily stabilized, and (1)
10) The surface is easily roughened. For gallium arsenide, (100)
The surface is easily stabilized, and the other surfaces are easily roughened. Therefore, when the first conductivity type semiconductor substrate is silicon, if the surface is the (111) plane, a flat surface can be easily obtained by utilizing anisotropy.

If the side surface of the thin film semiconductor layer is the (110) plane, the growth rate in the lateral direction increases. When the first conductive semiconductor substrate is gallium arsenide (GaAs), a flat surface can be easily obtained by using anisotropy if the surface is a (100) plane. As another type of MIS semiconductor device, a second conductivity type base region formed on a surface layer of a first conductivity type semiconductor substrate, and a first conductivity type emitter region formed on a surface layer of the second conductivity type base region A first trench that extends through the base region at least through the second conductivity type, reaches the semiconductor substrate, an insulating film formed on an inner wall of the first trench, and the semiconductor substrate and the second conductivity type via the insulating film. A gate electrode provided to face the base region, a second trench that extends through at least the first conductivity type emitter region and reaches the second conductivity type base region, and a second conductivity type base region inside the second trench and The semiconductor device may include an emitter electrode provided in contact with the first conductivity type emitter region and a collector electrode provided on the back surface side of the semiconductor substrate.

That is, by forming an emitter electrode for short-circuiting the base region of the second conductivity type and the emitter region of the first conductivity type in the second trench, it becomes easy to apply fine processing, the cell width is reduced, and the Voltage can be reduced. The distance t between the first trench and the second trench is 10 μm
In the following case, the cell width can be reduced and the on-voltage can be reduced.

The impurity concentration of the second conductivity type base region is 10
^If it is lower than ¹⁵ pieces / cm ^3, a latch-up of the parasitic thyristor is likely to occur due to a voltage drop due to a current flowing in the base region. Conversely, if it is higher than 10 ¹⁸ pieces / cm ³ ,
When a reverse voltage is applied, the injection amount of minority carriers from the base region to the semiconductor substrate increases, and the leakage current increases.

An IGBT provided with a second conductivity type collector region on the back surface side of the semiconductor substrate is an IGBT, and an IGBT lacking it is a MOSFET. The present invention relates to the emitter portion, and the collector structure is optional. M as above
As a method of manufacturing an IS semiconductor device, a connecting semiconductor portion and a thin film semiconductor layer are formed on a first conductivity type semiconductor substrate by epitaxial growth.

By the epitaxial growth, a connection semiconductor portion having good crystallinity and a thin film semiconductor layer are formed. The same applies to a MIS semiconductor device in which a thin film semiconductor layer is formed on an emitter electrode. Alternatively, a step of forming a mask on the first conductivity type semiconductor substrate, a step of performing isotropic etching, a step of forming an oxide film, a step of filling polysilicon in the etched concave portion, A step of forming an oxide film thereon, and forming a thin film semiconductor layer on the surface of the first conductivity type semiconductor substrate that is not etched by epitaxial growth. Is formed.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 is a sectional view of a unit cell which is a unit structure of an IGBT according to a first embodiment of the present invention.

A gate electrode made of polysilicon is formed on a high-resistance n ^- semiconductor substrate 1 via an insulating film 2 such as an oxide film.
3 are formed. The side surface and the upper surface of the gate electrode 3 are covered with insulating films 4 and 5 of an oxide film, for example. A thin-film semiconductor layer 11 is formed from the surface of the n ^- semiconductor substrate 1 to a position above the gate electrode 3 via the connecting semiconductor portion 12 on the side of the gate electrode 3, and an end of the thin-film semiconductor layer 11 far from the connecting semiconductor portion 12. A p base region 6 and an n ⁺ emitter region 7 are formed in the portion. Reference numeral 10 denotes an emitter electrode provided in common contact with the p base region 6 and the n ⁺ emitter region 7. On the back side of the n ^- semiconductor substrate 1, a p-collector region
8 and a collector electrode 9 is provided. In this IGBT, the insulating film 5 is a gate insulating film.

FIGS. 2 (a) to 2 (d) and FIGS. 3 (a) to 3 (a)
(D) is sectional drawing of the process order shown for every main manufacturing process of the IGBT which concerns on 1st Embodiment. In the following description, an n-channel IGBT will be exemplified. Hereinafter, the method of manufacturing the IGBT according to the first embodiment will be described with reference to the drawings. First, a high-resistance n ^- semiconductor substrate 1 is prepared, and an insulating film 2 covering the surface of the n ^- semiconductor substrate 1 is formed by thermal oxidation or CVD. Next, a polysilicon layer serving as a gate electrode 3 is formed on the insulating film 2 [FIG.
(A)].

Next, an insulating film 2 is formed using a mask (not shown).
After patterning the gate electrode 3 into a stripe shape [FIG. 2B], the insulating film 4 is thermally oxidized or CVD
[FIG. (C)]. Next, polishing is performed to smooth the surface, and the gate electrode 3 and the insulating film 4 are polished.
Are made equal [(d) in the figure].

Next, after an insulating film 5 is formed on the gate electrode 3 and the insulating film 4 [FIG. 3 (a)], a central portion of the insulating film 4 is opened in a stripe shape using a mask (not shown) [FIG. FIG. Next, epitaxial growth is performed from the exposed portion of the n ⁻ semiconductor substrate 1 by MBE, CVD, or LPE, and a shape is formed such that the thin film semiconductor layer 11 extends in the lateral direction via the n ⁻ type connecting semiconductor portion 12.

When MBE is used for epitaxial growth, a large number of molecules are supplied only to a specific surface using the directivity of a molecular beam having a uniform directivity, and are not supplied to the other surfaces. Selectively grow only the face that has received it. FIGS. 4A to 4C are perspective sectional views of the substrate surface for explaining the growth process. The gate electrode 3 is connected to the insulating film 2,
From the state covered with 4 and 5 (FIG. 4A), MBE is started and the molecular beam x3 is irradiated perpendicularly to the substrate until the connecting semiconductor portion 12 reaches the height of the upper surface of the insulating film 5. [Figure 4
(B)].

When the connecting semiconductor portion 12 reaches the height of the upper surface of the insulating film 5, the molecular beam x4 is made incident on the horizontal plane at a low angle of 10 degrees or less from the horizontal plane so that the side surface of the thin film semiconductor layer 11 extends. 4 (c)]. At this time, in the thin film semiconductor layer 11, the supply amount of the molecular beam per unit area to the side surface is more than five times as large as the supply amount to the upper surface. As a result, the speed at which the thin film semiconductor layer 11 extends in the horizontal direction is at least five times the speed at which the thin film semiconductor layer 11 extends in the upward direction.

In FIG. 4C, the thin film semiconductor layer 11 extends only in the right direction in the figure. However, since it is desirable to extend symmetrically, the direction of the substrate is changed during growth so that the left side extends. It is preferable that the molecular beam x4 be supplied.
This may be accomplished by constantly rotating the substrate during growth. Also, molecular beam sources are placed on both sides of the substrate,
x4 and molecular beams having symmetric directions may be simultaneously supplied from two directions.

When silicon is used as a material, MBE
The long condition is selected as follows. Epitaxial growth is 10
^-7From 10^-2Perform in a Pa ultra-high vacuum chamber. Minute
The following are examples of the source of the slave wire. Solid
How to evaporate recon with an electron gun, Knudsencel
A method of heating solid silicon and sublimating and evaporating it,
Such as a method of supplying with a sauce. Gas sources include:
Monosilane (SiH_Four), Monochlorosilane (SiH_Three
Cl), dichlorosilane (SiH)_TwoCl_Two), Triclo
Silane (SiHCl_Three), Tetrachlorosilane (Si
Cl _Four), Disilane (Si_TwoH₆)and so on.

The substrate temperature is from 300 ° C. to 1000 ° C., and the growth rate is from 0.1 μm / h to 100 μm / h. However, since a region where the reaction process of the epitaxial growth is controlled by the supply is desirable, the substrate temperature is set to 700 ° C. to 1000 ° C.
It is more desirable to set the range. On the other hand, there is a possibility that polysilicon is deposited on the surface of the insulating film 5, which adversely affects the shape, crystal quality, and device characteristics of the thin film semiconductor layer 11 formed by epitaxial growth. From such a viewpoint, it is desirable that the growth rate is slow because the deposition of polysilicon can be suppressed. However, an extremely slow growth rate impairs mass productivity. Therefore, considering this, the growth rate is 1 μm / h to 2 μm / h.
It is thought that it is better to set the degree.

Even if fine polysilicon nuclei are formed on the insulating film 5, the polysilicon can be removed by using the gas etching action before the polysilicon is enlarged. SiH ₃ C has strong etching action.
1, a gas containing a halogen element such as SiH ₂ Cl ₂ , SiHCl ₃ , and SiCl ₄ . In addition, SiH ₄ and Si ₂
Even if a small amount of hydrochloric acid gas (HCl) is added to H ₆ and supplied,
The etching action of HCl can suppress the deposition of polysilicon.

In controlling the shape of the thin film semiconductor layer 11 by MBE growth, as described above, in addition to the effect of the difference in the supply speed of molecules for each plane, anisotropic growth can be used as an auxiliary. This utilizes the fact that the growth rate differs depending on the plane orientation under the same growth environment. Here, a plane orientation that is easy to flatten on the surface of the thin film semiconductor layer 11 and is stable and has a low growth rate is selected, and a plane orientation that is rough and unstable on the side surface and has a high growth rate due to incorporation of atoms is selected.

The stable surface can be further stabilized by using a gas having an etching action. That is, even if a small crystal nucleus having an undesired direction is formed, the crystal nucleus can be removed by etching to prevent the growth. The etching action here is based on the same principle as the etching action on the insulating film, and a gas containing a halogen element is effective.

CVD or LPE for epitaxial growth
In the case of using, anisotropic growth is mainly used. The principle is the same as that described in the MBE section. For example, when a silicon substrate is used, the surface is (111), the stripe direction is <112>, and the side of the thin film is (110).
Exposure of the surface is advantageous. The reason is that the (111) plane of silicon has the property of being flattened and stable, and it is difficult to form nuclei necessary for growth. On the other hand, the (110) plane is rougher and more easily absorbs atoms.
1) Growth rate is faster than plane. Therefore, in order to form an epitaxial thin film that is long in the lateral direction, it is preferable that the upper surface be the (111) plane and the stripe direction be the <112> direction, so that the side surface is the (110) plane.

Using a gallium arsenide substrate for the same reason
In this case, the upper surface is the (100) surface, and the (100) surface
It is advisable to select an orientation where the (111) plane does not appear. Silicon C
VD growth conditions are as follows: substrate temperature 1000 ° C. to 1423 ° C.
SiH in range_Four, SiH_ThreeCl, SiH_TwoCl_Two, Si
HCl_Three, SiCl_Four, Si_Two H ₆Supply gas such as
A growth rate in the range of 0.1 μm / h to 100 μm / h
Is good. Above all, do not deposit polysilicon.
From the viewpoint of securing the mass productivity, 1 μm / h to 10 μm
The / h range seems to be good.

The conditions for LPE growth of silicon are as follows: a melt of a metal such as Sn or In at a temperature of 600 ° C. to 1000 ° C.
Dissolve i until it is saturated, contact it with the substrate at the same temperature, and gradually lower the temperature, from 0.1 μm / h to 100 μm / h
The growth rate is preferably in the range of When doping the thin film semiconductor layer 11 with an impurity during epitaxial growth, the following is performed.

In MBE and CVD, to dope a donor impurity, arsine (AsH ₃ ) or phosphine (PH ₃ ) gas is supplied simultaneously during growth. To dope the acceptor impurity, a diborane (B ₂ H ₆ ) gas is supplied simultaneously during the growth. In LPE,
To dope the donor impurity, arsenic (As) or phosphorus (P) is dissolved in the melt. To dope the acceptor impurity, boron (B) is dissolved in the melt.

Next, a p base region 6 and an n ⁺ emitter region 7 are formed by ion implantation and thermal diffusion [FIG.
(C)]. Here, the dose of the p base region 6 is 10 ¹¹
-10 ¹⁴ / cm ^2, and the impurity concentration after thermal diffusion is 10 ¹⁵
It is desirable to set it to 10 ¹⁸ / cm ³ . Further, it is desirable that the dose of the n ⁺ emitter region 7 be 10 ¹³ / cm ² or more and the impurity concentration after thermal diffusion be 10 ¹⁷ / cm ³ or more.

Next, ap ⁺ collector region 8 is formed on the back surface of the n ⁻ semiconductor substrate 1 by ion implantation and thermal diffusion, and finally, a collector electrode 9 and an emitter electrode 10 are formed to complete an n-channel IGBT 13. [FIG. (D)]. Withstand pressure 6
The typical dimensions of the 00V class IGBT 13 will be described with reference to FIG. First, it is desirable that the width W of the connecting semiconductor portion 12 be 10 μm or less. Even if W is 1 μm or less, the majority of the current flows through the storage layer formed near the insulating film 5, so that the on-resistance does not increase. The thickness t of the thin film semiconductor layer 11 is 10
μm or less.
The values of l, W2, and W3 can be reduced. If the thickness t of the thin film semiconductor layer 11 is 1 μm, W1, W2, and W3 are respectively
It can be 2 μm, 2 μm, 1 μm or less. The width of the unit cell is 20 μm or less, which can be reduced to less than half of the conventional width.

Assuming that the thickness t of the thin film semiconductor layer 11 is 0.1 μm, W1, W2, and W3 are also 0.2 μm, 0.2 μm,
It can be 0.2 μm. At this time, the factor that determines the cell width is the design rule or the connection semiconductor part.
The width W is 12 and the cell density can be further increased. The thicknesses of the insulating films tg1, tg2, and tg3 are 0.1 μm and 1 μm, respectively.
m and 1 μm or less. However, if tg2 and tg3 are too thin, avalanche breakdown is likely to occur due to electric field concentration caused by the corner of the gate electrode 3. It is desirable that the thickness tp of the gate electrode 3 be 10 μm or less.
The thickness is preferably 0.01 μm or more so that the gate resistance does not become huge.

In the 600 V breakdown voltage product, the thickness ts of the n ^- semiconductor substrate 1 is about 100 μm, and the thickness of the p collector layer 8 is 0.1 μm or more, up to about 300 μm. This IG
In the BT, the n ⁺ emitter region 7 and the p base region 6 are a thin film semiconductor layer 11, and the n ⁺ emitter region 7 is a p base region.
Since it is formed adjacent to 6, the microfabrication technology can be easily applied, and the cell width can be reduced. For example, the correlation curve between on-voltage and turn-off loss is about 30
% Improved.

In the connection semiconductor section 12, most of the current is supplied to the insulating film.
4 Because it flows through the storage layer formed near
The on-resistance does not increase because of the slimness of twelve. Further, the IGBT operates at the p-level of the thin-film semiconductor layer 11 during the ON operation.
Since the hole current flowing through the base region 6 passes through a region far from the boundary with the n ⁺ emitter region 7, the parasitic thyristor has a feature that it is difficult to latch up. A simulation that the latch-up withstand capability is ten times or more that of the conventional product was almost confirmed in an actual device.

Furthermore, in this IGBT, the parasitic thyristor is unlikely to latch up, so that the impurity concentration of the p base region 6 can be reduced to 10 ¹⁵ to 10 ¹⁸ / cm ³ .
As a result, when a reverse voltage is applied, the amount of holes injected from p base region 6 to n ⁻ drift layer 1 is reduced, so that leakage current can be reduced. If the impurity concentration of p base region 6 is set at 10 ¹⁵ / cm ³ , the leakage current can be reduced to about 1/100 of the conventional value. Therefore, the IGBT 13 can be used as a bidirectional device with little leakage current.

The present invention relates to the emitter structure, and the collector structure is optional. Therefore, the present invention is applied to a MOSFET and the like in addition to the IGBT. [Embodiment 2] FIG. 6 is a block diagram showing a second embodiment of the present invention.
It is sectional drawing of GBT. The parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

The difference from the first embodiment shown in FIG. 1 is that an insulating film 13 and a field plate electrode 14 are formed on a thin film semiconductor layer 11. When a positive voltage is applied to the field plate electrode 14 when a forward voltage is applied, the potential of the connection semiconductor portion 12 rises, and the electric field concentration due to the corner of the gate electrode 3 can be reduced. Thereby, there is an advantage that avalanche breakdown hardly occurs and the forward withstand voltage can be improved. In the case of an IGBT with a withstand voltage of 600 V class, a withstand voltage improvement of about 5% was observed.

Embodiment 3 FIG. 7 is a sectional view of an IGBT according to a third embodiment of the present invention. Parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. This embodiment differs from the IGBT of the first embodiment in that the gate electrode 3 is arranged above the p base region 6, and the emitter electrode is arranged below the p base region 6 and the n ⁺ emitter region 7.

In this embodiment, there is an advantage that the formation of the gate electrode 3 is facilitated as compared with the first embodiment. Further, the points of the manufacturing method of the present embodiment different from those of the first embodiment will be described below. After the insulating film 2 is formed on the surface of the n ^- semiconductor substrate 1, the insulating film 2 is patterned using a photo-etching process, and light etching is performed on the n ^- semiconductor substrate 1 using the pattern as a mask. An emitter electrode 10 is formed. Next, a window is opened in the insulating film 2 for performing epitaxial growth, and I of the first embodiment is opened.
The thin film semiconductor layer 11 is formed by performing epitaxial growth extending in the lateral direction similarly to the GBT. Here, the width W of the window opening may be as wide as 10 μm or more, unlike the first embodiment. Next, a p base region 6 and an n ⁺ emitter region 7 are formed, and an insulating film 5 and a gate electrode 3 are formed on the upper surface. Other steps are the same as in the first embodiment. The insulating film 5 becomes a gate insulating film.

Since epitaxial growth is performed after the formation of the emitter electrode 10, it is necessary to use polycrystalline silicon or a refractory metal such as tungsten for the emitter electrode 10. Embodiment 4 FIG. 8 shows an IG according to a fourth embodiment of the present invention.
It is sectional drawing of BT.

In the first embodiment, when the shapes of the gate electrode 3 and the insulating films 2, 4, and 5 are rounded, the electric field concentration is reduced, avalanche breakdown is less likely to occur, and the breakdown voltage is improved. IG withstand voltage of 600V class
In the case of BT, the breakdown voltage was improved by about 10%. FIG.
FIGS. 7A to 7D are cross-sectional views in the order of steps showing manufacturing steps for rounding the shapes of the gate electrode 3 and the insulating films 2, 4, and 5 according to the third embodiment.

A material serving as a mask, such as a photoresist, is patterned on the n ^- semiconductor substrate 1, and isotropically etched with a nitric acid, hydrofluoric acid, or acetic acid-based etchant [FIG. 9 (a)]. After removing the mask material, the surface is thermally oxidized, and then a polysilicon layer to be the gate electrode 3 is formed [FIG.

Next, the polysilicon layer is polished and flattened to form an oxide film 5 (FIG. 3C). A window is opened in the oxide film 5 [FIG. In the subsequent steps, a thin film semiconductor layer is deposited by epitaxial growth as in the first embodiment, and the subsequent processes are continued.

Also in the other second and third embodiments, when the shapes of the gate electrode 3 and the insulating films 2, 4, and 5 are rounded, the electric field concentration is reduced and the avalanche breakdown hardly occurs. The withstand voltage is improved. In the case where the thin film semiconductor layer is grown by MBE (when anisotropic growth is not used) in the examples described above, the plane orientation is not limited, so that the degree of freedom of the pattern of the thin film semiconductor layer is extremely high. FIG.
Is a perspective sectional view of an example in which a circular thin film semiconductor layer 11a is grown by MBE. Such a pattern shape can also be used.

In the case of CVD or LPE, since the plane orientation becomes important, it is preferable to adopt a stripe shape in which an appropriate orientation is selected. [Embodiment 5] FIG. 11 is a sectional view of an IGBT according to a fifth embodiment of the present invention. The parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

Hereinafter, an IGBT according to the fifth embodiment will be described.
A description will be given according to the manufacturing method. A p base region 6 is formed in the surface layer of the n ^- semiconductor substrate 1, and n ⁺
An emitter region 7 is formed. A first trench 16 that penetrates the p base region 6 from the surface and reaches the n ⁻ semiconductor substrate 1 is formed, and the inside of the first trench 16 is filled with the gate electrode 3 made of polysilicon via the insulating film 5. Close to the first trench 16, the n ⁺ emitter region 7 is removed from the surface.
A second trench 17 penetrating through to reach the p base region 6 is formed, and the second trench 17 is filled with the emitter electrode 10. On the back side of n ^- semiconductor substrate 1, p collector region 8 is formed, and collector electrode 9 is provided.

It is desirable that the distance t between the insulating film 2 and the emitter electrode is at least 10 μm or less and about 1 μm.
This embodiment differs from the first embodiment in that the emitter electrode 10 is embedded in the trench. Gate electrode
Not only 3 but also the emitter electrode 10 is buried in the second trench 17 formed by digging down the semiconductor device substrate in the vicinity of the first trench 14 so that the p base region 6 of the emitter section is thinned. As a result, similarly to the first embodiment, the unit cell can be miniaturized, the ON voltage is reduced, and the latch-up resistance is increased.

In the semiconductor device described above, a conventionally used technique can be used as the breakdown voltage structure. 12, 13, and 14 show examples in which a pressure-resistant structure is added. The source electrode is omitted. FIG. 12 is a perspective sectional view of a state in which a guard ring x5 is formed around the active portion where the thin film semiconductor layer 11 is formed. FIG. 13 shows an example in which a field plate x6 is formed around an active portion, in which a conductive material is formed in a stripe shape in a surrounding insulating film. It can be formed simultaneously with the formation of the gate electrode. FIG. 14 shows a case where a resistive nitride film x7 is formed as a resistive field plate around an active portion. In each of these cases, the electric field around the active portion is relaxed to increase the breakdown voltage.

[0058]

As described above, according to the present invention, M
By making the emitter part of the IS semiconductor device a thin film structure, it is easy to apply microfabrication, so that the cell width can be reduced and the on-voltage can be reduced, and the trade-off between on-voltage and turn-off loss can be improved. Become.

Further, by forming the first conductivity type emitter region of the emitter portion beside the second conductivity type base region, a MIS semiconductor device in which a parasitic thyristor is unlikely to latch up can be provided. Further, since the parasitic thyristor is unlikely to latch up, the impurity concentration of the second conductivity type base region can be reduced, and the leakage current when a reverse voltage is applied can be reduced.

The present invention is an important invention showing that the use of a thin-film semiconductor layer enables a dramatic improvement in performance over a conventional MIS semiconductor device fabricated on a semiconductor substrate.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an IGBT according to a first embodiment of the present invention.

FIGS. 2A to 2D are cross-sectional views of main IGBTs of Example 1 for respective main manufacturing steps;

3 (a) to 3 (d) are cross-sectional views showing main IGBT manufacturing steps of Embodiment 1 following FIG. 2 (d).

FIGS. 4A to 4C are perspective cross-sectional views illustrating a growth process by MBE.

FIG. 5 is an explanatory diagram of dimensions of each part of the IGBT according to the first embodiment of the present invention.

FIG. 6 is a sectional view of an IGBT according to a second embodiment of the present invention.

FIG. 7 is a sectional view of an IGBT according to a third embodiment of the present invention.

FIG. 8 is a sectional view of an IGBT according to a fourth embodiment of the present invention.

FIGS. 9A to 9D are cross-sectional views of main IGBTs of Example 4 for respective manufacturing steps.

FIG. 10 is a perspective sectional view of an example of a pattern by MBE.

FIG. 11 is a sectional view of an IGBT according to a fifth embodiment of the present invention.

FIG. 12 is a perspective sectional view 1 with a pressure-resistant structure added.

FIG. 13 is a perspective cross-sectional view to which a pressure-resistant structure is added, part 2

FIG. 14 is a perspective sectional view 3 with a pressure resistance structure added.

FIG. 15 is a sectional view of a conventional planar gate IGBT.

FIG. 16 is a sectional view of a conventional trench gate IGBT.

[Explanation of symbols]

1, 21, 31 ... n ^- semiconductor substrate 2, 22, 32 ... insulating film 3, 23, 33 ... gate electrode 4, 24 ... insulating film 5, 25, 35 ... gate insulation Films 6, 26, 36 ... p base region 7, 27, 37 ... n ⁺ emitter region 8, 28, 38 ... p ⁺ collector layer 9, 29, 39 ... collector electrode 10, 30, 40 ... Emitter electrode 11, 11a ... Thin film semiconductor layer 12 ... Connection semiconductor part 13 ... IGBT 14 ... Insulating film 15 ... Field plate 16 ... First trench 17 ... Second trench 26a, 36a... P ⁺ contact region 46 ... trench x3, x4 ... molecular beam x5 ... guard ring x6 ... field plate x7 ... resistive field plate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/78 653 H01L 29/78 653C (72) Inventor Manabu Takei 1 Tanabe Nitta, Kawasaki-ku, Kawasaki City, Kawasaki City, Kanagawa Prefecture No. 1 Fuji Electric Co., Ltd. (72) Inventor Katsunori Ueno 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Inside Fuji Electric Co., Ltd.

Claims (22)

[Claims] A gate electrode formed on the first conductive type semiconductor substrate via an insulating film; an insulating film covering side and top surfaces of the gate electrode; and a first electrode formed on the insulating film on the gate electrode. A conductive thin-film semiconductor layer, a connecting semiconductor portion connecting the semiconductor substrate and the first conductive thin-film semiconductor layer along the side of the gate electrode, and traversing the thin-film semiconductor layer over a portion of the thin-film semiconductor layer above the gate electrode A second conductivity type base region, a first conductivity type emitter region formed at an end of the thin film semiconductor layer remote from the connection semiconductor portion, a first conductivity type emitter region and a second conductivity type base. An MIS semiconductor device comprising: an emitter electrode provided in contact with a region; and a collector electrode formed on a back surface side of a semiconductor substrate. 2. The MIS semiconductor device according to claim 1, wherein the connecting semiconductor portion is a part of a semiconductor substrate. 3. The MIS semiconductor device according to claim 1, wherein the connecting semiconductor portion is formed of a semiconductor thin film layer. 4. The MIS semiconductor device according to claim 2, wherein a fourth electrode is provided on a surface of the thin film semiconductor layer near the connecting semiconductor portion via an insulating film. 5. The MIS semiconductor device according to claim 2, wherein the corner of the gate electrode is rounded. 6. An emitter electrode formed on a semiconductor substrate of a first conductivity type via an insulating film, an insulating film covering side surfaces of opposing emitter electrodes, and a thin film semiconductor of a first conductivity type formed on the emitter electrode. A connecting semiconductor portion connecting the semiconductor substrate and the first conductive type thin film semiconductor layer along the side of the emitter electrode and the thin film semiconductor layer from the surface of the semiconductor substrate to a part of the thin film semiconductor layer on the emitter electrode; A second conductivity type base region formed as a first conductivity type emitter region formed at an end of the thin film semiconductor layer farther from the connection semiconductor portion;
An MIS semiconductor device comprising: a gate electrode provided on a second conductivity type base region via an insulating film; and a collector electrode formed on a back surface side of the semiconductor substrate. 7. The MIS semiconductor device according to claim 6, wherein the connecting semiconductor portion is a part of a semiconductor substrate. 8. The MIS semiconductor device according to claim 6, wherein the connecting semiconductor portion comprises a semiconductor thin film layer. 9. The semiconductor device according to claim 7, wherein corners of the emitter electrode are rounded. 10. The MIS semiconductor device according to claim 1, wherein the width W of the connecting semiconductor portion is 10 μm or less. 11. The MIS semiconductor device according to claim 1, wherein the thickness t of the thin film semiconductor layer is 10 μm or less. 12. The semiconductor device according to claim 1, wherein the first conductive semiconductor substrate is a silicon substrate, and the surface is a (111) plane. 13. The semiconductor device according to claim 12, wherein the side surface of the thin film semiconductor layer is a (110) plane. 14. The semiconductor device according to claim 1, wherein the first conductive semiconductor substrate is gallium arsenide, and the surface is a (100) plane. 15. A second conductivity type base region formed on a surface layer of a first conductivity type semiconductor substrate; a first conductivity type emitter region formed on a surface layer of the second conductivity type base region; A first trench that penetrates through the second conductivity type base region and reaches the semiconductor substrate, an insulating film formed on an inner wall of the first trench, and faces the semiconductor substrate and the second conductivity type base region via the insulating film. A gate electrode, a second trench penetrating at least the first conductivity type emitter region and reaching the second conductivity type base region, and a second conductivity type base region and a first conductivity type inside the second trench. An MIS semiconductor device comprising: an emitter electrode provided in contact with an emitter region; and a collector electrode provided on a back surface side of a semiconductor substrate. 16. The distance t between the first trench and the second trench.
16. The MIS semiconductor device according to claim 15, wherein is smaller than or equal to 10 μm. 17. An impurity concentration of the second conductivity type base region is 1
0^Fifteen-10¹⁸Pieces / cm ^ThreeCharacterized by being within the range of
The MIS semiconductor device according to claim 1.
Place. 18. The MIS semiconductor device according to claim 1, further comprising a collector region of the second conductivity type on the back surface side of the semiconductor substrate. 19. A gate electrode formed on a first conductivity type semiconductor substrate via an insulating film, an insulating film covering side and top surfaces of the gate electrode, and a first electrode formed on the insulating film on the gate electrode. A conductive thin-film semiconductor layer, a connecting semiconductor portion connecting the semiconductor substrate and the first conductive thin-film semiconductor layer along the side of the gate electrode, and traversing the thin-film semiconductor layer over a portion of the thin-film semiconductor layer above the gate electrode A second conductivity type base region, a first conductivity type emitter region formed at an end of the thin film semiconductor layer remote from the connection semiconductor portion, a first conductivity type emitter region and a second conductivity type base. In a method for manufacturing a MIS semiconductor device including an emitter electrode provided in contact with a region and a collector electrode formed on a back surface side of a semiconductor substrate, a connection semiconductor portion and a thin film are formed on a first conductivity type semiconductor substrate. Etch the semiconductor layer Method of manufacturing MIS semiconductor device, and forming a Takisharu growth. 20. An emitter electrode formed on a first conductivity type semiconductor substrate via an insulating film, an insulating film covering a side surface of the emitter electrode, and a first conductivity type thin film semiconductor layer formed on the emitter electrode. A connecting semiconductor portion which connects the semiconductor substrate and the first conductive type thin film semiconductor layer along a side portion of the emitter electrode, and a connecting semiconductor portion formed on a part of the thin film semiconductor layer on the emitter electrode and formed across the thin film semiconductor layer. A two-conductivity-type base region, a first-conductivity-type emitter region formed at an end of the thin-film semiconductor layer remote from the connection semiconductor portion, and a gate electrode provided on the second-conductivity-type base region via an insulating film And a method of manufacturing a MIS semiconductor device having a collector electrode formed on the back side of the semiconductor substrate, wherein the connecting semiconductor portion and the thin film semiconductor layer are formed on the first conductivity type semiconductor substrate by epitaxial growth. Method of manufacturing MIS semiconductor device according to symptoms. 21. A gate electrode formed on a first conductivity type semiconductor substrate via an insulating film, an insulating film covering side and top surfaces of the gate electrode, and a first electrode formed on the insulating film on the gate electrode. A conductive thin-film semiconductor layer, a connecting semiconductor portion connecting the semiconductor substrate and the first conductive thin-film semiconductor layer along the side of the gate electrode, and traversing the thin-film semiconductor layer over a portion of the thin-film semiconductor layer above the gate electrode A second conductivity type base region, a first conductivity type emitter region formed at an end of the thin film semiconductor layer remote from the connection semiconductor portion, a first conductivity type emitter region and a second conductivity type base. In a method of manufacturing a MIS semiconductor device including an emitter electrode provided in contact with a region and a collector electrode formed on a back surface side of a semiconductor substrate, a thin film semiconductor layer is epitaxially grown on a first conductivity type semiconductor substrate. MI, which comprises more formed
A method for manufacturing an S semiconductor device. 22. An emitter electrode formed on a first conductivity type semiconductor substrate via an insulation film, an insulation film covering a side surface of the emitter electrode, and a first conductivity type thin film semiconductor layer formed on the emitter electrode. A connecting semiconductor portion which connects the semiconductor substrate and the first conductive type thin film semiconductor layer along a side portion of the emitter electrode; A two-conductivity-type base region, a first-conductivity-type emitter region formed at an end of the thin-film semiconductor layer remote from the connection semiconductor portion, and a gate electrode provided on the second-conductivity-type base region via an insulating film Forming a mask on the first conductivity type semiconductor substrate, performing isotropic etching, and oxidizing the MIS semiconductor device. Shape the membrane Performing a step of filling the etched recess with polysilicon, forming an oxide film on the polysilicon, and forming a thin film semiconductor layer by epitaxial growth on the surface of the first conductive type semiconductor substrate that is not etched. And a step of manufacturing the MIS semiconductor device.