JP2002353451A - Method for manufacturing super junction semiconductor element - Google Patents
Method for manufacturing super junction semiconductor elementInfo
- Publication number
- JP2002353451A JP2002353451A JP2001152686A JP2001152686A JP2002353451A JP 2002353451 A JP2002353451 A JP 2002353451A JP 2001152686 A JP2001152686 A JP 2001152686A JP 2001152686 A JP2001152686 A JP 2001152686A JP 2002353451 A JP2002353451 A JP 2002353451A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- trench
- semiconductor substrate
- growth
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000005498 polishing Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000004642 Polyimide Substances 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 4
- 230000015556 catabolic process Effects 0.000 description 8
- 239000012535 impurity Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004943 liquid phase epitaxy Methods 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Thyristors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、超接合半導体素子
の製造方法に関し、より詳細には、ＭＯＳＦＥＴ（絶縁
ゲート型電界効果トランジスタ）やＩＧＢＴ（絶縁ゲー
トバイポーラトランジスタ）、バイポーラトランジス
タ、ダイオード等に適用可能な高耐圧化と大電流容量化
を両立させることのできる超接合半導体素子の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a super junction semiconductor device, and more particularly, to a method for manufacturing a MOSFET (insulated gate field effect transistor), an IGBT (insulated gate bipolar transistor), a bipolar transistor, a diode, and the like. The present invention relates to a method for manufacturing a super-junction semiconductor element capable of achieving both a high withstand voltage and a large current capacity.
【０００２】[0002]
【従来の技術】従来の高耐圧半導体素子は、高い降伏電
圧を得るために高比抵抗のドリフト領域を主電流経路に
もうけるため、高耐圧のものほどこの部分の電圧降下が
大きくなってオン電圧が高くなるという問題があった。2. Description of the Related Art In a conventional high breakdown voltage semiconductor element, a drift region having a high specific resistance is provided in a main current path in order to obtain a high breakdown voltage. There was a problem that becomes high.
【０００３】この問題に対する解決法として、ドリフト
層を、不純物濃度を高めたｎ型とｐ型の領域とを交互に
積層した並列ｐｎ層で構成し、オフ状態のときは空乏化
して耐圧を負担するようにした構造の半導体装置が、例
えば、特公平２−５４６６１号公報、米国特許第５２１
６２７５号明細書、特開平７−７１５４号公報に開示さ
れている。As a solution to this problem, a drift layer is constituted by a parallel pn layer in which n-type and p-type regions with an increased impurity concentration are alternately stacked, and when in an off state, it is depleted to bear a breakdown voltage. A semiconductor device having such a structure is disclosed in, for example, Japanese Patent Publication No. 2-54661, U.S. Pat.
No. 6,275, and JP-A-7-7154.
【０００４】[0004]
【発明が解決しようとする課題】このような超接合構造
を形成するために、エピタキシャル成長によってトレン
チ構造を埋め込む方法や、プレーナー基板上においてエ
ピタキシャル成長とイオン打ち込みを繰り返す方法が使
われてきた。In order to form such a super junction structure, a method of filling a trench structure by epitaxial growth and a method of repeating epitaxial growth and ion implantation on a planar substrate have been used.
【０００５】しかしながら、トレンチ構造を形成してこ
のトレンチ部を埋め込む方法には、２つの問題点があっ
た。その第１の問題点は、アスペクト比の高いトレンチ
構造を形成する過程で、エッチングによるダメージが基
板に残り、このダメージを除去するために工程が増える
ほか、除去しきれないダメージが残るという問題点であ
る。However, the method of forming the trench structure and filling the trench portion has two problems. The first problem is that in the process of forming a trench structure having a high aspect ratio, damage due to etching remains on the substrate, and additional steps are required to remove the damage, and damage that cannot be removed remains. It is.
【０００６】また、第２の問題点は、従来のエピタキシ
ャル成長技術による場合、アスペクト比が１０前後であ
る極めて深いトレンチ構造を埋め込む必要があり、成長
中にトレンチの開口部がふさがってしまい、トレンチ内
部に空間が残るという問題点である。トレンチに対する
エピタキシャル成長によるこの問題を解決する指針は、
これまでに与えられていなかった。A second problem is that in the case of the conventional epitaxial growth technique, it is necessary to embed an extremely deep trench structure having an aspect ratio of about 10, and the opening of the trench is blocked during the growth, so that the inside of the trench is obstructed. The problem is that space remains in the space. The guideline to solve this problem by epitaxial growth for trench is
Had never been given before.
【０００７】また、エピタキシャル成長とイオン打ち込
みを繰り返す形成方法では、工程数が増加するため耐圧
構造部のコストが極めて高くなり、また、リソグラフィ
とイオン打ち込みの繰り返しによりプロセスダメージや
不純物汚染が増え、結晶品質を劣化するという問題点が
あった。また、この方法は、特定の位置にイオン打ち込
みした不純物を熱拡散により広げる方法であるため、超
接合領域における不純物分布が不均一であり、この不均
一性がデバイス特性を不安定にするという問題があっ
た。In the formation method in which epitaxial growth and ion implantation are repeated, the number of steps is increased, so that the cost of the breakdown voltage structure becomes extremely high. In addition, process damage and impurity contamination increase due to repetition of lithography and ion implantation, and crystal quality is reduced. There is a problem of deterioration. In addition, this method is a method in which the impurity implanted into a specific position is spread by thermal diffusion, so that the impurity distribution in the super junction region is non-uniform, and the non-uniformity makes device characteristics unstable. was there.
【０００８】これらの問題を解決するために、面間選択
性の高いエピタキシャル成長技術を導入することが望ま
しい。選択比を高める方法としては、以下の２つの方法
がある。In order to solve these problems, it is desirable to introduce an epitaxial growth technique having high inter-plane selectivity. There are the following two methods for increasing the selection ratio.
【０００９】第１は、原子線または分子線を用いたエピ
タキシー法により、分子の直進性を使って特定の面だけ
に原子線または分子線を当て、選択的に成長する方法で
ある。すなわち、トレンチ構造または凹凸構造の底部の
みに選択的に原子線または分子線を当てエピタキシャル
成長を促し、側壁には当たりにくくして側壁の成長を抑
え、エピタキシャル成長中に開口部が塞がらないように
する方法である。The first is a method in which an atomic beam or a molecular beam is applied only to a specific surface by using an epitaxy method using an atomic beam or a molecular beam, by using the rectilinearity of the molecule, and selectively grows. That is, a method in which an atomic beam or a molecular beam is selectively applied only to the bottom of a trench structure or a concavo-convex structure to promote epitaxial growth, hardly hit the side wall to suppress the growth of the side wall, and prevent the opening from being closed during the epitaxial growth. It is.
【００１０】第２は、異方性成長効果を利用するもの
で、平坦化して安定しやすく成長速度が遅い面での成長
と、荒れやすく成長速度が速い面での成長との差を利用
して選択成長を行う方法である。この異方性成長効果は
液相成長（ＬＰＥ；Liquid Phase Epitaxial）法で最も
顕著に現われるが、気相成長（ＣＶＤ；Chemical Vapor
Deposition）法でも得ることができ、原子線または分子
線を用いたエピタキシー法でもわずかに得ることができ
る。この場合、トレンチ構造または凹凸構造の側壁とし
て平坦化しやすい面を選び、底面に荒れやすい面を選
び、底面の成長速度を上げて、エピタキシャル成長中に
開口部が塞がらないようにする。The second method utilizes the anisotropic growth effect, and utilizes the difference between growth on a surface which is flattened and stable and has a low growth rate and growth on a surface which is rough and has a high growth rate. This is a method of performing selective growth. This anisotropic growth effect is most prominent in a liquid phase epitaxy (LPE) method, but is a chemical vapor deposition (CVD) method.
Deposition) method, and a slight amount can also be obtained by an epitaxy method using an atomic beam or a molecular beam. In this case, a surface that is easily flattened is selected as a sidewall of the trench structure or the uneven structure, a surface that is easily roughened is selected as a bottom surface, and the growth rate of the bottom surface is increased so that the opening is not blocked during epitaxial growth.
【００１１】しかしながら、このような解決方法にもま
だまだ改善の余地が残されているのが現状である。本発
明は、このような問題に鑑みてなされたもので、その目
的とするところは、トレンチをエピタキシャル成長によ
って埋め込む工程で、多結晶が生成しないようにし、そ
の結果、多結晶がトレンチ開口部を塞いでトレンチ内に
ボイドが残ることを防ぐようにした超接合半導体素子の
製造方法を提供することにある。However, at present, there is still room for improvement in such a solution. The present invention has been made in view of such a problem, and an object of the present invention is to prevent a polycrystal from being generated in a step of filling a trench by epitaxial growth, and as a result, the polycrystal blocks the trench opening. Accordingly, it is an object of the present invention to provide a method of manufacturing a super junction semiconductor device in which voids are prevented from remaining in a trench.
【００１２】また他の目的は、エピタキシャル成長によ
ってトレンチを十分に埋め込めなかった場合でも、耐圧
低下をまねくことのないような超接合半導体素子の製造
方法を提供することにある。Another object of the present invention is to provide a method of manufacturing a super junction semiconductor device which does not cause a decrease in breakdown voltage even when a trench cannot be sufficiently filled by epitaxial growth.
【００１３】さらに他の目的は、多結晶が生成しても成
長条件を選ぶことによりこれを最小限に抑え、ポリシン
グ工程において研磨膜厚を小さくし、研磨装置の寿命を
のばして基板にかかる機械的負荷も抑えることができる
ようにした超接合半導体素子の製造方法を提供すること
にある。Still another object of the present invention is to minimize the growth of polycrystals by selecting the growth conditions even if they are formed, to reduce the thickness of the polished film in the polishing step, to extend the life of the polishing apparatus, and to reduce the mechanical load on the substrate. It is an object of the present invention to provide a method of manufacturing a super junction semiconductor device capable of suppressing a mechanical load.
【００１４】[0014]
【課題を解決するための手段】本発明は、このような目
的を達成するために、請求項１に記載の発明は、トレン
チ構造を有する第１導電型の半導体基板に、第２導電型
のエピタキシャル層を成長させる第１の工程と、該第１
の工程により成長されたエピタキシャル層のうちトレン
チの非開口部直上に堆積した部分を、ポリシングにより
除去する第２の工程とを有することを特徴とする。In order to achieve the above object, the present invention is directed to a semiconductor device of the first conductivity type having a trench structure. A first step of growing an epitaxial layer;
And removing a portion of the epitaxial layer grown immediately above the non-opening portion of the trench, by polishing, in the epitaxial layer.
【００１５】また、請求項２に記載の発明は、請求項１
に記載の発明において、前記エピタキシャル層のポリシ
ングを少なくとも半導体基板の表面に達するまで行うこ
とを特徴とする。The invention described in claim 2 is the first invention.
The polishing of the epitaxial layer is performed at least until the epitaxial layer reaches the surface of the semiconductor substrate.
【００１６】また、請求項３に記載の発明は、トレンチ
構造を有する第１導電型の半導体基板の非開口部をマス
クする第１の工程と、該第１の工程において前記半導体
基板のマスクされていない領域に第２導電型のエピタキ
シャル層を成長させる第２の工程と、前記マスクをエッ
チングして、該マスク及びマスク上に付着した堆積物を
除去する第３の工程とを有することを特徴とする。According to a third aspect of the present invention, there is provided a first step of masking a non-opening portion of a semiconductor substrate of a first conductivity type having a trench structure, and the step of masking the semiconductor substrate in the first step. A second step of growing an epitaxial layer of a second conductivity type in a region that is not present, and a third step of etching the mask to remove the mask and deposits deposited on the mask. And
【００１７】また、請求項４に記載の発明は、請求項３
に記載の発明において、前記半導体基板の表面を少なく
ともエピタキシャル層の最上端に達するまでポリシング
する第４の工程を含むことを特徴とする。The invention described in claim 4 is the same as the invention described in claim 3.
The method according to the above aspect, further comprising a fourth step of polishing the surface of the semiconductor substrate until at least the top end of the epitaxial layer is reached.
【００１８】また、請求項５に記載の発明は、請求項１
乃至４いずれかに記載の発明において、前記トレンチ構
造の内部に成長したエピタキシャル層に生じた間隙を、
ポリイミドなどの絶縁性材料で埋め込むことを特徴とす
る。The invention described in claim 5 is the first invention.
5. The method according to any one of claims 1 to 4, wherein a gap generated in the epitaxial layer grown inside the trench structure is
It is characterized by being embedded with an insulating material such as polyimide.
【００１９】[0019]
【発明の実施の形態】以下、図面を参照して本発明の実
施例について説明する。 [第１の実施形態]図１は、本発明の第１の実施形態に係
わる超接合構造の断面図で、図２〜図７は、本発明の第
１の実施形態に係わる超接合構造の製造工程を示す断面
図である。図中符号１は、ｎ型半導体基板、２はｎ型エ
ピタキシャル層、３は酸化膜又は窒化膜などの絶縁性マ
スクである。Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a sectional view of a super junction structure according to a first embodiment of the present invention. FIGS. 2 to 7 are cross-sectional views of a super junction structure according to the first embodiment of the present invention. It is sectional drawing which shows a manufacturing process. In the figure, reference numeral 1 denotes an n-type semiconductor substrate, 2 denotes an n-type epitaxial layer, and 3 denotes an insulating mask such as an oxide film or a nitride film.
【００２０】本発明は、耐圧領域の構造と製造方法にか
かわるもので、ソース構造およびドレイン構造は任意で
ある。従って、ＩＧＢＴ（絶縁ゲート型バイポーラトラ
ンジスタ）やバイポーラトランジスタ、ＧＴＯサイリス
タ、ダイオード等にも適用される。The present invention relates to the structure of the breakdown voltage region and the manufacturing method, and the source structure and the drain structure are arbitrary. Therefore, the present invention is also applied to an IGBT (insulated gate bipolar transistor), a bipolar transistor, a GTO thyristor, a diode, and the like.
【００２１】以下、図１に示した第１の実施形態に係わ
る超接合構造の製造方法について、図２〜図７に基づい
て説明する。まず、低抵抗のｎ型半導体基板１を準備す
る。次いで、このｎ型半導体基板１の表面領域にエピタ
キシャル成長のマスクとなる酸化膜または窒化膜などの
絶縁性マスク３を形成する。次いで、図３に示すよう
に、図示しないマスクを使って、絶縁性マスク３にスト
ライプ状の窓開け部３ａを形成する。ストライプの窓開
け部３ａと絶縁性マスク３の幅は、１μｍ乃至２０μｍ
程度とする。Hereinafter, a method of manufacturing the super junction structure according to the first embodiment shown in FIG. 1 will be described with reference to FIGS. First, a low-resistance n-type semiconductor substrate 1 is prepared. Next, an insulating mask 3 such as an oxide film or a nitride film serving as a mask for epitaxial growth is formed on the surface region of the n-type semiconductor substrate 1. Next, as shown in FIG. 3, a striped window opening 3a is formed in the insulating mask 3 using a mask (not shown). The width between the window opening 3a of the stripe and the insulating mask 3 is 1 μm to 20 μm.
Degree.
【００２２】次いで、図４に示すように、窓開け部３ａ
に相当するｎ型半導体基板１をエッチングにより除去し
てトレンチ開口部１３を形成し、さらに絶縁性マスク３
をエッチングにより除去する。次いで、図５に示すよう
に、トレンチ開口部１３に、ＭＢＥ（分子線エピタキシ
ー法および原子線エピタキシー法を含み、以下、ＭＢＥ
という）、またはＣＶＤまたはＬＰＥにより、ｐ型のエ
ピタキシャル層２を結晶成長させる。このとき、トレン
チ底部の成長速度Ｖｂが、トレンチ側壁の成長速度Ｖｓ
より十分大きく、両者の速度比Ｖｂ／Ｖｓがトレンチの
アスぺクト比を上回ることが望ましい。Next, as shown in FIG.
Is removed by etching to form a trench opening 13, and furthermore, an insulating mask 3 is formed.
Is removed by etching. Next, as shown in FIG. 5, MBE (including a molecular beam epitaxy method and an atomic beam epitaxy method,
Or p-type epitaxial layer 2 is crystal-grown by CVD or LPE. At this time, the growth speed Vb of the trench bottom is equal to the growth speed Vs of the trench sidewall.
More preferably, it is desirable that the speed ratio Vb / Vs of both of them exceeds the aspect ratio of the trench.
【００２３】このような成長条件を達成するため、ＣＶ
ＤおよびＬＰＥでは異方性成長効果を利用するとよい。
すなわち、トレンチ側壁がファセットとなり、平坦で安
定な面を形成して成長速度が落ち、トレンチ底面が荒れ
た面となり成長速度が上がるように面方位を選ぶ。In order to achieve such growth conditions, CV
In D and LPE, the anisotropic growth effect may be used.
That is, the plane orientation is selected so that the trench sidewall becomes a facet, a flat and stable surface is formed, the growth rate is reduced, and the trench bottom becomes a rough surface and the growth rate is increased.
【００２４】一方、ＭＢＥでは主に分子線（原子線も含
み、以下、分子線という）の直進性を利用して、側壁の
成長速度を抑える。すなわち、指向性の揃った分子線を
ｎ型半導体基板１に対して垂直に照射し、成長反応を供
給律速条件（エピタキシャル成長の反応過程には、大き
く分けて供給律速と反応律速の２種類があり、供給律速
とは、材料（分子や原子）が結晶に初めて衝突した時、
その場で反応して結晶の一部となることである。そし
て、供給律速の特徴としては、付着率が１００％で跳ね
返りがない。材料がたくさん供給されると供給量に比例
した成長速度が速くなる。）とする。その結果、ｎ型半
導体基板１のうちトレンチ底部および非開口部では分子
線が入射するためエピタキシャル成長するが、トレンチ
側壁には分子線が入射しないのでほとんど成長しない。
その結果、速度比Ｖｂ／Ｖｓを大きくすることができ
る。分子線の指向性を揃えるためには、分子線に含まれ
る分子運動の角度のばらつきが６°以内となるのが望ま
しいので、分子線の供給ノズルを細長くし、横方向の速
度成分を持った分子を吸着したり、供給ノズルを基板か
ら遠く離すなどの方法がとられる。On the other hand, in MBE, the growth rate of the side wall is suppressed mainly by utilizing the straightness of a molecular beam (including an atomic beam, hereinafter, referred to as a molecular beam). That is, a molecular beam having uniform directivity is irradiated perpendicularly to the n-type semiconductor substrate 1 to control the growth reaction under supply-determining conditions (reaction processes of epitaxial growth are roughly classified into two types: supply-limiting and reaction-limiting. , Supply-limiting is when a material (molecule or atom) collides with a crystal for the first time,
It reacts in situ and becomes part of the crystal. As a characteristic of the supply rate control, there is no rebound at an adhesion rate of 100%. When a large amount of material is supplied, the growth rate proportional to the supplied amount is increased. ). As a result, the n-type semiconductor substrate 1 is epitaxially grown at the bottom and the non-opening of the trench because the molecular beam is incident thereon, but hardly grows because the molecular beam does not enter the sidewall of the trench.
As a result, the speed ratio Vb / Vs can be increased. In order to make the directivity of the molecular beam uniform, it is desirable that the variation of the angle of the molecular motion included in the molecular beam is within 6 °. Therefore, the supply nozzle of the molecular beam is made elongated to have a lateral velocity component. A method of adsorbing molecules or a method of moving the supply nozzle far from the substrate is used.
【００２５】図６に示すように、エピタキシャル層２が
十分厚く成長して、トレンチ底部がｎ型半導体基板１の
表面より高くなれば成長を終了する。次いで、エピタキ
シャル層２をポリシングし、その表面の高さがもとのｎ
型半導体基板１の表面と同じになるようにする。その結
果、図７に示すような超接合構造を得る。As shown in FIG. 6, when the epitaxial layer 2 grows sufficiently thick and the trench bottom becomes higher than the surface of the n-type semiconductor substrate 1, the growth is terminated. Next, the epitaxial layer 2 is polished so that the height of the surface is equal to the original n.
It should be the same as the surface of the mold semiconductor substrate 1. As a result, a super junction structure as shown in FIG. 7 is obtained.
【００２６】このように、本実施形態によれば、エピタ
キシャル層２を成長する際、絶縁性マスク３が存在しな
いので、絶縁性マスク３の上に多結晶が堆積することが
ない。多結晶が堆積すると、横方向に成長してトレンチ
の開口部を塞ぎやすい。その結果、トレンチ内に材料が
供給されなくなってエピタキシャル層２が十分成長せず
ボイドが残り、耐圧低下や素子特性のばらつきを招く。
本実施形態によれば多結晶の堆積を防ぐことができるの
で、超接合構造を安定して形成できる。As described above, according to the present embodiment, when the epitaxial layer 2 is grown, since the insulating mask 3 does not exist, no polycrystal is deposited on the insulating mask 3. When the polycrystal is deposited, it grows in the lateral direction and tends to close the opening of the trench. As a result, no material is supplied into the trench, and the epitaxial layer 2 does not grow sufficiently, leaving voids, leading to a decrease in breakdown voltage and variations in element characteristics.
According to this embodiment, since the deposition of polycrystals can be prevented, the super junction structure can be formed stably.
【００２７】[第２の実施形態]図５において、トレンチ
底面の成長速度Ｖｂが、トレンチ側壁の成長速度Ｖｓに
比べて十分大きくとれなかった場合、エピタキシャル層
２に、図８に示すような間隙４ａが残る。この場合、こ
の間隙４ａをそのまま残すと耐圧低下を招くことにな
る。そこで、この間隙４ａを、図９に示すように、ポリ
イミド４で埋め、次いで、第１の実施形態と同様にエピ
タキシャル層２およびポリイミド４をポリシングして、
図１０に示すような超接合構造を得る。図１０におい
て、残ったエピタキシャル層２とｎ型半導体基板１との
間でチャージバランスが取れていることが必要である。
このとき、耐圧構造部分は、ポリイミド４によって保護
されているので耐圧低下を起こさない。[Second Embodiment] In FIG. 5, if the growth rate Vb at the bottom of the trench cannot be made sufficiently higher than the growth rate Vs at the side wall of the trench, the epitaxial layer 2 has a gap as shown in FIG. 4a remains. In this case, if the gap 4a is left as it is, a decrease in withstand voltage will be caused. Therefore, as shown in FIG. 9, the gap 4a is filled with polyimide 4, and then the epitaxial layer 2 and the polyimide 4 are polished in the same manner as in the first embodiment.
A super junction structure as shown in FIG. 10 is obtained. In FIG. 10, it is necessary that the charge balance between the remaining epitaxial layer 2 and the n-type semiconductor substrate 1 be maintained.
At this time, since the withstand voltage structure is protected by the polyimide 4, the withstand voltage does not decrease.
【００２８】このように、本実施形態によれば、第１の
実施形態と比較して、成長速度比Ｖｂ／Ｖｓが十分大き
くとれなかった場合でも、超接合半導体素子を形成する
ことができる。As described above, according to the present embodiment, a superjunction semiconductor device can be formed even when the growth rate ratio Vb / Vs cannot be made sufficiently large as compared with the first embodiment.
【００２９】[第３の実施形態]第１の実施形態におい
て、図４に示した状態から絶縁性マスク３を除去せずに
エピタキシャル成長を開始してもよい。この場合、図１
１に示すように、絶縁性マスク３の上に多結晶５が堆積
され、この多結晶５が横にのびてトレンチ開口部１３を
塞ぎやすくする。しかし、基板温度を８００℃以上に上
げたり、ＭＢＥの場合は分子線の指向性を揃えることで
多結晶５の横方向ののびを抑えることができる。エピタ
キシャル層２の成長は、その上端部が多結晶５に接する
手前で終了する。次いで、絶縁性マスク３をエッチング
により除去する。このとき、多結晶５も同時に除去さ
れ、図１２に示すような超接合構造を得る。図１２に示
す構造は、表面にわずかに段差が生じているので、これ
をポリシングして平坦化し、図７に示すような超接合構
造を得る。Third Embodiment In the first embodiment, epitaxial growth may be started from the state shown in FIG. 4 without removing the insulating mask 3. In this case, FIG.
As shown in FIG. 1, a polycrystal 5 is deposited on the insulating mask 3, and the polycrystal 5 extends laterally to make it easier to close the trench opening 13. However, the lateral growth of the polycrystal 5 can be suppressed by increasing the substrate temperature to 800 ° C. or higher, or in the case of MBE, by adjusting the directivity of the molecular beam. The growth of epitaxial layer 2 ends before its upper end comes into contact with polycrystal 5. Next, the insulating mask 3 is removed by etching. At this time, the polycrystal 5 is also removed at the same time, and a super junction structure as shown in FIG. 12 is obtained. The structure shown in FIG. 12 has a slight step on its surface. This is polished and flattened to obtain a super junction structure as shown in FIG.
【００３０】このように本実施形態によれば、第１の実
施形態と比較してポリシングして除去する膜厚を小さく
できるという特徴がある。その結果、研磨装置の寿命を
のばし、基板にかかる機械的負荷も小さくすることがで
きる。しかし、多結晶が横方向にのびないようにするた
め、エピタキシャル層２の成長条件が制約されるという
問題がある。As described above, according to the present embodiment, there is a feature that the film thickness to be removed by polishing can be reduced as compared with the first embodiment. As a result, the life of the polishing apparatus can be extended, and the mechanical load on the substrate can be reduced. However, there is a problem that the growth conditions of the epitaxial layer 2 are restricted in order to prevent the polycrystal from extending in the horizontal direction.
【００３１】[第４の実施形態]図１３は、第１の実施形
態に係る超接合構造において、ＭＯＳＦＥＴを形成した
実施形態の断面斜視図であり、図１３（ａ）はプレーナ
構造の縦型ＭＯＳＦＥＴであり、図１３（ｂ）はトレン
チ構造の縦型ＭＯＳＦＥＴである。なお、説明を理解し
やすくするために、半導体基板に表面に形成される酸化
膜やソース電極などは省略してある。なお、第２の実施
形態を示す図１０のポリイミド４を有する構造に置きか
えることができることは容易に理解できる。[Fourth Embodiment] FIG. 13 is a sectional perspective view of an embodiment in which a MOSFET is formed in the super junction structure according to the first embodiment, and FIG. 13 (a) is a vertical type having a planar structure. FIG. 13B shows a vertical MOSFET having a trench structure. Note that an oxide film, a source electrode, and the like formed on the surface of the semiconductor substrate are omitted for easy understanding of the description. It can be easily understood that the structure having the polyimide 4 in FIG. 10 showing the second embodiment can be replaced.
【００３２】まず、図１３（ａ）について説明すると、
第１の実施形態で選られたエピタキシャル層２を有する
ｎ型半導体基板１に対し、その表面に図示しない酸化膜
とポリシリコンのゲート電極層を形成し、この酸化膜と
ゲート電極層をマスクとしてｐベース領域６とｎソース
領域７を拡散にて順次形成する。本例では、このｐベー
ス領域６が、ストライプ状になっており、エピタキシャ
ル層２のストライプ方向と直交するように形成されてい
る。このように直交されることで、ｐベース領域６が確
実にエピタキシャル層２及びｎ型半導体基板１と接する
ようになるため、位置合わせの精度を高める必要がな
く、製造が容易となる。First, referring to FIG. 13A,
An oxide film and a polysilicon gate electrode layer (not shown) are formed on the surface of the n-type semiconductor substrate 1 having the epitaxial layer 2 selected in the first embodiment, and the oxide film and the gate electrode layer are used as masks. A p base region 6 and an n source region 7 are sequentially formed by diffusion. In this example, the p base region 6 has a stripe shape and is formed to be orthogonal to the stripe direction of the epitaxial layer 2. The orthogonality ensures that the p base region 6 comes into contact with the epitaxial layer 2 and the n-type semiconductor substrate 1 without necessity, so that it is not necessary to increase the accuracy of the alignment, and the manufacturing is facilitated.
【００３３】次に、図１３（ｂ）では、第１の実施形態
で得られたエピタキシャル層２を有するｎ型半導体基板
１に対し、ｐベース領域８を形成し、続いてストライプ
状のｎ型ソース領域９を拡散やイオン注入などの方法で
形成し、その後、このｎソース領域上にエッチングによ
りトレンチ溝を形成し、そのトレンチ溝内に酸化膜１０
とポリシリコンのゲート電極１１を形成して、トレンチ
構造の縦型ＭＯＳＦＥＴを形成する。なお、この実施例
形態も図１３（ａ）と同じくｐベース領域８のストライ
プ方向とエピタキシャル層２のストライプ方向が直交し
ている。ただし、図１３（ａ），（ｂ）の実施形態にお
いて、直交でなく同じ方向としてもよい。Next, in FIG. 13B, a p-base region 8 is formed on the n-type semiconductor substrate 1 having the epitaxial layer 2 obtained in the first embodiment, and then a striped n-type region is formed. A source region 9 is formed by a method such as diffusion or ion implantation. Thereafter, a trench is formed on the n source region by etching, and an oxide film 10 is formed in the trench.
And a polysilicon gate electrode 11 to form a vertical MOSFET having a trench structure. In this embodiment, the stripe direction of the p base region 8 and the stripe direction of the epitaxial layer 2 are orthogonal to each other as in FIG. However, in the embodiments of FIGS. 13A and 13B, the directions may be the same as the directions instead of orthogonal.
【００３４】[0034]
【発明の効果】以上説明したように本発明によれば、ト
レンチ構造を有する第１導電型の半導体基板に、第２導
電型のエピタキシャル層を成長させる第１の工程と、第
１の工程により成長されたエピタキシャル層のうちトレ
ンチの非開口部直上に堆積した部分を、ポリシングによ
り除去する第２の工程とを有し、トレンチ構造の内部に
成長したエピタキシャル層に生じた間隙を、ポリイミド
などの絶縁性材料で埋め込むようにしたので、トレンチ
をエピタキシャル成長によって埋め込む工程で、多結晶
が生成しないようにし、その結果、多結晶がトレンチ開
口部を塞いでトレンチ内にボイドが残るという問題を解
決することができる。As described above, according to the present invention, a first step of growing a second conductivity type epitaxial layer on a first conductivity type semiconductor substrate having a trench structure, and a first step. A second step of removing, by polishing, a portion of the grown epitaxial layer immediately above the non-opening portion of the trench, wherein a gap generated in the epitaxial layer grown inside the trench structure is made of polyimide or the like. Since the insulating material is used to fill the trench, the process of filling the trench by epitaxial growth prevents polycrystals from being generated, thereby solving the problem that the polycrystal blocks the trench opening and voids remain in the trench. Can be.
【００３５】また、エピタキシャル成長によってトレン
チを十分に埋め込めなかった場合でも、耐圧低下をまね
くことなく超接合素子を形成することができる。Further, even when the trench cannot be sufficiently filled by the epitaxial growth, a super junction element can be formed without lowering the breakdown voltage.
【００３６】さらに、多結晶が生成しても成長条件を選
ぶことによりこれを最小限に抑えれば、ポリシング工程
において研磨膜厚を小さくし、研磨装置の寿命をのばし
て基板にかかる機械的負荷も抑えることができる。Further, even if polycrystals are formed, by minimizing the growth conditions by selecting the growth conditions, the polishing film thickness is reduced in the polishing step, the life of the polishing apparatus is extended, and the mechanical load applied to the substrate is reduced. Can also be suppressed.
【図１】本発明の第１の実施形態に係わる超接合構造の
断面図である。FIG. 1 is a cross-sectional view of a super junction structure according to a first embodiment of the present invention.
【図２】本発明の第１の実施形態に係わる超接合構造の
製造工程を示す断面図（その１）である。FIG. 2 is a cross-sectional view (part 1) illustrating a process for manufacturing the super-joined structure according to the first embodiment of the present invention.
【図３】本発明の第１の実施形態に係わる超接合構造の
製造工程を示す断面図（その２）である。FIG. 3 is a cross-sectional view (part 2) illustrating a step of manufacturing the super-joined structure according to the first embodiment of the present invention.
【図４】本発明の第１の実施形態に係わる超接合構造の
製造工程を示す断面図（その３）である。FIG. 4 is a sectional view (No. 3) showing a step of manufacturing the super-joined structure according to the first embodiment of the present invention.
【図５】本発明の第１の実施形態に係わる超接合構造の
製造工程を示す断面図（その４）である。FIG. 5 is a sectional view (No. 4) showing a step of manufacturing the super-joined structure according to the first embodiment of the present invention.
【図６】本発明の第１の実施形態に係わる超接合構造の
製造工程を示す断面図（その５）である。FIG. 6 is a cross-sectional view (No. 5) showing a step of manufacturing the super-joined structure according to the first embodiment of the present invention.
【図７】本発明の第１の実施形態に係わる超接合構造の
製造工程を示す断面図（その６）である。FIG. 7 is a sectional view (part 6) illustrating a step of manufacturing the super-joined structure according to the first embodiment of the present invention.
【図８】本発明の第２の実施形態に係わる超接合構造の
製造工程を示す断面図（その１）である。FIG. 8 is a cross-sectional view (part 1) illustrating a process for manufacturing the super-joined structure according to the second embodiment of the present invention.
【図９】本発明の第２の実施形態に係わる超接合構造の
製造工程を示す断面図（その２）である。FIG. 9 is a cross-sectional view (2) illustrating a step of manufacturing the super-joined structure according to the second embodiment of the present invention.
【図１０】本発明の第２の実施形態に係わる超接合構造
の製造工程を示す断面図（その３）である。FIG. 10 is a sectional view (part 3) illustrating a process for manufacturing the super-joined structure according to the second embodiment of the present invention;
【図１１】本発明の第３の実施形態に係わる超接合構造
の製造工程を示す断面図（その１）である。FIG. 11 is a cross-sectional view (part 1) illustrating a process for manufacturing the super-joined structure according to the third embodiment of the present invention.
【図１２】本発明の第３の実施形態に係わる超接合構造
の製造工程を示す断面図（その２）である。FIG. 12 is a cross-sectional view (2) illustrating a step of manufacturing the super-joined structure according to the third embodiment of the present invention.
【図１３】第１の実施形態に係る超接合構造において、
ＭＯＳＦＥＴを形成した実施形態の断面斜視図で、
（ａ）はプレーナ構造の縦型ＭＯＳＦＥＴ、（ｂ）はト
レンチ構造の縦型ＭＯＳＦＥＴである。FIG. 13 shows a super junction structure according to the first embodiment.
FIG. 2 is a cross-sectional perspective view of an embodiment in which a MOSFET is formed,
(A) is a vertical MOSFET having a planar structure, and (b) is a vertical MOSFET having a trench structure.
１ ｎ型半導体基板 ２ ｎ型エピタキシャル層 ３ 酸化膜又は窒化膜などの絶縁性マスク ３ａ 窓開け部 ４ ポリイミド ４ａ 間隙 ５ 多結晶 ６ ｐベース領域 ７ ｎシース領域 ８ ｐベース領域 ９ ｎシース領域 １０ 酸化膜 １１ ゲート電極 １３ トレンチ開口部 Reference Signs List 1 n-type semiconductor substrate 2 n-type epitaxial layer 3 insulating mask such as oxide film or nitride film 3 a window opening 4 polyimide 4 a gap 5 polycrystal 6 p base region 7 n sheath region 8 p base region 9 n sheath region 10 oxidation Film 11 gate electrode 13 trench opening
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/74 Ｈ０１Ｌ 29/74 Ｑ Ｆターム(参考） 5F005 AH02 AH03 5F103 AA04 BB13 GG01 HH03 JJ01 NN01 PP07 PP08 RR05 RR08──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI theme coat ゛ (Reference) H01L 29/74 H01L 29/74 Q F term (Reference) 5F005 AH02 AH03 5F103 AA04 BB13 GG01 HH03 JJ01 NN01 PP07 PP08 RR05 RR08
Claims (5)
体基板に、第２導電型のエピタキシャル層を成長させる
第１の工程と、該第１の工程により成長されたエピタキ
シャル層のうちトレンチの非開口部直上に堆積した部分
を、ポリシングにより除去する第２の工程とを有するこ
とを特徴とする超接合半導体素子の製造方法。A first step of growing a second conductivity type epitaxial layer on a first conductivity type semiconductor substrate having a trench structure; A second step of removing, by polishing, a portion deposited immediately above the opening, the method comprising the steps of:
なくとも半導体基板の表面に達するまで行うことを特徴
とする請求項１に記載の超接合半導体素子の製造方法。2. The method according to claim 1, wherein the polishing of the epitaxial layer is performed at least until the epitaxial layer reaches the surface of the semiconductor substrate.
体基板の非開口部をマスクする第１の工程と、該第１の
工程において前記半導体基板のマスクされていない領域
に第２導電型のエピタキシャル層を成長させる第２の工
程と、前記マスクをエッチングして、該マスク及びマス
ク上に付着した堆積物を除去する第３の工程とを有する
ことを特徴とする超接合半導体素子の製造方法。3. A first step of masking a non-opening portion of a semiconductor substrate of a first conductivity type having a trench structure, and a step of masking a second conductivity type on an unmasked region of the semiconductor substrate in the first step. A method of manufacturing a super junction semiconductor device, comprising: a second step of growing an epitaxial layer; and a third step of etching the mask to remove the mask and deposits deposited on the mask. .
タキシャル層の最上端に達するまでポリシングする第４
の工程を含むことを特徴とする請求項３に記載の超接合
半導体素子の製造方法。4. A fourth step of polishing the surface of the semiconductor substrate at least until reaching the top end of the epitaxial layer.
4. The method according to claim 3, further comprising the step of:
タキシャル層に生じた間隙を、ポリイミドなどの絶縁性
材料で埋め込むことを特徴とする請求項１乃至４のいず
れかに記載の超接合半導体素子の製造方法。5. The super-junction semiconductor device according to claim 1, wherein a gap generated in the epitaxial layer grown inside the trench structure is filled with an insulating material such as polyimide. Production method.
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| JP2001152686A JP2002353451A (en) | 2001-05-22 | 2001-05-22 | Method for manufacturing super junction semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001152686A JP2002353451A (en) | 2001-05-22 | 2001-05-22 | Method for manufacturing super junction semiconductor element |
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Family
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004114384A1 (en) * | 2003-06-17 | 2004-12-29 | Shin-Etsu Handotai Co.,Ltd. | Silicon epitaxial wafer manufacturing method and silicon epitaxial wafer |
| JP2007173734A (en) * | 2005-12-26 | 2007-07-05 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| US7601603B2 (en) | 2004-03-31 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device |
| JP2010525605A (en) * | 2007-04-23 | 2010-07-22 | アイスモス・テクノロジー・リミテッド | Method for manufacturing trench-type semiconductor device with thermally sensitive refill material |
| CN102184861A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Trench filling method and trench structure of cold MOS (metal oxide semiconductor) |
| CN102184860A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Cold MOS (Metal Oxide Semiconductor) groove padding method and cold MOS groove structure |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0453142A (en) * | 1990-06-18 | 1992-02-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH04198089A (en) * | 1990-11-28 | 1992-07-17 | Toshiba Corp | Molecular beam source |
| JPH07113169A (en) * | 1993-10-13 | 1995-05-02 | Mitsubishi Electric Corp | Device for forming thin film |
| JP2000340578A (en) * | 1999-05-28 | 2000-12-08 | Hitachi Ltd | Manufacture of semiconductor device |
| JP2001087996A (en) * | 1999-09-22 | 2001-04-03 | Shin Etsu Handotai Co Ltd | Method and device for specularly chamfering periphery of semiconductor wafer |
| DE10053463A1 (en) * | 1999-10-28 | 2001-05-03 | Denso Corp | Semiconductor substrate comprises substrate component of one conductivity type with channels which taper from top to bottom and are deeper than their width and which are filled with semiconductor of opposite type to first component |
| JP2001127289A (en) * | 1999-10-28 | 2001-05-11 | Denso Corp | Semiconductor device and manufacturing method thereof |
-
2001
- 2001-05-22 JP JP2001152686A patent/JP2002353451A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0453142A (en) * | 1990-06-18 | 1992-02-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH04198089A (en) * | 1990-11-28 | 1992-07-17 | Toshiba Corp | Molecular beam source |
| JPH07113169A (en) * | 1993-10-13 | 1995-05-02 | Mitsubishi Electric Corp | Device for forming thin film |
| JP2000340578A (en) * | 1999-05-28 | 2000-12-08 | Hitachi Ltd | Manufacture of semiconductor device |
| JP2001087996A (en) * | 1999-09-22 | 2001-04-03 | Shin Etsu Handotai Co Ltd | Method and device for specularly chamfering periphery of semiconductor wafer |
| DE10053463A1 (en) * | 1999-10-28 | 2001-05-03 | Denso Corp | Semiconductor substrate comprises substrate component of one conductivity type with channels which taper from top to bottom and are deeper than their width and which are filled with semiconductor of opposite type to first component |
| JP2001127289A (en) * | 1999-10-28 | 2001-05-11 | Denso Corp | Semiconductor device and manufacturing method thereof |
| JP2001196573A (en) * | 1999-10-28 | 2001-07-19 | Denso Corp | Semiconductor substrate and manufacturing method therefor |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004114384A1 (en) * | 2003-06-17 | 2004-12-29 | Shin-Etsu Handotai Co.,Ltd. | Silicon epitaxial wafer manufacturing method and silicon epitaxial wafer |
| CN100428411C (en) * | 2003-06-17 | 2008-10-22 | 信越半导体株式会社 | Silicon epitaxial wafer manufacturing method and silicon epitaxial wafer |
| US7601603B2 (en) | 2004-03-31 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device |
| USRE44236E1 (en) | 2004-03-31 | 2013-05-21 | Denso Corporation | Method for manufacturing semiconductor device |
| JP2007173734A (en) * | 2005-12-26 | 2007-07-05 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| JP2010525605A (en) * | 2007-04-23 | 2010-07-22 | アイスモス・テクノロジー・リミテッド | Method for manufacturing trench-type semiconductor device with thermally sensitive refill material |
| CN102184861A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Trench filling method and trench structure of cold MOS (metal oxide semiconductor) |
| CN102184860A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Cold MOS (Metal Oxide Semiconductor) groove padding method and cold MOS groove structure |
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