KR101190007B1 - Semiconductor device and super junction structure forming method thereof - Google Patents

Abstract

Disclosed are a semiconductor device and a method of forming a superjunction structure thereof. A method of forming a superjunction structure of a semiconductor device includes: growing a first epitaxial layer of a first conductivity type on an upper portion of a first conductivity type substrate; Implanting first conductivity type ions entirely on top of the grown first epitaxial layer without masking; Defining a region where a second conductivity type region is to be formed through a mask operation, and etching silicon to remove all or a portion of the first conductivity type ions implanted in the defined region; And growing a second epitaxial layer on top of the first epitaxial layer after implanting the second conductivity type ions into the defined region. According to the present invention, the device fabrication cost can be reduced, the concentration of the N conductive filler can be increased to an appropriate level, and the problem of alignment between epi layers can be solved fundamentally.

Description

Semiconductor device and super junction structure forming method

The present invention relates to a semiconductor device and a method of forming the superjunction structure thereof.

Semiconductor devices are an important element in power electronics, which are developed to meet the needs of a wide range of industries, including automotive applications as well as high isolation voltages, low conduction losses, switching speeds, and low switching losses. It is becoming. For example, semiconductor devices including insulated gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field effect transistors (power MOSFETs), and various types of thyristors continue to develop in response to such demands.

The on-resistance of the power semiconductor device is highly dependent on the electrical resistance of the drift layer portion, but the impurity concentration that determines the electrical resistance of the drift layer is the breakdown voltage of the PN junction formed by the base and the drift layer. Since it can not be applied beyond the limit according to the trade-off relationship between the breakdown voltage and the on-resistance of the semiconductor device is established. This trade-off relationship has a limitation determined by the material of the semiconductor device, and thus, the manufacture of a semiconductor device having a low on resistance is required by overcoming this limitation.

As an example of the structure of a semiconductor device for power to solve this problem, a super junction structure in which a P conductive filler and an N conductive filler is embedded is proposed.

FIG. 1 illustrates a MOSFET having a horizontal gate according to the prior art, and FIG. 2 illustrates a MOSFET having a superjunction structure according to the prior art.

Unlike the MOSFET having the horizontal gate shown in FIG. 1, the MOSFET having the superjunction structure shown in FIG. 2 has a P region (ie, P-conductive filler) 210 in the same direction as the current flow direction in the drift region. With this present, the PN junction between the P conductive filler 210 and the N conductive filler 220 is formed in the vertical direction. For reference, in FIGS. 1 and 2, reference numeral 10 denotes an N + conductive substrate, 30 denotes an N drift layer, 35 denotes a P conductive base region, 40 denotes an N + conductive source region, and 50 denotes a gate electrode. 55 denotes a gate insulating layer, 70 denotes a source metal electrode, and 80 denotes a drain metal electrode.

When the superjunction structure is applied as shown in FIG. 2, when a reverse voltage is applied, a depletion region that extends in parallel along the PN junction surface repeated at a narrow interval (L _{pillar in} FIG. 2) meets each other even at a low reverse bias. Since the drift region is completely converted to the depletion layer, the electric field concentration at the PN junction can be reduced.

Therefore, if the amount of charge in the P-conducting and N-conducting regions in the drift region is controlled so that the drift region can be completely converted into a depletion layer, a high breakdown voltage may be secured even if a relatively high N drift concentration is applied as compared to a general MOSFET. This allows the design of a semiconductor device having a low forward resistance at the same breakdown voltage and improved forward characteristics.

In addition, assuming that the N-conducting region and the P-conducting region of the N drift region are completely switched to the depletion region, the on-resistance of the MOSFET having the superjunction structure is linear with the breakdown voltage and the cell pitch. As a result, the cell pitch can be reduced while maintaining the breakdown voltage to improve the forward device characteristics.

That is, if the cell pitch is reduced, the distance between each PN junction is reduced, and thus the length of the depletion region meets can be increased, so that the concentration of the N drift region can be increased, so that the resistance of the N drift region can be reduced, and the degree of integration increases. Since the effect can be obtained, the resistance of the chip can be effectively reduced.

As such, the superjunction structure for reducing the on resistance of the semiconductor device and improving the forward device characteristics can be formed by various methods.

However, the conventional method of forming a superjunction structure has a problem of increasing the device fabrication cost due to the increase in the number of epitaxial growth processes and the increase of the mask operation, and it is also difficult to increase the concentration of the N-conductive filler.

Therefore, there is a need for a method of forming a superjunction structure capable of reducing device fabrication cost and increasing the concentration of N-conductive filler to an appropriate level.

The above-described background technology is technical information that the inventor holds for the derivation of the present invention or acquired in the process of deriving the present invention, and can not necessarily be a known technology disclosed to the general public prior to the filing of the present invention.

The present invention is to provide a semiconductor device and a method of forming a superjunction structure which can reduce the device manufacturing cost, increase the concentration of the N-conductive filler to an appropriate level, and can fundamentally solve the alignment problem between the epi layers.

Other objects of the present invention will be readily understood through the following description.

According to an aspect of the present invention, there is provided a method of forming a superjunction structure of a semiconductor device, the method comprising: (a) growing a first epitaxial layer of a first conductivity type on top of a first conductivity type substrate; (b) implanting first conductivity type ions entirely on top of the grown first epitaxial layer without masking; (c) defining a region where a second conductivity type region is to be formed through a mask operation, and etching the silicon to remove all or a portion of the first conductivity type ions implanted in the defined region; And (d) implanting a second conductivity type ion into the defined region, and then growing a second epitaxial layer on top of the first epitaxial layer.

By repeatedly performing the steps (b) to (d), it is possible to form a super junction structure in which the PN junction is longitudinally formed.

Steps (c) may be formed between the first conductivity type region and the second conductivity type region in the horizontal direction by silicon etching according to the step (c).

By the silicon etching of step (c), a discontinuous section may be generated in the ion concentration distribution between the first conductivity type region and the second conductivity type region in the horizontal direction.

An alignment key may be formed together in the silicon etching process of step (c) to allow the defined region to continue in the longitudinal direction even after the growth of the new epitaxial layer.

The step (b) may further include forming an oxide film on the first epitaxial layer, and the step (d) may further include removing the formed oxide film.

The ion concentration of the first epitaxial layer and the second epitaxial layer may not be uniform.

The second conductivity type ions implanted in the step (d) may diffuse to form a second conductivity type region when the second epitaxial layer is grown.

The first conductivity type may be any one of P type and N type, and the second conductivity type may be another one of P type and N type.

The semiconductor device may be at least one of a power MOSFET and an IGBT.

Other aspects, features, and advantages will become apparent from the following drawings, claims, and detailed description of the invention.

According to the embodiment of the present invention, it is possible to reduce the device manufacturing cost, increase the concentration of the N conductivity type filler to an appropriate level, and fundamentally solve the alignment problem between the epi layers.

1 is a view showing the structure of a MOSFET (Metal Oxide Semiconductor Field Transistor) having a horizontal gate according to the prior art.
2 is a view showing the structure of a MOSFET having a superjunction structure according to the prior art.
3 and 4 illustrate a process of forming a superjunction structure of a semiconductor device according to the prior art, respectively.
5 is a view illustrating a process of forming a superjunction structure of a semiconductor device in accordance with an embodiment of the present invention.
6 illustrates a form of an alignment key according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Where an element such as a layer, region or substrate is described as being "on" or "onto" another element, the element may be directly on top of another element or may extend directly over it , Or an intervening element may exist. On the other hand, if one element is referred to as being "directly on" another element or "directly onto" another element, there are no other intermediate elements. Also, when an element is described as being "connected" or "coupled" to another element, the element may be directly connected to or directly coupled to another element, or an intermediate intervening element may be present have. On the other hand, if one element is described as being "directly connected" or "directly coupled" to another element, there are no other intermediate elements.

The terms "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" Relative terms such as " vertical "may be used herein to describe a relationship to another element, layer or region of an element, layer or region, as shown in the figures. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 and 4 are views illustrating a process of forming a superjunction structure of a semiconductor device according to the prior art, respectively.

Referring to FIG. 3, which shows an example of a process of forming a superjunction structure according to the related art, in step (a), an N conductive epitaxial layer 30 is grown on an N + conductive substrate 10, and step (b). ), P-conductive ions are implanted into the region where the P-conductive filler 210 is to be formed.

Subsequently, the process proceeds to step (c) to form a new epitaxial layer on top of the epitaxial layer into which the P conductivity type ions are implanted. In the process of forming a new epitaxial layer, the P conductive ions implanted in step (b) are diffused by a high temperature to form a circular P conductive region.

As such, by repeatedly performing the process of the first epitaxial layer growth, the P conductivity type ion implantation, and the second epitaxial layer growth on top of the first epitaxial layer, as shown by the identification number 320, the longitudinal P conductive filler 210 is formed. ), Ie a longitudinal PN junction can be formed.

As described above, since the P-conductive ions implanted by the thermal process such as epilayer growth are diffused, the interface between the P-conductive region and the N-conductive region is formed in a C-shape in a vertical direction. do. The boundary surface formed to be bent as described above is a section in which the concentrations of the N conductive region and the P conductive region change, which may cause difficulty in balancing charges and may hinder the flow of current.

Accordingly, a method of minimizing the width of the P-conductive region into which the P-conductive ion is diffused by reducing the _pillar pitch (L _pillar of FIG. 2) is required. The most common way to reduce the filler pitch is to increase the number of epitaxial growths (i.e., increase the number of epilayer growth and ion implantation), and thus the degree of bending between the P conductive fillers 210 and the N conductive fillers 220. There is a way to reduce it. However, this method of reducing the filler pitch has a problem in that the cost is increased by increasing the number of epitaxial growth processes and the number of mask operations.

In addition, a method of implanting N-conducting ions and P-conducting ions into each region and canceling the ions at the boundary thereof to minimize the horizontal diffusion of the ions can be applied. Compared with the conventional method, a problem arises in that the manufacturing cost of the semiconductor device increases.

Referring to FIG. 4, which shows another example of a process of forming a superjunction structure according to the related art, in step (a), an N conductive epitaxial layer 30 is grown on an N + conductive substrate 10, and step (b). ) Implants N-conductive ions into the epitaxial layer 30 grown without a mask operation. That is, after the epi layer 30 is grown, N-conductive ions are implanted as a whole without masking before implantation of the P-conductive ions to be described later.

In step (c), a photoresist 430 is coated on the epitaxial layer 30, and a pattern through a mask operation is formed for the P conductivity type ion implantation.

In step (d), the P resistive ions are implanted into the area exposed through the mask operation, that is, the area where the P conductive filler is to be formed, and the photoresist 430 remaining on the epi layer 30 in the step (e). After removing, a new epitaxial layer is formed on top of the epitaxial layer into which the P conductivity type ion is implanted in step (f).

In the process of forming a new epitaxial layer, the P-conductive ions implanted in step (d) are diffused by a high temperature to form circular P-conductive regions, and by repeating steps (b) to (f), P-conductive filler 210 in the direction is formed.

The N-conductive ions implanted entirely in step (b) are offset by the P-conducting ions partially implanted in step (d) to inhibit the horizontal diffusion of the P-conducting ions.

The method of forming the P-conductive filler 210 using an offset effect between each ion by implanting P-conductive ions to the region where the P-conductive filler 210 is to be formed is limited. The P-conductive region is formed, and the degree of bending in the vertical direction is relatively small, thereby reducing the filler pitch.

However, in this method, since N-conductive ions are also implanted in the P-conductive region, offsets are generated between the ions even in the P-conductive region, so that it is not easy to balance the charge, thus increasing the concentration of the N-conductive region. It causes problems

FIG. 5 is a view illustrating a process of forming a superjunction structure of a semiconductor device according to an embodiment of the present invention, and FIG. 6 is a view illustrating a form of forming an alignment key according to an embodiment of the present invention.

Referring to FIG. 5, which shows a process for forming a superjunction structure according to an embodiment of the present invention, in step (a), an N conductive epitaxial layer 30 is grown on an N + conductive substrate 10. N conductive ions are implanted into the epitaxial layer 30 grown in step (b) without masking. That is, after the epi layer 30 is grown, N-conductive ions are implanted as a whole without masking before implantation of the P-conductive ions to be described later. Although not shown in step (b), a step of forming an oxide (oxide) on the grown epitaxial layer 30 may be further included.

In step (c), a photoresist 430 is coated on the epitaxial layer 30, and pattern formation and silicon etching are performed through a mask operation for P-conductive ion implantation.

At this time, the epi layer 30 to an appropriate depth so that some or all of the N conductive ions implanted in the region where the P conductive filler is to be formed (that is, the N conductive ions implanted by step (b)) can be removed. The upper part of is also etched together. As a result, in the superjunction structure, the distribution of one impurity (implanted ion) concentration in the horizontal direction is essentially discontinuous, and the distribution of the impurity concentration in the horizontal direction is discontinuous in the P-conductive region and the N-conductive region. A step is formed between the surfaces of the.

In step (d), P-conductive ions are implanted into the silicon-etched region (that is, the region where the P-conductive filler is to be formed) through a mask operation. Since some or all of the N-conductive ions implanted in the region where the P-conductive region is to be formed are removed, and then P-conductive ions are implanted, the offset effect between the two ions may not occur or be minimized in the P-conductive region. It is easy to balance the charge between the conductive ions and the N conductive ions.

Subsequently, after removing the photoresist 430 remaining on the epitaxial layer 30 in step (e), a new epitaxial layer is formed on top of the epitaxial layer into which P conductivity type ions are implanted in step (f).

In the process of forming a new epitaxial layer, the P-conductive ions implanted in step (d) are diffused by a high temperature to form a circular P-conductive region, and by repeating this process, the longitudinal P-conductive filler 210 is formed. Is formed.

In addition, since the compensation between the P-conducting ions and the N-conducting ions occurs only at the boundary between the P-conducting region and the N-conducting region, diffusion in the horizontal direction with respect to the P-conducting region can be effectively suppressed. Thus, a small filler pitch can be realized. In addition, it is easy to balance charges according to the decrease of filler pitch, and the offset effect between two ions implanted in the same region is minimized, so that it is possible to inject a high concentration of N-conductive ions, and as a result, the forward characteristic of the semiconductor device is improved. Can be improved.

In the method of forming a superjunction structure using the multilayer epitaxial growth method as described above, since the vertical junction between the P conductive region and the N conductive region is performed by repeating the epitaxial growth process, the photolithographic process, and the ion implantation process, Alignment between P conductive regions in the epi layer is important.

In general, the alignment between each epi layer is based on a trench key formed prior to epi growth. However, in the epitaxial growth process where silicon is grown isotropically, the trench key is filled with epitaxial growth, resulting in unclear steps between the trench interior and exterior. As the epitaxial layer grows thicker, the alignment between the layers becomes more difficult. There was a problem.

In order to solve this problem, a method of adding a separate key forming process is used to maintain the trench key step so that alignment between the P conductive regions is possible.

However, as shown in FIG. 6, the structure of the semiconductor device according to the present exemplary embodiment may be classified into a alignment key (see FIG. Since the trenches that align keys are also etched at the same time, there is an advantage that the trench key step is always maintained.

That is, in the method for forming a superjunction structure according to the present embodiment, the trench key may be defined at the same time every time in the silicon etching process for removing the N conductivity type ions, thereby fundamentally solving the problem of alignment of the P conductivity type regions between the epitaxial layers. There is a vertex that can be.

In addition, in the P-conductive region and the N-conductive region according to the superjunction structure forming method according to the present embodiment, the concentration of each conductive carrier may not be uniform in the vertical direction. For example, the N-conductive ion concentration of the epitaxial layer grown in each epitaxial growth step may be changed, or the N-conductive ion concentration injected through step (b) may be different.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims And changes may be made without departing from the spirit and scope of the invention.

10: N + conductive substrate
30: N drift layer
35: P conductive base area
40: source area
50: gate electrode
55 gate insulating layer
70: source metal electrode
80: drain metal electrode
210: P conductive filler
220: N conductive filler

Claims (8)

In the method of forming a superjunction structure of a semiconductor device,
(a) growing a first epitaxial layer of a first conductivity type on top of the first conductivity type substrate;
(b) implanting first conductivity type ions entirely on top of the grown first epitaxial layer without masking;
(c) defining a region where a second conductivity type region is to be formed through a mask operation, and etching the silicon to remove all or a portion of the first conductivity type ions implanted in the defined region; And
(d) implanting a second conductivity type ion into the defined region, and then growing a second epitaxial layer on top of the first epitaxial layer.
The method of claim 1,
And repeating steps (b) to (d) to form a super junction structure in which PN junctions are longitudinally formed.
The method of claim 1,
And a step is formed between the first conductivity type region and the second conductivity type region in the horizontal direction by silicon etching according to the step (c).
The method of claim 1,
And a discontinuous section is generated in the ion concentration distribution between the first conductivity type region and the second conductivity type region in the horizontal direction by silicon etching according to the step (c).
The method of claim 1,
And a align key is formed together in the silicon etching process of step (c) to allow the defined region to continue in the longitudinal direction even after the growth of the new epitaxial layer.
The method of claim 1,
Wherein the first conductivity type is any one of P type and N type, and the second conductivity type is another one of P type and N type.
The method of claim 1,
And the semiconductor device is at least one of a power MOSFET and an IGBT.
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