JP2001127289A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with new constitution and the manufacturing method. SOLUTION: In an N-type silicon substrate 1, trenches 5 where the concentration of at least side walls becomes low are formed and the trenches 5 are filled with a P-type epitaxial film 14. A silicon substrate 15 where the specified layer 17 of atoms is buried by prescribed depth and the silicon substrate 1 where the trenches 5 are formed are stuck by direct junction, and they are peeled in the atom buried layer 17 of the silicon substrate 15 by heat-treating them. Then, a thin N-type silicon layer 18 is arranged on the substrate 1 where the trenches 5 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A semiconductor device called a power device can be used for driving a large current with a high withstand voltage, and is used for vehicles such as automobiles and industrial equipment. At present, the operation principle of the power device, which has become mainstream, is MOS gate control, and MOSFETs and IGBTs are mainstream in most application fields. However, the MOSFET has a problem that its on-resistance is large especially in a region of high withstand voltage specification of several hundred volts or more. This is MOSF
This is because the on-resistance of the ET is mainly determined by the high-resistance drift region, and generally, there is a trade-off relationship between the high breakdown voltage and the on-resistance. Therefore, IGBTs are often used for high withstand voltage applications. However, since IGBTs are bipolar devices, there is a problem that the switching speed is slower in principle than MOSFETs which are unipolar devices. In each case, its performance is approaching the theoretical limits of the device structure, and new device concepts are expected.

In such a situation, Japanese Patent Laid-Open No. 7-71
There is a power MOSFET disclosed in Japanese Patent Publication No. 54-54. FIG. 20 shows a schematic sectional view thereof. A semiconductor layer 101 is formed on a low resistance N ⁺ substrate 100, and the semiconductor layer 1
In FIG. 01, a P-type region (body P region) 102 and an N-type region (drift N region) 103 sandwiched therebetween are arranged, and a high-concentration P region (channel P region) 104 is provided above the body P region 102. Is formed, and a high concentration N
A region (source N region) 105 is arranged.

A gate oxide film 106 is formed on the semiconductor layer 101.
, A gate electrode 107 is arranged. In addition, the source electrode 108 contacts the source N region 105 and the channel P region 104, and the N ⁺
On the back surface of the substrate 100, a drain electrode (not shown) is arranged.

The depth and width of the drift N region 103 are
It is appropriately designed according to the specifications of the device, and the depth is generally 45 μm for a withstand voltage specification of, for example, 600 volts.
m or more, and the width is generally 5 μm or less in order to obtain an on-resistance of, for example, 1 Ωmm ² . This device structure is based on Siemens.
s) announced by the company, Cool MOS
(Cool MOS).

The operation principle of the cool MOS will be briefly described. In the ON state, electrons are supplied to the source N region 105.
Pass through the vicinity of the surface of channel P region 104 and are introduced into drift N region 103. Thereafter, the electrons move vertically downward by the drain voltage applied to the back substrate. In order to reduce the on-resistance at this time, it is necessary to reduce the resistance of the drift N region 103, that is, it is desirable that the drift N region 103 has a high impurity concentration.

In the off state, drift N region 10
3 and the entire body P region 102 interposed therebetween, that is, the vicinity of the surface of the device is depleted over the entire surface of the device, and the voltage applied by the depletion layer is averagely dispersed, whereby a local electric field is generated. Prevents concentration and secures pressure resistance. Thus, both the N and P regions 102, 1
The impurity densities and the widths of both regions 102 and 103 are appropriately designed so that 03 is uniformly depleted. here,
As described above, in order to reduce the on-resistance, it is desirable that the drift N region 103 has a high concentration. On the other hand, in the high concentration region, a depletion layer is difficult to be formed, so that the drift N region 103 is completely depleted. Therefore, it is desirable that the width of the region 103 is small.

[0008] As described above, the cool MOS is an excellent element capable of exhibiting performance exceeding the conventional theoretical limit, and its manufacturing method is described in G. Deboy et al.
newgeneration of high voltage MOSFETs breaks the l
In the "imit line of silicon" IEDM98 Proc. (1998), several epi and photolithography, ion implantation,
It is reported to spread repeatedly.

However, as described above, the cool MOS
The method of manufacturing (a vertical transistor having a high-concentration diffusion region 103 that is deep and narrow within the substrate and allows current to flow from the surface of the substrate toward the back surface) poses a major problem in terms of manufacturing cost. For example, consider a case where a drift N region 103 having a depth of 45 μm and a width of 5 μm is formed by epi growth. As described above, when the epitaxial growth and ion implantation are formed based on the repetition of the diffusion process, in the diffusion process, the diffusion length in the vertical direction and the diffusion length in the horizontal direction are the same. It must be equal to or less than the width of the drift layer. Therefore, under the above conditions, a total of at least nine photo steps (= depth / width = 45/5) are required. In contrast to the substrate process so far, in the subsequent device processes, the photo process includes gate electrode etching, P ⁺ ion implantation, N ⁺ ion implantation, contact etching, wiring etching, and protection film etching (for pad exposure). Six times in total. That is, only the substrate manufacturing process accounts for more than half of the total number of processes.

[0010]

SUMMARY OF THE INVENTION The present invention has been made under the above-mentioned background, and an object of the present invention is to provide a semiconductor device having a novel structure and a method of manufacturing the same.

[0011]

According to a third aspect of the present invention, a trench is formed in a semiconductor substrate of a first conductivity type in which at least a sidewall has a low concentration. Then, the inside of the trench is filled with a semiconductor material of the second conductivity type. Furthermore, the semiconductor substrate for bonding of the first conductivity type in which a layer of a specific atom is buried at a predetermined depth, and the semiconductor substrate on which the trench is formed are bonded by direct bonding.
Next, by heat treatment, the thin semiconductor layer of the first conductivity type is separated on the semiconductor substrate on which the trench is formed by peeling off at the atomic buried layer of the bonding semiconductor substrate.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the two substrates to be bonded have different plane orientations. This is preferable as a method for obtaining the semiconductor device according to the first aspect.

That is, the diffusion region of the second conductivity type formed on the semiconductor support substrate of the first conductivity type extends in the depth direction from the substrate surface, and has a width larger than a laterally extending dimension in an arbitrary plane parallel to the substrate surface. Also, the spreading dimension in the normal direction of the substrate surface is larger. The first conductivity type semiconductor layer formed on the semiconductor support substrate has a different plane orientation from the semiconductor support substrate. In particular, as described in claim 2, in the semiconductor device according to claim 1, the plane orientation of the semiconductor support substrate is (11).
0) and the plane orientation of the semiconductor layer is preferably (100).

According to the method of manufacturing a semiconductor device of the fifth aspect, the trench is formed in the semiconductor substrate of the first conductivity type. Then, by performing the heat treatment in the gas phase containing the second conductivity type impurity, the impurity is diffused from the opening of the trench into the semiconductor substrate, and the impurity concentration on the inner wall of the trench is effectively reduced. Further, the inside of the trench is filled with a semiconductor material of the second conductivity type, and a thin semiconductor layer of the first conductivity type is disposed on the semiconductor substrate. Here, if the semiconductor substrate and the semiconductor layer of the first conductivity type have different plane orientations as described in claim 6, it is preferable as a method for obtaining the semiconductor device according to claim 1. .

According to the method of manufacturing a semiconductor device of the present invention, a trench having a low concentration at least in the side wall is formed in the semiconductor substrate of the first conductivity type. Then, the inside of the trench is filled with a semiconductor material of the second conductivity type. Further, the first conductivity type bulk single crystal semiconductor substrate and the semiconductor substrate in which the trench is formed are bonded by direct bonding. Next, the bulk single crystal semiconductor substrate is thinned, and a thin semiconductor layer of the first conductivity type is disposed on the semiconductor substrate on which the trench is formed. Here, it is preferable that the semiconductor substrate of the first conductivity type and the bulk single crystal semiconductor substrate have different plane orientations as a method for obtaining the semiconductor device according to the first aspect. It will be.

According to the method of manufacturing a semiconductor device of the ninth aspect, a trench in which at least the side wall has a low concentration is formed in the semiconductor substrate of the first conductivity type. Then, the inside of the trench is filled with a semiconductor film of the second conductivity type. Further, the SOI substrate in which a thin semiconductor layer of the first conductivity type is disposed on the substrate with an insulating film interposed therebetween is directly bonded to the semiconductor substrate in which the trench is formed. Next, at least the substrate of the SOI substrate is removed, and a semiconductor layer of the first conductivity type is disposed on the semiconductor substrate on which the trench is formed.
Here, assuming that the semiconductor substrate of the first conductivity type and the semiconductor layer of the first conductivity type of the SOI substrate have different plane orientations, the semiconductor device according to claim 1 is obtained. This is a preferable method for the above.

According to the semiconductor device manufacturing method of the present invention, a semiconductor layer of the second conductivity type is formed on the semiconductor substrate of the first conductivity type. Then, a trench is formed in the semiconductor layer. Further, the first conductivity type semiconductor layer is formed inside the trench by the epitaxial growth method to fill the inside of the trench, and the epitaxial growth is continued, so that the first conductivity type semiconductor layer is formed on the upper surface of the second conductivity type semiconductor layer.
A conductive semiconductor layer is formed. Next, the first conductive type semiconductor layer on the second conductive type semiconductor layer is thinned.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a semiconductor device according to the present embodiment. This semiconductor device is an N-channel type power MOSFET. In FIG. 1, a semiconductor support substrate 1 includes an N ⁺ type silicon substrate 2 and an N type silicon layer 3 formed thereon. The N-type silicon layer 3 is formed by epitaxial growth. A thin N-type silicon layer 4 is disposed on the support substrate 1 (N-type silicon layer 3). Specifically, the thickness of the N-type silicon layer 4 is 1 μm or less. Further, the N-type silicon layer 4 and the semiconductor support substrate 1 (substrate 2, silicon layer 3)
And the plane orientation is different. Specifically, the plane direction of the semiconductor support substrate 1 is (110), and the plane direction of the N-type silicon layer 4 is (100). Note that the plane orientation of the N-type silicon layer 4 may be the same as the plane orientation of the semiconductor support substrate 1.

A trench (groove) 5 is formed in the N-type silicon layer 3, and the trench 5 is filled with single-crystal silicon to form a P-type diffusion region 6. The P-type diffusion region 6 extends in the depth direction from the substrate surface, and has a larger spreading dimension in a normal direction of the substrate surface than a lateral spreading dimension in an arbitrary plane parallel to the substrate surface. This P-type diffusion region 6 becomes a body P region in the transistor.

FIG. 2 is a plan view of the N-type silicon layer 3 taken along line AA. In FIG. 2, a large number of body P regions 6 (trench 5) are formed in N-type silicon layer 3. This body P region 6 (trench 5) has a columnar shape.

In FIG. 1, an N-type region sandwiched between body P region 6 (trench 5) serves as drift N region 7. On the support substrate 1 (N-type silicon layer 3), a gate electrode 11 is formed via a gate oxide film 10.
In the surface layer portion of the N-type silicon layer 4 below the gate electrode 11, a P ⁺ type region (channel P region) 8 for controlling Vt of a channel is formed. Further, an N ⁺ type region (source N region) 9 is formed in a surface layer inside the channel P region 8. Then, source electrode 12 is in contact with channel P region 8 and source N region 9.
A drain electrode (not shown) is arranged on the lower surface of the N ⁺ type silicon substrate 2.

The operation of the transistor is such that when the transistor is on, the outermost surface of the channel P region 8 is inverted to form a channel, and the drift N region 7 and the high concentration N type region ( Through 2), a current flows to the drain electrode on the back surface. On the other hand, in the off state, the depletion layers extending from the respective PN junction regions are in contact with each other, and are completely depleted from the surface of the substrate to a considerably deep region in accordance with the cool MOS principle described above.
Thereby, a high breakdown voltage can be maintained. In other words, the concentration and dimensions are controlled to ensure such a high breakdown voltage.

The body P region 6 and the drift N region 7
As the number increases, the current capacity per unit area increases,
Needless to say, it is preferable. Next, the manufacturing method will be described with reference to FIGS.

First, as shown in FIG. 3A, a high concentration N-type substrate 2 having an impurity concentration of about 1 × 10 ²⁰ / cm ³ is prepared. Then, the N-type single-crystal silicon layer 3 is formed by using a mixed gas of silane gas and phosphine gas, for example.
Epitaxial growth is performed by 5 μm. At this time, in order to eliminate the increase in the thickness of the substrate due to the formation of the epitaxial layer 3, for example, it is desirable to use a wafer that is thinner by about 45 μm in advance than an appropriate thickness corresponding to the diameter of the silicon wafer to be used.

Although the impurity concentration of the N-type layer 3 is determined by the width of the drift N region, it is generally 1 × 10 ¹⁵ / cm.
It is about ³ to 1 × 10 ¹⁷ / cm ³ . Further, FIG.
As shown in FIG. 2B, an oxide film 13 having a thickness of about 100 nm is formed on the surface of the N-type single crystal silicon layer 3 by thermal oxidation or the like, a photoresist is applied, and a desired region 13a is etched. As a result, an opening 13a is formed.

Further, using the oxide film 13 (or a laminated film of the oxide film and the resist) as a mask material, as shown in FIG. 3C, the single crystal silicon layer 3 is etched to form a trench (groove) 5. I do. Etching is ICP (Induct
ive Coupled Plasma) or wet etching using KOH or TMAH. When wet etching is used, formation of crystal defects due to etching damage is suppressed as compared with dry etching. Furthermore, although a substantially vertical trench (groove) can be formed by utilizing the anisotropy of etching,
In this case, it is necessary that the plane orientation of the silicon wafer is (110) and the side wall after etching is the (111) plane. The material used as the mask may be a nitride film or a resist film other than the oxide film. These mask materials may be removed by wet etching or the like after the trench is formed by etching, or the next epitaxial growth step may be performed as it is. FIG. 3C shows a case where the mask material is removed. Also, in order to remove defects caused by damage during etching, CDE (Chemical Dry Etch) is used.
ching) or a continuous step of thermal oxidation and thermal oxide film removal, that is, sacrificial oxidation and the like.

Subsequently, as shown in FIG. 4A, for example, silane (SiH ₄ ) or dichlorosilane (SiCl ₂ H
_{Using 2} ) as a material gas, an N-type single crystal silicon film 14 is epitaxially grown. The thickness of the epitaxially grown single-crystal silicon film (epitaxial film) 14 is 以上 or more of the width of the trench 5 so that the trench 5 is completely filled (buried). Here, the opening is tapered by slightly isotropically etching the opening, or the temperature and gas are changed during the epitaxial growth step, so that no cavity is formed inside the hole by increasing the filling property. A method such as etching only the opening may be used.

After such an epitaxial process, the non-opening area on the wafer surface is of course not only when the mask material remains but also when the mask material is removed by etching due to the complexity of the shape near the opening. There is a concern that the silicon will be polycrystalline or amorphous silicon instead of crystalline silicon. Therefore, as shown in FIG. 4B, the surface of the semiconductor substrate is subjected to CMP (Chemical Mechanical).
Polishing or dry etching using a technique such as cal polishing is performed to remove the epitaxial film 14 on the surface.
More specifically, it is removed to at least the position that was the surface of the initial silicon layer 3.

For this polishing, for example, CMP (Chemical Mec.)
Although the hanical polishing method can be used, the amount of single crystal silicon removed by polishing is at least equal to or greater than the thickness of the grown single crystal silicon layer 3. At this time, excessive polishing may cause the surface to sink, which may reduce the depths of the drift N region and the body P region and reduce the withstand voltage of the element. In order to prevent this, it is necessary to accurately control the polishing amount. For example, the polishing amount can be controlled by, for example, monitoring the presence of a phosphorus element and terminating the polishing when the concentration increases while monitoring the presence of the phosphorus element. P at this time
As a method of monitoring elements, a difference in polishing rate depending on the type of impurities may be used in addition to instrumental analysis such as elemental absorption. Alternatively, the single crystal silicon film 14 in the trench 5
When epitaxial growth is used for filling, a thin oxide film is formed on the upper surface of the substrate, which is a non-opening region, and by preventing epitaxial growth on the thin oxide film, the oxide film is used as a stopper at the time of polishing to serve as an end point of polishing. Controllability may be improved. Specifically, for example, the initial substrate is 20
After thermal oxidation of about 0 nm, a photoresist is applied thereon, and a resist and an oxide film in a desired region are removed in a photo step. Next, this laminated film is used as a mask material and filled with single-crystal silicon that has been etched and epitaxially grown. At this time, single crystal silicon does not grow on the oxide film. When the surface is polished, the polishing rate is different between the oxide film and silicon. Therefore, when the oxide film is exposed, it functions as a stopper, and the end point of polishing can be detected. Subsequently, when the thermal oxide film is removed with, for example, a diluted HF aqueous solution, a step corresponding to the thickness of the thermal oxide film is generated. This step is at most about 200 nm, and can be flattened by a small amount of polishing. Therefore, it is possible to suppress variations in the polishing amount.

After such a polishing step, FIG.
As shown in (c), the substrate 15 having the hydrogen storage layer 17
Prepare That is, the hydrogen storage layer 17 is formed by ion implantation of hydrogen atoms in a region within 1 μm from the surface (the lower surface in the figure) of the N-type silicon substrate 15. As described above, the bonding semiconductor substrate 15 has the specific atom (hydrogen atom) layer 17 embedded at a predetermined depth, and stores hydrogen between the thick silicon layer 16 and the thin N-type silicon layer 18. Layer 17 is formed. Then, the bonding semiconductor substrate 15 (thin silicon layer 18) is bonded to the substrate 1 by direct bonding. This is peeled off by an appropriate heat treatment at the atomic buried layer 17 (hydrogen-containing surface) of the bonding semiconductor substrate 15, leaving a thin N layer 18 as shown in FIG.

The peeling by hydrogen ion implantation and heat treatment on the bonding substrate 15 described above is a known technique called smart cut. In addition, instead of hydrogen,
Argon, xenon, helium, and hydrogen molecules may be used.

Thus, the thin N-type silicon layer 18 is arranged on the substrate 1. At this time, the structure is such that a low-concentration N-type single-crystal silicon layer 4 is uniformly formed on a high-concentration N-type silicon substrate 2 by a thickness equal to the depth of the body P region (6). , Body P region 6 is formed in N type silicon layer 4 (drift N region 7).
On this substrate 1, a thin N-type silicon layer 16 is formed.

Here, the plane orientations of the two substrates 1 and 15 to be bonded can be different. Note that, although the bonding semiconductor substrate 15 is bonded to the support substrate 1 and only the thin silicon layer 18 is left by the heat treatment, an N-type single crystal silicon is formed by epitaxial growth instead of this, and the epitaxial layer is thinned. Is also good.

Thereafter, as shown in FIG. 1, a channel P region 8 and a source N region 9 are formed, and a gate oxide film 10, a gate electrode 11, a source electrode 12, and the like are arranged. As a result, an N-channel type power MOSFET is completed.

Next, specific dimensions and impurity concentrations of the device will be described. Assuming a specification of an off withstand voltage of 600 volts, in the basic structure shown in FIG. 1, the shapes of the regions of different conductivity types (drift N region 7 and body P region 6) are as shown in FIGS. For example, depth D = 45μ
m and a width W = 2 μm. Further, as shown in FIG. 2, the body P region 6 is circular in a plan view on the wafer surface. That is, from the viewpoint of device performance, the shape of the body P region 6 is preferably a cylindrical shape having no electric field concentration at an edge portion. This is because the portion where the electric field is concentrated may determine the breakdown voltage (avalanche breakdown).

With respect to the arrangement of the body P region 6,
In a structure in which both the vertical and horizontal directions are aligned on a straight line as shown in FIG. 2, the distance between adjacent body P regions 6 greatly differs depending on the direction. That is, an arbitrary body P
Assuming that the distance from the region 6 to the body P region 6 at the first proximity position (up, down, left and right) is d1, the distance to the body P region 6 at the second proximity position (obliquely lower right, etc.). d
2 becomes √2d1. In other words, since the width of the drift N region 7 is not uniform, the conditions for complete depletion are not uniform. That is, in order to completely deplete the drift N region 7, a voltage more than necessary is applied between the body P regions 6 in the first proximity, and there is a possibility that breakdown occurs here. Therefore, in order to avoid the above problems,
It is desirable that the spacing between the adjacent body P regions 6 be as uniform as possible. For example, as shown in FIG. May be arranged.

Although the body P region 6 has been described as having a columnar shape, as described above, the method of manufacturing the body P region or the drift N region is based on trench formation by etching and filling of the inside thereof by epitaxial growth. Since the epitaxial growth depends on the plane orientation of the crystal, considering the crystallinity of the epitaxially grown film, when the crystal plane orientation changes continuously like the inner wall of a cylindrical opening region, the crystal of the epitaxial film Sex may be disturbed.

Therefore, as shown in FIGS. 7 and 8, the plane to be epitaxially grown may have a constant plane orientation. That is, when a wafer having a crystal orientation of (100) is used, the plane orientations are (110) and (100), respectively.
Represents the case of a plane. Here, it is assumed that the horizontal direction in the figure is parallel to the orientation flat of the wafer.

Alternatively, as shown in FIGS. 9 and 10, the body P region 6 is formed into a regular hexagon in consideration of the balance between the two effects described above, that is, alleviating the electric field concentration and improving the crystallinity of the epitaxial film. Is also good. Similarly, as shown in FIGS. 11 and 12, the body P region 6 may be a regular octagon. Thus, it can be made into a polygonal shape. In both FIG. 10 and FIG. 12, the adjacent body P regions 6 are arranged such that the adjacent intervals are uniform.

It is possible to provide an optimum element design by properly using these shapes according to the purpose. Alternatively, as shown in FIG. 13, the body P regions 6 may be arranged in an elongated rectangle. In this case, the length of one side of the rectangular shape is about 2 μm corresponding to the width of the opening region, and the other is several mm corresponding to the size of the cell. Here, as another example, the long side may be provided with a non-opening region of about 2 μm at intervals of, for example, about 100 μm to maintain the strength at the time of etching.

Alternatively, as shown in FIG.
The region 6 may be arranged at an angle of 45 degrees. As aforementioned,
In consideration of the surface orientation dependence of etching (particularly wet etching) and epitaxial growth, it is effective to arrange the semiconductor device so that an appropriate plane orientation appears on the side wall.

As described above, this embodiment has the following features. (A) As a method for manufacturing a semiconductor device, as shown in FIG. 3C, a trench 5 in which at least the side wall has a low concentration in an N-type silicon substrate (a semiconductor substrate of a first conductivity type) 1 is formed. As shown in FIG. 4A, a P-type epitaxial film (second conductive type semiconductor material) 1 is formed in the trench 5.
As shown in FIG. 4C, a silicon substrate (first conductive type bonding semiconductor substrate) 15 in which a specific atom layer 17 is embedded at a predetermined depth, and a semiconductor in which a trench 5 is formed. The substrate 1 is bonded by direct bonding. And
As shown in FIG. 5, a thin silicon layer (a semiconductor layer of the first conductivity type) 18 is disposed on the substrate 1 in which the trench 5 has been formed by peeling off the atomic buried layer 17 of the silicon substrate 15 by heat treatment. . Therefore, the diffusion region 10 in FIG.
In the case of forming 2,103 by epi growth, many photo steps are required, but in this example, no photo step is required. Thus, the substrate process can be improved, and the cost of all processes can be reduced. In FIG. 20,
Gate / source portion for controlling channel and drift layer 10
If it is attempted to make the two have a one-to-one correspondence with respect to the positional relationship of 3, it is difficult to maintain the alignment accuracy of the two in a miniaturized element.
Alignment is unnecessary and excellent in fine processing.

Further, the plane orientations of the substrates 1 and 15 to be bonded are different (the plane orientation of the silicon layer 4 on the support substrate 1 is different from the plane orientation of the substrate 1). The orientation is (110), and the plane orientation of the silicon layer 4 is (1).
00) has the following effects. In order to control the shape of the trench 5 formed by etching and not to form damage or defects on the substrate by etching,
As described earlier, wet etching is more effective than dry etching.
Although it is necessary to use a substrate having a plane orientation, there is a concern that the (110) substrate is inferior to the normal (100) substrate in the film quality and channel resistance of the gate oxide film. On the other hand, the substrate to be bonded is used as a (100) substrate, and a gate and a source region are formed here.
The disadvantage that the substrate is inferior to a normal (100) substrate can be solved. (Second Embodiment) Next, a second embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

In the first embodiment, the high-concentration N-type substrate 2
Although an N-type layer (drift N region) 3 is formed by epitaxial growth on the upper surface, another method is used in the present embodiment. First, as shown in FIG. 15A, a trench 21 is formed by etching a high-concentration N-type silicon substrate 20 as a semiconductor substrate of the first conductivity type. And FIG.
As shown in (b), for example, heat treatment is performed in a gas phase containing a P-type impurity element such as boron (B). As a result, P-type impurities are introduced into silicon, and the concentration of the desired region 22 is apparently reduced. That is, the impurity is diffused from the opening of the trench 21 into the silicon substrate 20 to effectively reduce the impurity concentration on the inner wall of the trench 21.

The subsequent steps are the same as those described above. That is, as shown in FIG. 15C, the inside of the trench 21 is filled with P-type silicon (second-conductivity-type semiconductor material) 23 by an epitaxial growth method, and a thin N A silicon layer (first conductive type semiconductor layer) 24 is disposed.

Here, the plane orientation of the silicon substrate 20 and the N-type silicon layer 24 can be made different by using a bonding method by direct bonding. The substrate obtained by this method can omit a thick film epitaxial growth step for forming an N-type layer (drift region),
In addition to greatly contributing to the cost reduction of the process, it has the following advantages. That is, the profile of the drift N region (22) formed by the present method has a shape in which the concentration gradually decreases from the end of the body P region 23, and the depletion layer is more likely to extend as the distance from the end increases. No excessive voltage is required to deplete the entire drift N region. This does not require a hexagonal vertex arrangement as shown in FIG. 10 or the like, and facilitates layout of wiring and the like. Furthermore, in the etching step, the etching depth is desirably the same as the upper surface of the high-resistance N region (the member denoted by reference numeral 2 in FIG. 3C), but it is extremely difficult to perform this accurately. There is a concern that etching is excessive as shown in FIG. 19A or insufficient as shown in FIG. Thus, the variation in the positional relationship between the high-concentration N region 2 and the drift N region causes a variation in device performance. On the other hand, in this example, since the drift N region is formed after the etching, the relationship between the two is determined in a self-aligned manner, and thus there is no such a concern. (Third Embodiment) Next, a third embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

As a manufacturing method, first, FIG.
The steps described with reference to FIGS. 4A, 4B, and 4C are performed. That is, an N-type silicon layer 3 is formed on a high-concentration N-type silicon substrate 2 to form an N-type silicon substrate (a semiconductor substrate of the first conductivity type) 1. A trench 5 is formed, the inside of the trench 5 is filled with a P-type silicon film 14, and the surface is flattened.

Then, as shown in FIG.
A bulk single crystal silicon substrate (bulk wafer) 30 as a conductive type bulk single crystal semiconductor substrate is prepared, and the silicon substrate (support substrate) 1 in which the trench 5 is formed and the bulk substrate 30 are bonded by direct bonding. Further, grinding and polishing are performed from the back surface of the bulk substrate 30 to reduce the thickness as shown in FIG. As a result, the thin N-type silicon layer 31 is disposed on the silicon substrate 1 on which the trench 5 has been formed.

Also in this case, the plane orientation of the silicon substrate 1 and the N-type bulk single crystal silicon substrate 30 can be made different by using the bonding method by direct bonding. In this example, since a special process and a wafer are not required, the process can be simplified. (Fourth Embodiment) Next, a fourth embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

As a manufacturing method, first, FIG.
The steps described with reference to FIGS. 4A, 4B, and 4C are performed. That is, an N-type silicon layer 3 is formed on a high-concentration N-type silicon substrate 2 to form an N-type silicon substrate (a semiconductor substrate of the first conductivity type) 1. A trench 5 is formed, the inside of the trench 5 is filled with a P-type silicon film 14, and the surface is flattened.

Then, as shown in FIG. 17A, an SOI substrate 40 is prepared as a bonding substrate to be bonded. SOI
In the substrate 40, a thin N-type silicon layer (first conductivity type semiconductor layer) 43 is disposed on a silicon substrate 41 via an oxide film 42 as an insulating film. This SOI substrate 40
And a silicon substrate (supporting substrate) 1 having a trench 5 formed therein
And are bonded by direct bonding. Specifically, the upper surface (flat surface) of the silicon substrate 1 and the thin film layer 43 of the SOI substrate 40 are directly bonded.

Subsequently, the back surface of the SOI substrate 40 (substrate 4
As shown in FIG. 17B, at least the substrate 41 is removed from the first side) by grinding / polishing or wet etching, more specifically, to the interface of the buried oxide film 42. At this time, the oxide film 42 functions as a stopper for polishing or wet etching, so that the film thickness uniformity is high. Thus, the N-type silicon layer 43 is arranged on the silicon substrate 1 on which the trench 5 has been formed.

Also in this case, the bonding between the silicon substrate 1 and the N-type SOI
The plane orientation of the mold silicon layer 43 can be made different. (Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIG.
The following description focuses on the differences from this embodiment.

This example is a method that does not require a bonding substrate. First, as shown in FIG. 18A, a P-type single-crystal silicon layer (second-conductivity-type semiconductor layer) 51 is formed on a high-concentration N-type silicon substrate (first-conductivity-type semiconductor substrate) 50 by an epitaxial growth method. To form Then, FIG.
As shown in the figure, a trench 52 is formed by etching,
Further, as shown in FIG. 18C, an N-type single-crystal silicon layer (first conductivity type semiconductor layer) 53 is formed inside the trench 52 by an epitaxial growth method, and the inside of the trench 52 is filled (filled). Do). At this time, the epitaxial growth is continued, that is, advanced excessively, and an N-type silicon layer (first conductivity type semiconductor layer) 53 is formed on the upper surface of the silicon layer 51. Specifically, a single-crystal N-type silicon layer 54 having a thickness of 1 μm or more is formed on the P-type silicon layer 51.

Since single-crystal silicon also grows on the region other than the trench opening, materials such as a resist and an oxide film used as an etching mask for forming a trench are removed before the epitaxial process.

Subsequently, the surface of the silicon layer 53 is ground,
By polishing, the film is thinned as shown in FIG.
As a result, the thin N-type silicon layer 5
4 will be arranged.

In addition to the above-described embodiments, the present invention may be implemented as follows. Although the description has been made by taking an N-channel element as an example, the present invention may be applied to a P-channel element in which conductivity types P and N are reversed.

In addition to the MOSFET, the present invention may be applied to a MOS thyristor or an IGBT (a structure in which the N layer 2 in FIG. 1 is a P-type collector layer).

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view taken along line AA in FIG.

FIG. 3 is a cross-sectional view for explaining a manufacturing process.

FIG. 4 is a cross-sectional view for explaining a manufacturing process.

FIG. 5 is a cross-sectional view for explaining a manufacturing process.

FIG. 6 is a cross-sectional view of a semiconductor device.

FIG. 7 is a cross-sectional view of a semiconductor device.

FIG. 8 is a cross-sectional view of a semiconductor device.

FIG. 9 is a cross-sectional view of a semiconductor device.

FIG. 10 is a cross-sectional view of a semiconductor device.

FIG. 11 is a cross-sectional view of a semiconductor device.

FIG. 12 is a cross-sectional view of a semiconductor device.

FIG. 13 is a cross-sectional view of a semiconductor device.

FIG. 14 is a cross-sectional view of a semiconductor device.

FIG. 15 is a cross-sectional view for explaining a manufacturing process in the second embodiment.

FIG. 16 is a cross-sectional view for explaining a manufacturing process in the third embodiment.

FIG. 17 is a cross-sectional view for explaining a manufacturing step in the fourth embodiment.

FIG. 18 is a cross-sectional view for explaining a manufacturing step in the fifth embodiment.

FIG. 19 is a cross-sectional view for explaining a manufacturing process.

FIG. 20 is a cross-sectional view illustrating a conventional device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor support substrate, 2 ... N ⁺ type silicon substrate, 3 ... N
Type silicon layer, 4 ... N type silicon layer, 5 ... trench, 6
... P-type diffusion region, 14 ... P-type epitaxial film, 15 ...
Bonding substrate, 17: hydrogen storage layer, 18: N-type silicon layer, 20: N ⁺ type silicon substrate, 21: trench, 30
... Bulk wafer, 40 ... SOI substrate, 41 ... Silicon substrate, 42 ... Oxide film, 43 ... Silicon layer, 50 ... N ⁺ type silicon substrate, 51 ... P type silicon layer, 52 ... Trench
53 ... N-type silicon layer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 658E (72) Inventor Toshio Sakakibara 1-1-1, Showa-cho, Kariya-shi, Aichi Pref. (72) Inventor Hitoshi Yamaguchi 1-1-1 Showa-cho, Kariya-shi, Aichi F-term in DENSO Corporation (reference) 5F052 DA01 DB01 GC03 JA01 KB01

Claims (11)

[Claims] 1. A semiconductor support substrate (1) of a first conductivity type, formed on the semiconductor support substrate (1), extending in a depth direction from a substrate surface, and extending in an arbitrary plane parallel to the substrate surface. A second conductivity type diffusion region (6) having a larger spreading dimension in the normal direction of the substrate surface than the spreading dimension; and a semiconductor supporting substrate (1) formed on the semiconductor supporting substrate (1). A semiconductor device comprising: a first conductivity type semiconductor layer (4) having a different plane orientation. 2. The semiconductor device according to claim 1, wherein the plane orientation of the semiconductor support substrate (1) is (110), and the plane orientation of the semiconductor layer (4) is (100). Semiconductor device. 3. A step of forming a trench (5) in which at least a side wall has a low concentration in a semiconductor substrate (1) of a first conductivity type, and a semiconductor material (1) of a second conductivity type in the trench (5).
4) embedding, a first conductivity type bonding semiconductor substrate (15) in which a layer of specific atoms (17) is embedded to a predetermined depth, and a semiconductor substrate (1) in which the trench (5) is formed. Bonding directly by bonding, and heat-treating the semiconductor substrate (15) by bonding.
And a step of disposing a thin first conductivity type semiconductor layer (18) on the semiconductor substrate (1) on which the trench (5) has been formed by stripping with the atomic buried layer (17). A method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the two substrates (1, 15) to be bonded have different plane orientations. 5. An opening of the trench (21) by forming a trench (21) in a semiconductor substrate (20) of a first conductivity type and performing a heat treatment in a gas phase containing an impurity of a second conductivity type. From the semiconductor substrate (20) to the trench (2)
1) a step of reducing the impurity concentration of the inner wall; and forming a second conductive type semiconductor material (2) in the trench (21).
A method of manufacturing a semiconductor device, comprising: a step of embedding in 3); and a step of arranging a thin semiconductor layer (24) of a first conductivity type on the semiconductor substrate (20). 6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor substrate (20) and a first conductive type semiconductor layer (2) are formed.
A method for manufacturing a semiconductor device, wherein the plane orientation is different from that of 4). 7. A step of forming a trench (5) in a semiconductor substrate (1) of a first conductivity type having at least a side wall with a low concentration, and a semiconductor material (1) of a second conductivity type in said trench (5).
4) embedding the first single-type bulk single-crystal semiconductor substrate (30) and the semiconductor substrate (1) on which the trench (5) is formed by direct bonding; Thinning the semiconductor substrate (30) and arranging a thin semiconductor layer (31) of the first conductivity type on the semiconductor substrate (1) on which the trench (5) is formed. Semiconductor device manufacturing method. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor substrate of the first conductivity type and the bulk single crystal semiconductor substrate have different plane orientations. Device manufacturing method. 9. A step of forming a trench (5) in which at least a side wall has a low concentration in a semiconductor substrate (1) of a first conductivity type, and a semiconductor material (1) of a second conductivity type in the trench (5).
4) embedding with an SOI substrate (4) in which a thin first conductivity type semiconductor layer (43) is disposed on a substrate (41) via an insulating film (42);
0) and a step of directly bonding the semiconductor substrate (1) having the trench (5) formed thereon, and removing at least the substrate (41) of the SOI substrate (40) to remove the trench (5). Semiconductor substrate formed (1)
Arranging the first conductivity type semiconductor layer (43) on the semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first conductivity type semiconductor substrate (1) and the first conductivity type semiconductor layer (43) of the SOI substrate (40) are in plane. A method for manufacturing a semiconductor device, wherein the directions are different. 11. A step of forming a semiconductor layer (51) of a second conductivity type on a semiconductor substrate (50) of a first conductivity type, and a step of forming a trench (52) in the semiconductor layer (51). Forming a semiconductor layer (53) of a first conductivity type inside the trench (52) by an epitaxial growth method to bury the inside of the trench (52) and continuing the epitaxial growth to form a semiconductor layer (2) of the second conductivity type; Forming a first conductivity type semiconductor layer (53) on the upper surface of the first conductivity type semiconductor layer (53); and thinning the first conductivity type semiconductor layer (53) on the second conductivity type semiconductor layer (51). And a method of manufacturing a semiconductor device.