JPH0453142A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable growth of Si layer of the predetermined thickness in an intrinsic base region without relation to roughness of entire surface of a substrate by exposing a region to form the intrinsic base region after formation of an external base region and realize therein a molecular beam epitaxial growth. CONSTITUTION:A polycrystalline Si to form an external base region is deposited in the thickness of about 30nm by CVD method. A P type polycrystalline Si layer 5 is formed by adding a P type impurity such as boron. A SiO2 film 6 is deposited on the layer 5 as an insulating film. The film 6, layer 5 and a mask 3 on the film 3 are removed. A single crystalline Si region is exposed and a P type Si layer 7 is grown by the molecular beam epitaxial growth method. A polycrystalline Si 7a is selectively removed by utilizing difference of etching characteristics of single and polycrystalline Si. A SiO2 film 6a is deposited on the entire part of surface. The deposited SiO2 film 6a is etched by the etching having directivity to remove the other portions, leaving the part on the side wall of aperture of the film 6. High concentration impurity-added N type polycrystalline Si layer 8 is deposited. A layer 8 is patterned, leaving an N type polycrystalline Si layer 8a on the aperture of the SiO2 film 6b.

Description

[Detailed Description of the Invention] [R required] Regarding a method for manufacturing a semiconductor device including a bipolar transistor suitable for high-speed operation, the present invention aims to provide a new method for manufacturing a semiconductor device including a lateral base contact type bipolar transistor. , a Si substrate with a single-crystal Si surface region on which an intrinsic base is to be formed, an external base region formed to surround the surface region, and an insulating film formed thereon.
A process of performing molecular beam epitaxial growth to grow monocrystalline Si connected to the external base region on the monocrystalline Si surface region and polycrystalline Si on the insulating film, and a process of selectively etching away the polycrystalline Si. The grown single-crystal Si constitutes an intrinsic base.

[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a bipolar transistor suitable for high-speed operation.

[Prior Art] A typical structure of a bipolar transistor is shown in cross-sectional view in FIGS. 2(A) and 2(B), and will be explained using an npn transistor as an example.

FIG. 2 (A> shows a collector region 11 made of n-type Si, showing an upper base contact type bipolar transistor.
A base region 13 made of P-type Si is formed on the
An emitter region 17 made of n-type Si is formed in the surface region of this base region 13. Insulation protection J119 is
Predetermined regions of these emitter region 17 and base region 13 are exposed to define a contact region for t[i. On the surfaces of the emitter region 17, base region 13, and collector region 11, an emitter electrode 21, a base salt @22,
The collector electrode fi23 is formed using AR, for example.

In the illustrated structure, a region of the base region 13 that functions as a base for transporting carriers injected from the emitter to the collector is a region directly below the emitter region 17 . The base region outside the base region functions as a true base region, but has the role of transmitting the potential from the base salt fi22. Here, if the contact area between the base region 13 and the collector region 11 is large, the pn junction area becomes large and the floating capacitance becomes large. This capacitance becomes a cause of limiting the operating speed.

Therefore, a lateral base contact type structure as shown in FIG. 2(B) is known as a bipolar transistor structure suitable for high-speed operation.

In FIG. 2(B), an insulating region 12 is formed on the surface of a collector region 11 made of n-type Si, and only a portion of the collector region 11 is exposed within the opening. Intrinsic base region 15 is located above collector region 11 that is not exposed within this opening.
is formed of a p-type wheel crystal S1. An external base region 16 made of p-type polycrystalline Si is in contact with the side surface of this intrinsic base region 15. n within the surface of the intrinsic base region 15
An emitter region 17 of type Si is formed, forming a bipolar transistor structure. An emitter electrode 21, a base pole 22, and a collector electrode 23 are placed on the emitter region 17, external base region 16, and collector region 11, respectively.
is formed using AR, for example.

In the configuration of FIG. 2(B), since the external base region 16 is separated by the collector region 11 and the insulating region 12, the capacitance formed between the external base region 16 and the collector region 11 is reduced. Therefore, the lateral base contact type bipolar transistor shown in FIG. 2(B) is more suitable for high-speed operation than the upper base contact type bipolar transistor shown in FIG. 2(A).

The third example of the conventional technology for manufacturing a lateral base contact type bipolar transistor as shown in FIG.
This will be explained with reference to FIGS. (A), (B), and (C).

In FIG. 3(A), a base region 15 made of p-type Si is formed on a collector region 11 made of n-type Si,
A mask 25 having a predetermined pattern is formed thereon. This mask 25 is made of Si NM, for example, and is resistant to etching.

By performing selective etching using mask 25, the surface portions of base region 15 and collector region 11 therebelow are selectively etched.

This etching method is active ion etching (RI).
E) Preferably, anisotropic etching is used, such as
Thereafter, an insulator region 12 is formed under the mask 25 so as to surround the mesa that is not formed. For example, the insulating region 12 is formed by depositing an insulating material directionally by sputtering or the like. Thereafter, etching or the like may be performed so that the side surfaces of the base region 15 are exposed. In this way, a protruding intrinsic base region 15 surrounded by the insulating region 12 is formed. Similar structures can also be created using different processes.

Thereafter, as shown in FIG. 3(B), a p-type polycrystalline Si layer 16 is formed on the insulating region 12 by bias sputtering.
Deposit. In other words, the polycrystalline Si layer 16 is formed by bias sputtering, in which sputtering is performed by introducing Ar gas or the like while applying an appropriate bias voltage to the substrate.
grows only in the concavity. In this way, the extrinsic base region 16 laterally contacts the intrinsic base region 15.
form.

Thereafter, as shown in FIG. 3(C), a protection layer 11119 made of SiO2 or the like is formed on the surface, openings are made in the areas where electrodes are to be formed, an AJ film is deposited, and patterning is performed to form the emitter electrode 21 and the base electrode. 22. A collector electrode 23 is formed to form a bipolar transistor.

[Problems to be Solved by the Invention] According to the conventional technique described with reference to FIGS. 3(A), (B), and (C), polycrystalline crystals are formed in the concave portions on the sides of the intrinsic base by bias sputtering. Bias sputtering is a process that is extremely sensitive to irregularities on the substrate surface, such as when forming an external base region made of Si. When transistors of various sizes are mixed on the substrate, it is almost impossible to embed polycrystalline Si uniformly on the substrate, so it is difficult to embed polycrystalline silicon evenly on the substrate. It is extremely difficult to form them by the processes shown in FIGS. 3(A), (B), and (C).

An object of the present invention is to provide a novel method for manufacturing a semiconductor device including a lateral base contact type bipolar transistor.

Another object of the present invention is to provide a method for manufacturing a semiconductor device including a bipolar transistor, which can form an extrinsic base region that laterally contacts an intrinsic base region without being affected by surface irregularities.

Means for Solving the Problems J The method for manufacturing a semiconductor device of the present invention comprises a single crystal Si surface region on which an intrinsic base is to be formed, an external base region formed to surround the surface region, and a A process of performing molecular beam epitaxial growth of Si on a Si substrate having an insulating film formed on the surface region, growing single crystal S1 connected to the external base region on the single crystal Si surface region, and growing polycrystalline Si on the insulating film. and a step of selectively etching away polycrystalline Si, and this single crystal S1 constitutes an intrinsic base.

That is, before forming the intrinsic base region, an extrinsic base region is formed, an insulating film is provided on the extrinsic base region, a single crystal region where the intrinsic base region is to be formed is exposed, and single crystal Si is grown thereon by molecular beam epitaxial growth. grow up. At this time, the Si region grown on the insulating film becomes polycrystalline. The polycrystalline Si on this insulating film is selectively etched away.

[Operation] After creating the external base region, the region where the intrinsic base region is to be created is exposed and molecular beam epitaxial growth is performed there, so that a Si layer of a predetermined thickness is formed in the intrinsic base region regardless of the unevenness of the surface of the entire substrate. can grow.

Furthermore, since Si deposited in areas other than the intrinsic base region becomes polycrystalline, it can be easily and selectively removed.

Connection between the intrinsic base and the extrinsic base can be made with self-line without using a mask.

Molecular beam epitaxial growth of Si is a stable process that can be easily performed as long as the surface of the substrate is properly treated before growth. Therefore, a homogeneous intrinsic base region can be easily formed on a large-area substrate. It becomes easy to create large-scale circuits or large-capacity memories.

[Embodiment 1] The present invention will be described in detail below, taking as an example the case of manufacturing a Hpn bipolar transistor.

Referring to FIG. 1(A), a high concentration (e.g. resistivity
．． Using a substrate in which an n-type Si epitaxial layer 2 with a low concentration (for example, a specific resistance of 0.1 Ωan) is formed on an n-type Si substrate 1 with a
A N film 3 is deposited to a thickness of about 1100 nm. Next, this SiN film 3 is patterned to remove the portion other than the portion that will become the intrinsic transistor region.

Using this buttered SiN film 3 as a mask,
A surface portion of the type Si epitaxial layer 2 is selectively removed, for example, to a thickness of about 25 nm.

Subsequently, as shown in FIG. 1 (CB), thermal oxidation is performed using the SiN film 3 as a mask to grow an oxide film 4 of about 50 nm on the exposed portions of Si.

Si 8f expands by oxidation, so Si
The surface of the O2 film 4 is approximately at the same level as the n-type S1 pittaxial layer 2 under the mask 3.

Next, as shown in FIG. 1(C), polycrystalline Si to form an external base region is deposited to a thickness of about 30 nm and 30 m by CVD.
accumulate. This polycrystalline Si is deposited with doping residue (
For example, by adding diborane (82H6) to make it p-type, or by depositing polycrystalline Si and then adding p-type impurities such as boron using ion implantation, p-type crystalline Si can be made p-type.
Layer 5.

A 5i02 film 6 is deposited as an insulating film on this polycrystalline Si layer 5 to a thickness of, for example, about 300 nm.

That is, in the structure of FIG. 1(C), 5iNIi13 is formed in the portion where the intrinsic base region is to be formed, and the P-type polycrystalline Si layer which is to form the extrinsic base is surrounded by 5iNIi13.
A layer 5 is formed in contact with a 5i02 film 6 covering it.

Thereafter, as shown in FIG. 1(D), the 5i02 film 6 on the SiN film 3 used as a mask and the p-type polycrystalline 81 layer 5 below it are selectively removed, and then the SiN mask 3 is removed.
remove. In this way, the single crystal Si region on which the intrinsic base region is to be formed is exposed.

As shown in FIG. 1(E), p-type S
grow i A single-crystal p-type Si layer 7 grows in the intrinsic base region exposed on the surface of the single-crystal Si layer. Si deposited elsewhere becomes a polycrystalline Si layer 7a.

Since molecular beam epitaxial growth (MBE) is highly directional, the single crystal 31 region 7 grows directionally on the exposed single crystal Si surface. If the side walls of the opening are upright, most growth from the side walls can be prevented.

It is in close contact with the polycrystalline Si layer 5 in the lateral direction. No epitaxial growth occurs on the SiO2 film 6, and a polycrystalline Si layer 7a is deposited. Since the directivity is good, the polycrystalline Si layer 7a is prevented from protruding laterally at the opening.

The single crystal Si layer 7 is grown by MBE to a thickness of about 1100 nm, for example.

Next, as shown in FIG. 1(F), single crystal s1 and polycrystal S
Polycrystalline Si is selectively removed by utilizing the difference in etching characteristics of i. For example, etching is performed using a hydrofluoric acid-nitric acid mixture to remove the polycrystalline Si layer 7a. At this time, the single-crystal S1 layer 7 is resistant to the etching solution, so it is hardly etched.

The single crystal Si layer 7 can be made p-type by adding diborane as a doping residue during MBE growth, or by adding p-type impurities such as boron by ion implantation after growing the 81 layer of non-doped 1. to make it p-type. This p-type layer 7 becomes an intrinsic base region, and the impurity concentration is selected to be, for example, about 5×IQ18cm+-3.
A p-type Si epitaxial layer 7 is electrically connected to the polycrystalline Si layer 5, and the intrinsic base region is connected to the extrinsic base region.

Next, as shown in FIG. 1(G), a 5iOZ film 6 is applied to the entire surface.
a to a thickness of approximately 400 nm.

Then, as shown in Figure 1 () (>, for example, C) (F
3-gas reactive ion etching is performed to perform directional etching to etch away the deposited 5102M6a, leaving only the portion on the opening side wall of the base S j O2g 6 and removing the other portion. This r#J wall soil sio
2M reduces the diameter of the opening.

Next, as shown in FIG. 1(I), a heavily doped n-type polycrystalline Si layer 8 is deposited to a thickness of, for example, about 200 nm. In addition, in the case of adding about 1021 ゛3 As ions to this polycrystalline Si layer, for example, impurities may be added into the polycrystalline Si layer at the same time as the growth or by ion implantation after the growth. .

Next, as shown in FIG. 1 (J), the n-type polycrystalline S
The i-layer 8 is patterned and an n-type polycrystalline Si layer 8a with a thickness of about 200 nm is left on the opening of the SiO2 film 6b, and heat treatment is performed at about 1000°C for several seconds to several tens of seconds. The impurities are removed from the polycrystalline Si layer 8a.
An emitter region 9 is formed by diffusing into the molded t-layer 7.

Next, as shown in FIG. 1(K), 5i02II! 6
An opening is formed in b to form a region for contacting an electrode to the external base region 5.

Next, as shown in FIG. 1(L), the n-type multi-connection 881 layer 8a
An emitter electrode 10a, a base electrode 10b, and a collector electrode 10c made of aluminum are formed on the external base region 5 exposed in the opening of the upper-5i02 film 6b and on the surface of the n medium-sized Si substrate 1, respectively. .

In this way, a bipolar transistor is formed in which the extrinsic base region contacts the intrinsic base region from the lateral direction.

Although the case of an npn bipolar one-herald transistor has been described, it will be obvious to those skilled in the art that a pnp bipolar transistor can also be manufactured using the same process.

Although the present invention has been described above in accordance with the embodiments, the present invention is not limited to these examples. For example, various modifications,
It will be obvious to those skilled in the art that improvements, combinations, etc. are possible.

Effects of the Invention As described above, the present invention provides a method for manufacturing a semiconductor device that allows easy formation of contacts from the lateral direction of the intrinsic base region to the external base region of polycrystalline Si.

As a result, it becomes easy to create a high-speed, large-scale circuit device or a large-capacity memory device.

[Brief explanation of the drawing]

FIGS. 1(A) to (L) are cross-sectional views for explaining the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2(A) and (B) are structural examples of bipolar transistors. FIG. 2(A) is a cross-sectional view showing an upper base contact type bipolar transistor;
Figure (B) is a cross-sectional view showing a lateral base contact type bipolar transistor, and Figures 3 (A) to (C) are cross sections for explaining a method of manufacturing a lateral base contact type bipolar transistor using conventional technology. It is a diagram. In the figure, 4.6 n+ type Si substrate n type Si epitaxial layer SiN film 5i02 film ρ type polycrystalline Si layer p type ret layer n type polycrystalline Si layer emitter region electrode collector region insulating region base region intrinsic base region outside Base region Emitter region Protective film Emitter electrode Base electrode Collector electrode Mask (A)! ! Selective etching CB)! I Selective acid oxidation (C) Poly-Si layer, oxide film deposition Figure 1 (Part 1) (G) Si02 deposition (H) Directional etching (1) Polycrystalline Si deposition 8: N-type poly-Si layer (D> selection) Etching (E) MBIJ length (F) Polycrystalline Si etching 7: p-type t layer (J) emitter formation (K) base contact region opening 9: emitter region (K) t, scraping 10: mask ( A) Intrinsic base shaping (A) Upper base contact type (B) Bias sputtering (B) Lateral base contact type (C) Emitter region, Ti shadow formation conventional technology Figure 3 Procedure amendment (method) [1. Incident Indication of 1990 Patent Application No. 159304 (J) Emitter formation 2, Name of invention Method for manufacturing semiconductor devices 3, Person making amendment Address related to the case (522) Name

Claims (2)

[Claims] (1) A single-crystal Si surface region on which an intrinsic base is to be formed, an external base region formed to surround the surface region, and an insulating film formed thereon.
performing molecular beam epitaxial growth of Si on the substrate, growing single crystal Si connected to the external base region on the single crystal Si surface region and polycrystalline Si on the insulating film; A method of manufacturing a semiconductor device, comprising a step of selectively etching away, and comprising an intrinsic base made of the single crystal Si. (2) The single-crystal Si surface region has a first conductivity type and is exposed within an opening of a lower insulating film, and the external base is disposed on the lower insulating film and has a first conductivity type. reverse second
It is formed of polycrystalline Si having a conductivity type, and the Si
2. The method of manufacturing a semiconductor device according to claim 1, wherein said molecular beam epitaxial growth grows second conductivity type single crystal Si on said single crystal Si surface region.