KR930011282A - Single Polycrystalline Silicon Bipolar Device Structure and Fabrication Method with Self-aligned Silicide Electrode - Google Patents
Single Polycrystalline Silicon Bipolar Device Structure and Fabrication Method with Self-aligned Silicide Electrode Download PDFInfo
- Publication number
- KR930011282A KR930011282A KR1019910021081A KR910021081A KR930011282A KR 930011282 A KR930011282 A KR 930011282A KR 1019910021081 A KR1019910021081 A KR 1019910021081A KR 910021081 A KR910021081 A KR 910021081A KR 930011282 A KR930011282 A KR 930011282A
- Authority
- KR
- South Korea
- Prior art keywords
- polycrystalline silicon
- oxide film
- electrode
- nitride film
- base
- Prior art date
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 title claims abstract 8
- 229910021332 silicide Inorganic materials 0.000 title claims abstract 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract 8
- 238000002955 isolation Methods 0.000 claims abstract 14
- 150000004767 nitrides Chemical class 0.000 claims abstract 13
- 238000001312 dry etching Methods 0.000 claims abstract 9
- 238000000151 deposition Methods 0.000 claims abstract 7
- 229910052796 boron Inorganic materials 0.000 claims abstract 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract 4
- 230000008021 deposition Effects 0.000 claims abstract 4
- 239000012535 impurity Substances 0.000 claims abstract 4
- 238000009826 distribution Methods 0.000 claims abstract 3
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 claims abstract 2
- 238000011084 recovery Methods 0.000 claims abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052723 transition metal Inorganic materials 0.000 claims 3
- 150000003624 transition metals Chemical class 0.000 claims 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 claims 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims 2
- 239000001301 oxygen Substances 0.000 claims 2
- 229910052760 oxygen Inorganic materials 0.000 claims 2
- 238000000206 photolithography Methods 0.000 claims 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- HJELPJZFDFLHEY-UHFFFAOYSA-N silicide(1-) Chemical compound [Si-] HJELPJZFDFLHEY-UHFFFAOYSA-N 0.000 claims 2
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 239000012298 atmosphere Substances 0.000 claims 1
- -1 boron ions Chemical class 0.000 claims 1
- 238000010292 electrical insulation Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 claims 1
- 239000000843 powder Substances 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 206010010144 Completed suicide Diseases 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
본 발명은 정보의 고속처리를 요하는 시스템에 사용되는 바이폴라 소자구조 및 제조방법에 관한 것으로서, 종래의 바이폴라 소자의 구조는 다결정 실리콘 전극들간의 트렌치 격리영역을 정의하기 위한 측벽 질화막을 에미터다결정 실리콘 전극의 안쪽에 정의함으로써 공정 신뢰도 측면에서 두가지의 문제점을 가지고 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar device structure and a manufacturing method used in a system requiring high-speed processing of information. The structure of a conventional bipolar device includes an emitter polycrystalline silicon having a sidewall nitride film for defining trench isolation regions between polycrystalline silicon electrodes. Defining the inside of the electrode has two problems in terms of process reliability.
첫째로 P+다결정 실리콘의 선택적 건식식각을 위한 다결정 실리콘 산화막 성장시 다결정 실리콘 내에서의 붕소 역산화에 의한 베이스-컬렉터 접합 깊이의 불균일성 활성 및 비활성 베이스 영역을 형성하기 위한 붕소의 동시 주입 등을 베이스 접합깊이와 불순물 분포의 제어를 곤란하게 한다.Firstly, the base bonding is performed by the simultaneous implantation of boron to form the non-uniform activity of the base-collector junction depth by boron back oxidation in the polycrystalline silicon and the formation of the inactive base region during the growth of the polycrystalline silicon oxide layer for the selective dry etching of P + polycrystalline silicon. Control of depth and impurity distribution becomes difficult.
둘째로 소자의 전체 크기를 결정하는 P+다결정 실리콘의 선행 정의는 각 전극간의 전기적 격리를 위한 다결정실리콘의 건식식각시 식각종점의 결정을 곤란하게 한다.Secondly, the prior definition of P + polycrystalline silicon, which determines the overall size of the device, makes it difficult to determine the etching end point during dry etching of polycrystalline silicon for electrical isolation between electrodes.
또한 증착 산화막에 의한 트렌치 격리영역의 목구공정은 다결정 실리콘 에미터 표면의 손상을 가져올 수 있다. 본 발명은 각 다결정 실리콘 전극간의 트렌치 격리영역을 정의하기 위한 측멱 질화막을 에미터 다결정 실리콘전극의 바깥쪽으로 형성함으로써, 다결정 실리콘의 식각종짐의 결정을 용이하게 하고, 또한 에미터 다결정 실리콘 전극상에 질화막과 N+다결정 실리콘을 이용함으로써 트렌치 격리영역의 복구를 위한 증착산화막의 건식식각의 종점의 절정과 베이스 영역에서의 불순물 분포의 제어를 용이하게 하고, 또한 다결정 실리콘 전극상에 실리사이드가 선택적으로 자기 정렬되는 구조척 개선을 통하여 공정 신뢰도와 바이폴라 소자의 성능을 향상시키도록한 것이다.In addition, the necking process of the trench isolation region by the deposition oxide may damage the surface of the polycrystalline silicon emitter. The present invention forms a side nitride film for defining the trench isolation region between each polycrystalline silicon electrode on the outside of the emitter polycrystalline silicon electrode, thereby facilitating the determination of etch termination of the polycrystalline silicon, and on the emitter polycrystalline silicon electrode. The use of a nitride film and N + polycrystalline silicon facilitates the climax of the dry etching end point of the deposited oxide film for the recovery of the trench isolation region and the control of the impurity distribution in the base region, and the selective suicide of the silicide on the polycrystalline silicon electrode. Through improving the structural scale, the process reliability and the performance of the bipolar device are improved.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 의하여 완성된 단일 다결정 실리콘 바이폴라 소자의 단면도.2 is a cross-sectional view of a single polycrystalline silicon bipolar device completed in accordance with the present invention.
제3도의 (a) 내지 (f)는 본 발명에 의한 단일 다결정 실리콘 바이폴라 소자의 제조 공정도.(A)-(f) of FIG. 3 is a manufacturing process chart of the single polycrystal silicon bipolar element by this invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910021081A KR950001147B1 (en) | 1991-11-25 | 1991-11-25 | Manufacturing method of polysilicon bipolar device with self aligned silicide electrodes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910021081A KR950001147B1 (en) | 1991-11-25 | 1991-11-25 | Manufacturing method of polysilicon bipolar device with self aligned silicide electrodes |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930011282A true KR930011282A (en) | 1993-06-24 |
KR950001147B1 KR950001147B1 (en) | 1995-02-11 |
Family
ID=19323390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910021081A KR950001147B1 (en) | 1991-11-25 | 1991-11-25 | Manufacturing method of polysilicon bipolar device with self aligned silicide electrodes |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950001147B1 (en) |
-
1991
- 1991-11-25 KR KR1019910021081A patent/KR950001147B1/en not_active IP Right Cessation
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Publication number | Publication date |
---|---|
KR950001147B1 (en) | 1995-02-11 |
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