JPS6140057A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PURPOSE:To improve performance of a semiconductor device at a high rate or a high frequency, by reducing a base resistance using a laminated structure of a non-single-crystal Si film and a metal silicide film as a base taking out electrode. CONSTITUTION:After an N<+> type buried region 2 is formed in a P type Si substrate 1, an N type epitaxial layer 3 and a field oxidation film 4 are formed. Next, a polycrystal Si film which has been patterned and doped with B is deposited, and moreover an MoSi2 film is deposited thereon. Next, over the entire face, an oxidation film 8 is deposited. Next, using a photo resist pattern 9 formed as a mask, the films 8-6 are etched away to form a base taking out electrode 10. Thereafter, B which is being doped in the films 7, 6 is diffused with heat-treatment to form a P<+> type external base region 12. Moreover, by implanting B, a P type active base region 13 is formed. After an oxidation film 14 is deposited over the entire face, the oxidation film 14' on the side walls of the electrode 10 is left with anisotropic etching. Next, an N<+> type emitter region 16 is formed in the region 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a transistor for a bipolar type high-speed logic operation or an analog operation circuit in a high frequency region, and a manufacturing method thereof.゛ [Technical background of the invention and its problems] A 9-ipolar type transistor operates in a high-speed or high-frequency region, using a substrate with shallow junction formation by ion implantation, an embedded oxide film, a grooved structure, etc. - We have achieved improved performance by reducing the parasitic capacitance between the collectors, and through the development of fine patterning and self-alignment technology). Ta.

For example, Japanese Patent Publication No. 57-41826 discloses a technique for reducing the space-collector capacitance by employing a lead-out space electrode made of polycrystalline silicon.

In addition, in Japanese Patent Application Laid-open No. 57-53979, polycrystalline silicon is used as a diffusion source for forming a pace electrode and an external paste, and after forming an opening for forming an emitter and an active paste, thermal diffusion is performed. By forming an external space region, and further forming a submicron oxide film by thermal oxidation on the side wall of the polycrystalline silicon facing the opening, an active space region and an emitter region are formed in a self-lined manner. Techniques for reducing pace resistance are disclosed. A technique similar to this Japanese Patent Application Publication No. 57-53979 was published in Japanese Patent Publication No. 57-53979.
6-4457, JP 57-186360, JP 57-186359, JP 57-18
It is also disclosed in Report No. 8872. In addition, the special public
In Japanese Patent Publication No. 266'30, Japanese Patent Publication No. 55-27469, and Japanese Patent Publication No. 57-32511, a self-alignment technique using steps such as oxide films was introduced in forming a polycrystalline silicon paste electrode. , techniques for reducing pace-collector capacity have been developed. .

In these conventional techniques, it is considered that the reduction of parasitic capacitance and the reduction of resistance of the space region in the substrate have been almost satisfactorily achieved. However, the layer resistance value of a paste extraction electrode made of polycrystalline silicon is about 3 to 5 times higher than that of a case where the same amount of impurities is added to single crystal silicon.

For this reason, a conventional pace extraction electrode made of polycrystalline silicon has a value of about 50 to 500 Ω/mouth.

On the other hand, for example, a report on the relationship between the ECL circuit Tatsuki Deis constant and the sensitivity coefficient (Taizai, Yamazaki: Ultra-high-speed ECL
Development and mass production of the Logic HD100K series, Hitachi Review, 64:P, 59-62. According to t9sz), pace resistance rbb' occupies a large weight in those that require high-speed operation. Therefore, lowering the layer resistance value of the paste extraction electrode is one of the major factors in improving the performance of the transistor. -As a technique for lowering the resistance value of the pace extraction electrode, the so-called PSA or A-PSA7' process (Po1
ySi Self-Aligned Process)
(L'Nakaghiba at al, 'A
n Advanced PEA 'Teahniilo
g) rfor high-sp@ed Bipola
rLSl,', IEgE, Vol.

ED-27, pp, 1390-1394.1980)
It has been known. In this technology, the pace extraction electrode is white 2
It is reduced to Ω/mouth. However, this technique is possible in a process that does not involve high-temperature heat treatment after emitter formation, and is applied only to a portion of the polycrystalline silicon film from which the paste region is extracted. Since the electrode and the emitter region are not separated by a submicron insulating film, it is difficult to sufficiently lower rbb'.

[Purpose of the invention]

(1) To provide a bipolar semiconductor device that has good performance in high-speed or high-frequency ranges by reducing pace resistance, and a method for manufacturing the same.

[Summary of the Invention] A semiconductor device according to the first invention of the present application includes a low concentration diffusion layer formed on the surface of a first conductivity type semiconductor substrate (for example, an N-type epitaxial layer on a Pi silicon substrate) and this low concentration diffusion layer. a second conductivity type high concentration diffusion layer formed in contact with the second conductivity type high concentration diffusion layer; and an extraction electrode consisting of a non-single crystal silicon film and a metal silicide film formed by sequentially stacking on the second conductivity type high concentration diffusion layer; , comprising an insulating film formed on the side of the extraction electrode, and a high concentration diffusion layer of the first conductivity type formed in the low concentration diffusion layer of the second conductivity type. be.

According to the Hiko semiconductor device, since a laminated structure of a non-single-crystal silicon film and a metal silicide film is used as the paste extraction electrode, the layer resistance can be significantly reduced, and the paste resistance can be reduced. can be achieved. Therefore, performance in high speed or high frequency ranges can be improved.

Further, the method for manufacturing a semiconductor device according to the second invention of the present application includes the method for manufacturing a semiconductor device according to the first invention.
A step of sequentially stacking a non-single crystal silicon film, a thin metal silicide film, and a metal silicide film on a part of a semiconductor substrate of a conductive type, and selectively doping impurities of a second conductive type into these 74 turns. A process of selectively etching a part of these patterns to form an extraction electrode and exposing a part of the semiconductor substrate, and a process of diffusing impurities from the extraction electrode by heat treatment. A step of forming a second conductivity type high concentration diffusion layer, a step of forming a second conductivity type low concentration diffusion layer by doping the exposed substrate with a second conductivity type impurity, and a step of forming an insulating film on the entire surface. After the deposition, etching is performed by anisotropic etching and etching to leave an insulating film on the side wall of the extraction electrode, and high concentration diffusion of a first conductivity type is performed in the low concentration diffusion layer of the second conductivity type. The method is characterized by comprising a step of forming a layer.

According to this method, a paste extraction electrode having a laminated structure of non-single crystal silicon and metal silicide is used also as a diffusion source, and moreover, an anisotropic process is performed.

Since a submicron insulating film is formed on the side wall of the extraction electrode by etching, a high-concentration diffusion layer of the second conductivity type (external pace region), a low-coal diffusion layer of the second conductivity type (active pace region) and High concentration diffusion layer of first conductivity type (emitter region)
can be formed using Selfa Line and can be made extremely fine. Therefore, it is possible to easily manufacture the bipolar semiconductor device of the first invention of the present application in which the pace resistance is significantly reduced by four times (by reducing the layer resistance of the pace extraction electrode and the resistance value of the active pace region). .

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described together with manufacturing methods shown in FIGS. 1 to 8.

First, N+W is selectively applied to a part of the P-type silicon substrate 1!
! ! After forming the embedded region 2, an N-type epitaxial layer 3 is grown over the entire surface. Next, a selective oxidation method was used to obtain a film with a thickness of 60 mm.
A field oxide film 4 of 00 to 1ooooX is formed.

. Subsequently, a part of the epitaxial layer 3 surrounded by the field oxide film 4 is doped with N type impurities to form an N+ type collector contact region 5. Next, LPCVD
An impurity-free polycrystalline silicon film 6 with a thickness of 5,000× is deposited on the entire surface by the method, and a MoS 12 film 7 with a thickness of 3,000× is further deposited on the entire surface by the horn-and-four-vine method (the first
(Illustrated) Next, the MO812 film 7 and the polycrystalline silicon film 6 are sequentially turned by chemical dry etching (CDI) or reactive ion etching (RIE). Next, these NoJ? Selective acceleration energy for turns 40-50 keys, dose 10
Ron is ion-implanted under the condition of 15-10"cm-2. Then, a film thickness of 3000-400cm is deposited on the entire surface.
An oxide film 8 is deposited (as shown in FIG. 2).

Next, after forming a photoresist pattern 9 covering areas other than the active paste forming region, the 6 cvo oxide film 8 is etched by RIE using SF6 using this as a mask.
Next, perform RIE using BCt〆t2) Mo8
12 film and the polycrystalline silicon film 6 are etched to form a paste extraction electrode IO. Furthermore, considering these variations in film thickness, the thickness of the epitaxial layer 3 is 0.1 to 0.2μ.
Then, after removing the photoresist cutter 9, the damage caused to the surface of the epitaxial layer 3 caused by RIB is removed by alkaline etching, etching, and etching (as shown in FIG. 3). Next, thermal oxidation is performed on the surface of the epitaxial layer 30 (with a thickness of 500X).
A thermal oxide film 11 is formed. Next, 1000-110
Heat treatment is performed at 0° C. to diffuse doped zolon into ItsXMoSi□gv and polycrystalline silicon film 6 to form P+ type external space region 12. Furthermore, acceleration energy 4
A P'' type active space region 13 is formed by ion-implanting zolon under the conditions of 0 keV and a dose of about 1014/112 (as shown in FIG. 4).

Next, a CVD oxide film 14 having a thickness of 3,000 to 500 mm is deposited on the entire surface. Subsequent heat treatment is performed at 00-1000 DEG C. to anneal the CVD oxide film 14 and the active region 13 (as shown in FIG. 5). Subsequently, the CVD oxide film 14 and thermal oxide film 11 are processed and etched by RIB using SF6, and the CVD oxide film 8 and Mo
A CVD oxide film 14' is left on the side wall of the lead-out electrode 10 made of 812 Remove (as shown in Figure 6).

Next, after depositing a polycrystalline silicon film on the entire surface, an acceleration energy of 40 to 50 keV and a dose of 1015 to 1 are applied.
Phosphorus, arsenic, or both phosphorus and arsenic are ion-implanted under the condition of Q"/1wr2. Next, the polycrystalline silicon film is turned to form a polycrystalline silicon film pattern 15. ℃ for several tens of minutes to diffuse impurities from the polycrystalline silicon film/JP turn 15 to form an N+ type emitter region 16 (as shown in FIG. 7).Subsequently, CvD oxide film 80 is deposited at a predetermined position. A contact hole is selectively formed by etching. Next, wiring gold and metal are deposited on the entire surface, and then turning is performed to form an emitter electrode 17, a pace electrode 18, and a collector electrode 19 to form a ζNPN bipolar transistor. (Illustrated in Figure 8). Subsequently, after depositing a passivation film on the entire surface, final steps such as surface stabilization are performed.

In the NPN bipolar transistor shown in FIG. 8, the paste extraction electrode 10 has a laminated structure of the polycrystalline silicon film 6 and the Mo812 film 7 that can withstand high-temperature heat treatment. I can do it. For example, when using a MoSi□ film with about 3000 lines, 3 to 4V
The value of the electrode can be #1150 to 1/200 of that of the case where a polycrystalline silicon film is used as an electrode.

Further, in the process shown in FIG. 4, an external space region 12 is formed using the extraction electrode 10 as a spreading source, and an active space region is formed by ion implantation using the extraction electrode 10 (and the CVD oxide film 8 thereon) as a mask. 13 is formed, and then a Zabumicron CVD oxide film 14' is formed on the side wall of the extraction electrode 10 using the knee RIB method shown in FIGS. -N15 to AJ+
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Since the diameter is 1°, these regions can be formed very finely with self-alignment. Therefore, the pace area (contribution of the active pace area) in the substrate can be reduced.

Therefore, in devices that require high-speed operation, the maximum sensitivity/resistance rbb' can be reduced to about 1/10 or less than conventional values, and a performance improvement of about 20 cm can be expected. .

Note that when the Mo81z film and the silicon substrate are brought into direct contact, a Schottky contact will be formed unless the surface concentration on the silicon substrate side is as high as about 1020. However, in the structure of the present invention, the polycrystalline silicon Since there are two films and 71 layers, good ohmic contact can be achieved. Furthermore, since the polycrystalline silicon film exists under the ζMo5t film, it is possible to prevent punch-through caused by silicon in the shallow junction of the substrate being sucked up into the MoSi film.

In the above embodiment, a Mo5t film was used as the metal silicide film constituting the pace extraction electrode, but the present invention is not limited to this, and other films such as Ti1l□ film and WS12 film, which exhibit sufficiently lower layer resistance than impurity-doped polycrystalline silicon, Like polycrystalline silicon, it has the property of being able to serve as a diffusion source.
The same effect as in the above embodiment can be obtained by using silicide that does not change or has a low degree of alteration by high-temperature heat treatment at 000° C. or higher.

' Also, in the above embodiment, the emitter and recess regions are formed using a polycrystalline silicon film as a diffusion source, but the emitter and recess regions may be formed by ion implantation. However, if ion implantation is used, it may be difficult to perform processing before electrode formation and to form a diffusion film, so it is desirable to use polycrystalline silicon as a diffusion source.

Further, in the above embodiment, the polycrystalline silicon film was doped with N-type impurities by ion implantation, but a polycrystalline silicon film doped with the same impurity may also be formed by LPCVD. . Note that when the N-type impurity is arsenic only, the diffusion coefficient is smaller than that of phosphorus, so when the impurity contains phosphorus or phosphorus and arsenic, it also has a high temperature of 900 to 100.
It is desirable to carry out the diffusion treatment at 0°C.

[Effects of the Abolition of Ming]

As detailed above, according to the present invention, there is provided a bipolar half-circle that has good performance in high-speed or high-frequency regions. It is possible to provide a method that allows for the production of...

[Brief explanation of the drawing]

FIGS. 1 to 8 are cross-sectional views showing manufacturing steps for obtaining an NPN bipolar transistor according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... pg silicon substrate, 2... N+W buried region, 3... Nu epitaxial layer, 4... field oxide film, 5... N+ type collector contact region, 6...
...Polycrystalline silicon film, 7...MOSi2 film, 8...
・CVD oxide film photoresist pattern, 10
...Pace extraction electrode, 11'...Thermal oxide film, 12
... External pace area, 13... Active pace area, 1
4, 1a'...CVD oxide film, 15...4 turns of polycrystalline silicon film, 16...N+ type emitter region, 1
7...Emi electrode, 18...Pace electrode, 19.
...Collector electrode. Applicant's agent Patent attorney Suzue Takehiko Condolences 1 Figure 4'

Claims (4)

[Claims] (1) a low concentration diffusion layer of a second conductivity type formed on the surface of a semiconductor substrate of a first conductivity type; a high concentration diffusion layer of a second conductivity type formed in contact with the low concentration diffusion layer; an extraction electrode made of a non-single-crystal silicon film and a metal silicide film sequentially laminated on a high concentration diffusion layer of a conductivity type; an insulating film formed on a side wall of the extraction electrode; and an insulating film formed on a side wall of the extraction electrode; 1. A semiconductor device comprising: a first conductivity type high concentration diffusion layer formed within a low concentration diffusion layer. (2) The metal silicide constituting the extraction electrode is MoSi
2. The semiconductor device according to claim 1, wherein the semiconductor device is one of TiSi_2, TiSi_2, and WSi_2. (3) A step of forming a non-single crystal silicon film pattern doped with a second conductivity type impurity and a metal silicide film pattern laminated thereon on a part of the first conductivity type semiconductor substrate, and these patterns. A step of selectively etching a part of the lead-out electrode to expose a part of the semiconductor substrate, and a step of diffusing impurities from the lead-out electrode by heat treatment to form a second conductivity type high concentration diffusion layer. a step of doping the exposed substrate with a second conductivity type impurity to form a second conductivity type low concentration diffusion layer; and a step of depositing an insulating film on the entire surface, etching it by anisotropic etching, and removing the a step of leaving an insulating film on the side wall of the electrode;
1. A method of manufacturing a semiconductor device, comprising: forming a first conductivity type high concentration diffusion layer within a conductivity type low concentration diffusion layer. (4) After sequentially stacking a non-single-crystal silicon film and a metal silicide film, pattern them, and then ion-implant impurities of the second conductivity type to form the non-single-crystal silicon film pattern and metal silicide film pattern. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is laminated.