JP3070209B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in isolation between high frequency signals between elements in a monolithic semiconductor integrated circuit.

[0002]

2. Description of the Related Art Hitherto, as an example of an insulating isolation structure between elements of a monolithic semiconductor integrated circuit, there is a method called dielectric isolation or trench isolation. Dielectric isolation method or is deposited thick polycrystalline silicon, there is a drawback that it must be polished away most of the silicon substrate. or,
In the trench isolation method, even if the horizontal isolation is good, the isolation in the direction perpendicular to the main surface of the substrate is p.
An n-junction must be used, which has drawbacks based on the pn-junction isolation method.

[0003] To improve these drawbacks, there is known a technique in which a trench isolation method is improved (Japanese Patent Application Laid-Open No. 61-59852). In this method, two single-crystal silicon substrates are bonded together with an insulating film interposed therebetween, and a separation groove is formed on one of the single-crystal silicon substrates from the surface to the insulating film. A film is formed, and polycrystalline silicon not doped with impurities is filled in the isolation trench in which the insulating film is formed. This method
Since the elements are also separated by the insulating film in the direction perpendicular to the main surface of the silicon substrate, there is an advantage that the entire periphery of each element is separated by the insulating film.

[0004]

However, the above-mentioned Japanese Patent Application Laid-Open
In the structure disclosed in JP 61-59852 A, each element is insulated DC by the separation groove, but the separation groove acts as a stray capacitance between the elements, and a high-frequency signal propagates to an adjacent element.
There has been a problem that a noise failure occurs in an adjacent element or a malfunction occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to completely isolate elements from one another in a high frequency band in a semiconductor integrated circuit.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate;
A buried insulating film formed on the buried insulating film;
And a semiconductor layer of the first conductivity type.
In the semiconductor integrated circuit in which is formed, the element of the semiconductor layer
Embedded from the surface of the semiconductor layer to surround the formation area
The isolation groove formed to reach the insulating film and the side wall of the isolation groove
Is formed, a sidewall insulating the insulating component away a side surface of the element formation region
A second conductivity type which is filled in the film and the isolation trench and which is opposite to the semiconductor layer
Of and a groove filling portion consisting of a semiconductor, the groove filling portion is doped with an impurity to a concentration 1 × 10 ¹⁶ / cm ³ or more, the groove
In the filling portion, the semiconductor layer and the groove filling portion form a pn junction.
Constant potential is applied so that reverse bias occurs when
It is characterized by that. Further, the configuration of the second invention is a
The constant potential applied to the filling part is the ground potential.
Sign. In a third configuration of the invention, the semiconductor substrate has an
A source potential.

[0007]

The respective element formation regions formed in the semiconductor layer of the first conductivity type are buried in a direction perpendicular to the main surface of the semiconductor layer (vertical direction) by a buried insulating film , and are formed in a direction parallel to the main surface. In the (lateral direction), it is completely insulated and separated in direct current by the side wall insulating film formed on the side wall of the separation groove.

On the other hand, the first conductive type semiconductor layer is formed in the isolation groove.
Made of a semiconductor of the second conductivity type opposite to
It is formed by filling a groove filling portion doped to 10 ¹⁶ / cm ³ or more. This groove filling portion, conductive there by impurity doping is, a constant potential is applied. This result
As a result, each element is filled with the sidewall insulating film formed in the isolation trench.
A stray capacitance with the filling portion is formed, and there is no stray capacitance directly connecting each element. Accordingly, high-frequency coupling between elements is eliminated, and a high-frequency signal is prevented from leaking to an adjacent element and causing noise interference. The constant potential applied to the groove filling part is
Even if a pn junction is formed with the semiconductor layer, the reverse
Because it is set to a constant potential that becomes the bias,
There is no leakage even if a pinhole occurs. Attached to groove filling part
If the given potential is the ground potential, it is formed in the separation groove
Inner surface of the formed sidewall insulating film (the groove filling portion is filled)
Side) is at ground potential.

[0009]

The present invention has a buried insulating film and a side wall insulating film surrounding each element forming region of the semiconductor layer of the first conductivity type. Insulated and separated. In addition, a sidewall insulating film is interposed in an isolation groove formed around each element formation region, and a first conductivity type semiconductor is formed.
Impurity in the semiconductor of the second conductivity type opposite to the layer to a predetermined concentration or more
And doped groove filling portion is filled with the groove filling portion
Has a constant potential applied to the semiconductor integrated circuit.
Insulation in the high-frequency region between the devices is improved. Ma
And, if it is connected groove filling portion to ground, a high-frequency signal of each element for leaks to ground, it does not propagate to the adjacent element regions. Therefore, the isolation between the elements in the semiconductor integrated circuit in the high frequency region is further improved.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to a specific embodiment. FIG. 1 is a sectional view showing a configuration of a semiconductor integrated circuit according to a specific embodiment of the present invention, and FIG. 2 is a plan view thereof. Hereinafter, a method of manufacturing the present apparatus will be described with reference to FIGS. As shown in FIG. 3, the main surface 20a of the second single-crystal silicon substrate 20 (semiconductor substrate) is mirror-polished, and then the main surface 20a is thermally oxidized to form the SiO ₂ layer 1 ( buried insulating material). Film ). Next, after the main surface 10a (bonding surface) of the first single crystal silicon substrate 10 (semiconductor layer) is mirror-polished, the main surface 10a and the main surface 20a of the second single crystal silicon substrate 20 are separated. It is heated to 200 ° C. or more in a sufficiently clean atmosphere to make it adhere. As a result,
As shown in FIG. 4, the second single crystal silicon substrate 20 and the first single crystal silicon substrate 10 were joined with the SiO ₂ layer 1 interposed therebetween.

Next, as shown in FIG. 5, grids are formed around the element regions 6a and 6b where elements such as transistors are formed in the first single crystal silicon substrate 10 in a later step. A groove 3 is formed. The isolation groove 3 was formed to have a width of 2 μm and a depth of 8 μm by anisotropic etching such as photolithography and reactive ion etching until reaching the SiO ₂ layer 1.

[0012] Next, as shown in FIG. 6, the surface of the first single crystal silicon substrate 10 is thermally oxidized, the oxide film 4 (the side wall insulation made of SiO ₂ having a thickness of 5000Å on the inner surface of the isolation trench 3
Film ) was formed. Next, as shown in FIG. 7, polycrystalline silicon is deposited on the surface of the first single-crystal silicon substrate 10 so that the polycrystalline silicon wall 5 (groove)
(Filled part) was formed. In the growth process of the polycrystalline silicon, oxidation film 4 is in direct contact with that element forming region 6a, 6
Doping with an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or more so that polycrystalline silicon has a conduction type (p-type conduction or n-type conduction) opposite to a conduction type (b-type conduction or p-type conduction) such as b Was done.

Next, the polycrystalline silicon 50 and the oxide film 40 which have protruded from the separation groove 3 are polished and removed, whereby the structure shown in FIG.
Was formed. Next, elements such as transistors were formed in the element forming regions 6a and 6b by a normal integrated circuit forming process. Here, 7 is a base diffusion layer, 8 is an emitter diffusion layer, and 9 is a collector diffusion layer.
Reference numeral 30 denotes an interlayer insulating film made of BPSG. Reference numeral 31 denotes an aluminum electrode, which is in ohmic contact with the base diffusion layer 7, the emitter diffusion layer 8, the collector diffusion layer base 9, and the like through a contact hole formed in the interlayer insulating film 30.

The polycrystalline silicon wall 5 having the above structure is formed continuously in one integrated circuit chip.
Then, at an arbitrary take-out position of the chip, in the same step as the step of forming the aluminum electrode 31 of each element, the chip is connected to the underlying polycrystalline silicon wall 5 via the contact hole formed in the interlayer insulating film 30. The extraction electrode 32 is formed. The extraction electrode 32 and the ground pad 33 are connected. The ground pad 33 is connected to the ground (ground) terminal of the lead pin by wire bonding.

In this embodiment, a buried layer 34 and a side wall diffusion layer 35 are provided. The buried layer 34 is formed by converting the first single crystal silicon substrate 10 to the second single crystal silicon substrate 20.
Formed before bonding to the side wall diffusion layer 35.
Are formed before the insulating film 4 is formed on the inner surface of the separation groove 3. These buried layer 34 and sidewall diffusion layer 3
The presence of 5 does not prevent the effect of the present invention.

With the above configuration, each of the element forming regions 6a,
6b and the like are completely DC-insulated and separated from other element formation regions by the SiO ₂ layer 1 in the vertical direction and by the insulating film 4 formed on the inner surface of the isolation groove 3 in the horizontal direction. . In the semiconductor integrated circuit of this embodiment, the polycrystalline silicon wall 5 has conductivity by impurity doping, and is connected to the ground (ground). At the boundaries between the element forming regions 6a, 6b, etc., a floating capacitance is formed by the insulating film 4 interposed between the polycrystalline silicon wall 5 at the ground potential and the element forming regions 6a, 6b, etc. However, since one end of the stray capacitance is connected to the ground, propagation of a high-frequency signal between the element forming regions 6a, 6b and the like is suppressed. As a result, each element formation region 6
a, 6b and the like are completely insulated and separated from both DC and high frequency. Therefore, interference between adjacent elements is prevented.

FIG. 9 shows a device simulation result showing this effect. After the insulating film 4 is formed on the inner surface of the isolation groove 3, (A) the impurity concentration 1 ×
When it fills the polycrystalline silicon doped with 10 ²⁰ / cm ^3, which was the potential in the floating state, (B)
When the isolation trench 3 is filled with polycrystalline silicon not doped with an impurity and its potential is set to a floating state,
(C) When the isolation trench 3 is filled with SiO ₂ and its potential is set to a floating state, (D) Polycrystalline silicon doped with an impurity in the isolation trench 3 at a concentration of 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ^3. And the potential is set to the ground potential,
(E) The isolation trench 3 is filled with polycrystalline silicon doped with an impurity at a concentration of 1 × 10 ¹⁶ / cm ³ , and when the potential is set to the ground potential, (F) the isolation trench 3 is doped with the impurity at a concentration of 1 × 10 ¹⁸
/ Cm ³ polycrystalline silicon doped with a filling, when the potential of the ground potential, filled with polycrystalline silicon doped with impurities at a concentration of 1 × 10 ²⁰ / cm ³ to (G) isolation trenches 3, the Simulate the case where the potential is set to the ground potential.
Rations . In each case described above, when a step voltage was applied to one element formation region 6a, a voltage waveform appearing in the adjacent element formation region 6b was observed. FIG. 9 shows the waveforms of the above cases.

The following conclusions were obtained from the above simulation . (1) When the filling of the separation groove 3 is not grounded, the leakage of the high-frequency signal to the adjacent element is large. The degree is higher as the conductivity of the filler is higher. (2) When the filling of the separation groove 3 is grounded, the higher the conductivity of the filling, the smaller the leakage of the high-frequency signal to the adjacent element. (3) When the isolation trench 3 is filled with polycrystalline silicon doped with n or p-type impurities at a concentration of 1 × 10 ²⁰ cm ⁻³ and grounded, the structure disclosed in Japanese Patent Application Laid-Open No. 61-59852 is used. As compared with the conventional example (B), the amount of leakage of the high-frequency signal to the adjacent element is reduced by two digits or more. (4) When the polycrystalline silicon filling the isolation groove 3 is grounded, the impurity concentration of the polycrystalline silicon is 1 × 10 ¹⁶ / cm.
^In the case of ³ or more, the effect of suppressing and preventing the interference current by 10 times or more can be obtained as compared with the case where non-doped polycrystalline silicon is used.

In the above cases (A) and (G), experiments were actually conducted, and the above conclusions were confirmed. FIG. 10 is a waveform chart showing this. In the case of (G), it can be seen that the leakage of the high-frequency component is completely eliminated (completely buried in the noise of the measurement system).

Next, (D), (E), and (D) shown in FIG.
With respect to (F) and (G), the ratio r of the area of each curve (the magnitude of interference power × time) to the area of the curve in the case of (B) non-doped polycrystalline silicon and floating is determined.
The relationship between the ratio r and the impurity concentration was determined. The result is shown in FIG.
Shown in From FIG. 11, the impurity concentration of the polycrystalline silicon is 1
It can be seen that the leakage power of the high-frequency signal is reduced by more than one digit by grounding the polycrystalline silicon in the case of × 10 ¹⁶ cm ⁻³ or more, as compared with the case of non-doped polycrystalline silicon.

In the above embodiment, as the impurity doped into the polycrystalline silicon wall 5, an impurity whose polycrystalline silicon wall 5 has a conductivity type opposite to that of the element forming regions 6a and 6b is selected. As a result, even if a pinhole or the like occurs in the insulating film 4 formed on the inner surface of the isolation groove 3, a pn junction is formed between the element forming regions 6a, 6b and the like and the polycrystalline silicon wall 5. By using the semiconductor integrated circuit so that a reverse bias is applied to the pn junction, insulation from direct current is performed. Further, the effect of preventing leakage of a high-frequency signal is as follows:
As described above, as long as the n-junction is reverse biased.

If the insulating film 4 can be formed without generating a pinhole, the polycrystalline silicon wall 5 and the element forming region 6
Even if a, 6b, etc. are of the same conductivity type, the above-described effect of preventing leakage of high-frequency signals similarly occurs. Also,
Although the buried insulating film 1 and the side wall insulating film 4 are made of SiO ₂ , other insulating films such as Si ₃ N ₄ may be used.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor integrated circuit according to a specific example of the present invention.

FIG. 2 is a plan view of the semiconductor integrated circuit according to the embodiment.

FIG. 3 is an exemplary sectional view showing a manufacturing step of the semiconductor integrated circuit according to the embodiment;

FIG. 4 is a sectional view showing the manufacturing process of the semiconductor integrated circuit according to the embodiment.

FIG. 5 is a sectional view showing the manufacturing process of the semiconductor integrated circuit according to the same embodiment.

FIG. 6 is a sectional view showing the manufacturing process of the semiconductor integrated circuit according to the embodiment.

FIG. 7 is a sectional view showing the manufacturing process of the semiconductor integrated circuit according to the embodiment.

FIG. 8 is a sectional view showing the manufacturing process of the semiconductor integrated circuit according to the same embodiment.

FIG. 9 is a waveform diagram showing a result of simulating leakage of a high-frequency signal between elements.

FIG. 10 is a waveform chart showing the measurement of leakage between high-frequency signals between elements.

FIG. 11 is a characteristic diagram showing a relationship between a leakage amount of a high-frequency signal and an impurity concentration.

[Explanation of symbols]

10 ... the first silicon substrate (first conductivity type semiconductor layer) 20 ... second silicon substrate (semiconductor substrate) 3 ... isolation trenches 1 ... SiO ₂ layer (buried insulating film) 4: insulating layer (sidewall insulation film) 5 ... polycrystalline silicon walls (groove filling portion) 6a, 6b, 6c, 6d ... element forming region 32 ... extraction electrodes 33 ... ground pad

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-148852 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/76 H01L 21/762

Claims (3)

(57) [Claims] A semiconductor substrate formed on the semiconductor substrate;
Buried insulating film, and a first buried insulating film formed on the buried insulating film.
A semiconductor layer of a conduction type, and an element is formed on the semiconductor layer.
In the semiconductor integrated circuit, the semiconductor layer is formed so as to surround an element forming region of the semiconductor layer.
Formed from the surface of the semiconductor layer to the buried insulating film;
And a side surface of the element formation region formed on a side wall of the separation groove.
A side wall insulating film that insulates and separates the second conductive layer from the semiconductor layer,
A groove filling portion made of a semiconductor of a mold type, wherein the groove filling portion is doped with impurities to a concentration of 1 × 10 ¹⁶ / cm ³ or more, and the semiconductor layer and the groove filling portion are filled in the groove filling portion. Part is p
Constant potential so that reverse bias occurs when an n-junction is formed
A semiconductor integrated circuit, characterized in that a semiconductor integrated circuit is provided. 2. The method according to claim 1, wherein the constant potential applied to the groove filling portion is an arc potential.
The semiconductor device according to claim 1, wherein the semiconductor device has a ground potential.
Body integrated circuit. 3. An earth potential is applied to the semiconductor substrate.
The method according to claim 1 or 2, wherein
Semiconductor integrated circuit.