JP2668873B2 - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JP2668873B2 JP2668873B2 JP62067383A JP6738387A JP2668873B2 JP 2668873 B2 JP2668873 B2 JP 2668873B2 JP 62067383 A JP62067383 A JP 62067383A JP 6738387 A JP6738387 A JP 6738387A JP 2668873 B2 JP2668873 B2 JP 2668873B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- groove
- substrate
- memory device
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000003860 storage Methods 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims description 47
- 239000003990 capacitor Substances 0.000 claims description 14
- 239000010408 film Substances 0.000 description 25
- 239000010410 layer Substances 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体記憶装置に関し、特にシリコン等の半
導体基板表面に凹凸を設けて基板表面積を実効的に増加
した三次元構造をもったダイナミックメモリー半導体記
憶装置に関する。
〔従来の技術〕
従来のダイナミックメモリー半導体記憶装置として、
例えば、半導体基板表面に設けられた微細な溝表面に絶
縁膜を設け、その上から溝内部に充填した電極材を電荷
蓄積部としながら、溝内部の基板表面を蓄積モードで動
作させるものがある。
この半導体記憶装置によれば、基板表面の不純物濃度
を高くすることにより、基板表面の空乏層のひろがりに
よってMOS容量が減少するのを防ぐようにしている。
〔発明が解決しようとする問題点〕
しかし、従来の半導体記憶装置によれば、基板表面の
不純物濃度を高くして使っているのでMOSFETの基板電位
特性が悪化する欠点がある。この場合、溝内壁のみを高
濃度化すればこの問題は起こらないが、実現するプロセ
スが難しい。
〔問題点を解決するための手段〕
本発明は上記に鑑みてなされたものであり、
半導体基板に隣りあって形成された第１および第２の
溝と、
前記第１の溝内に形成されたMOS容量の一方の電極
と、
前記半導体基板に埋め込まれて形成され、前記半導体
基板と逆の導電形を有し、前記MOS容量の他方の電極，
および前記MOS容量に隣りあって形成されるMOSFETのソ
ース・ドレインの一方となる共通埋込電極と，
前記半導体基板に形成され、所定の電位を前記第２の
溝の周辺に形成される前記MOSFETのチャンネルを介して
前記共通埋込電極に供給する前記MOSFETのソース・ドレ
インの他方を備えたことを特徴とする半導体記憶装置を
提供する。本発明の実施態様によると、基板電位特性を
悪化させないでMOS容量を増加させるため半導体基板表
面に二種類の溝を設ける。第一種の溝はその内側表面の
中間部に設けられた絶縁厚膜とチャンネルストッパーと
からなる分離領域をはさんで底部側の内部表面に基板、
容量絶縁薄膜、及び良導体の容量電極からなり少なくと
も基板側の一部に基板と逆導電性の第一の埋込電極を設
けたMOS容量と、開口部側の内側表面乃至基板表面にあ
って前記容量電極と電気的に接続された基板と逆導電性
の第一電極とを有する。
第二種の溝は開口部付近の内壁表面乃至基板表面に基
板と逆導電性のソース・ドレインの一方としての第二の
電極、底部側に内部表面に接する基板と逆導電性のソー
ス・ドレインの他方としての第二の埋込電極、および溝
内壁表面に設けられたゲート絶縁薄膜及びゲート電極と
しての良導体からなるMOSFETを構成する。この第一種及
び第二種の溝はアレイ状に配置され、第一及び第二の埋
込電極は、基板と逆導電性の第三の埋込電極によって架
橋されている。第一種の溝は容量電極を電荷蓄積部とす
る一つの記憶ノードとなり、情報が第一電極を通じて書
き込み或いは読み出しされる。第二の溝はゲート電極に
MOSFETを反転させる電位を印加し、第二の電極に与えら
れた電位及び電荷をこの反転層、第二の埋込電極、及び
第三の埋込電極を介して第一の埋込電極を与えるように
なっている。
本発明の好ましい実施態様によれば、溝内の基板表面
に反転層を形成し、絶縁膜を介して構内部に埋められた
電荷蓄積部としての容量電極の対極に用いる。これによ
って、基板表面の不純物濃度を高くすることなく、電荷
蓄積電極の使用電圧範囲でMOS容量を100％使うことがで
きる。この反転層に少数キャリアを供給するソースとし
て、定電位に接続された基板と逆導電性の電極が、エピ
タキシャル成長法あるいはウェル構造により基板深部と
表面の電気導電性を変え、溝がこの接合にまたがる深さ
にまで達するようにして形成される。この場合に、ダイ
ナミックRAMメモリーセルのように、高密度にMOSFET及
びMOS容量を配した構造になるときは、特性安定の為に
必要なバックゲートバイアスを十分に与えることができ
なくなる恐れがあるが、本発明では記憶ノードとなる溝
部分を格子点として格子状に連続した埋込拡散層をソー
ス電極とし、MOS構造のバックゲートと基板深部とは同
一導電性の半導体領域が連続するようにしてこれを解決
している。さらに、この場合、埋み込み拡散層を定電位
に接続する構造が必要になるが、本発明では、溝内に埋
め込まれた導伝物質をゲート電極とし、溝底部付近に接
するソース・ドレインの一方としての埋込拡散層と基板
表面に形成され定電位につながる基板と逆導電性のソー
ス・ドレインの他方としての領域にまたがる溝側壁部を
ゲート領域とするMOSFETとして形成された溝を用い、ゲ
ート電極に定電位を印加することによりゲート領域を反
転して基板表面から埋込拡散層に電位を供給する。
以下、本発明の半導体記憶装置を詳細に説明する。
〔実施例〕
第１図より第11図は本発明の一実施例による半導体記
憶装置を製造する工程を示す。先ず、Ｐ型シリコン単結
晶基板１の表面に、周知の技術により、高濃度ボロンの
チャンネルストッパー２、及び膜厚4000〜6000Åの二酸
化硅素（SiO2）３からなる分離領域を作る。次いで、基
板表面の熱酸化により500Å程度のシリコン酸化膜４、
気相成長法により１μｍ厚のシリコン窒化膜（Si3N4）
５を全面に被着した後、周知の写真食刻によりフォトレ
ジスト６をマスクとして、窒化膜５、酸化膜４及び基板
１をエッチングし、基板１の表面から深さ1.5μｍに達
する第一の溝７を掘る。その後基板１の法線に対して角
度をつけたイオン注入法により、ボロン８を溝７内の
み、特に側壁部に重点的に導入する（第１図）。
次に、溝７の側壁に素子分離領域を形成する。このた
め、レジスト６を剥離除去してから基板表面の熱酸化を
行う。窒化膜５に覆われた基板表面は酸化されず、溝７
の壁面にだけ厚さ4000〜8000Åの酸化膜９をつけること
ができる。この段階で、周知の写真食刻によりフォトレ
ジスト10をマスクとして、前工程と同様に、第二の溝11
を深さ1.5μｍに形成する（第２図）。
フォトレジスト10を剥離除去した後、異方性のプラズ
マエッチングにより酸化膜を除去すると第一の溝７の内
部の酸化膜９は底部のみ除去され、側壁部に残った形に
することができる（第３図）。
この段階で、窒化膜５及び酸化膜９をマスクとして基
板１のエッチングを進め、第一及び第二の溝の両方を深
さ５μｍまで深くする。次に、溝の深さ方向に平行のイ
オン注入によって高濃度のリン12を溝の底部に導入する
（第４図）。
次に、不活性雰囲気中での熱処理によって、第一の溝
７と第二の溝11間で、及び第一の溝７相互間で接続した
ひとつのｎ型拡散領域13を形成する。ｎ型拡散領域13は
連結された埋込領域13a,13bとなる（第５図）。
第一の溝７相互の接続は、第６図に示すように、第一
の溝７を格子状に配置することによってなされる。この
とき、基板表面は深部から連続したＰ型領域にすること
ができる。
次に、窒化膜５を除去した後、熱酸化によって溝の内
壁部に厚さ250Åの酸化膜14を形成する。これをMOS構造
の絶縁膜として用いる。さらに、溝内にシリコンをドー
プした多結晶シリコン15a,15bを埋め、これをMOS構造の
電極として用いる。ここで写真食刻により、フォトレジ
スト16をマスクとしてヒ素17を基板表面に導入する（第
７図）。
この後、第一の溝７内のポリシリコン15aとヒ素拡散
層17とを接続するためフォトレジスト18を用い写真食刻
により酸化膜４をエッチング除去する（第８図）。次い
で、リンをドープした膜厚5000Åのポリシリコン19を被
着形成する（第９図）。これで、本発明の主要部分が完
成された。
第一の溝７に於いては、溝内のポリシリコン15aが溝
側壁を環状にとり囲む分離領域8,9によって溝底部の基
板表面と電気的に分離された表面のｎ型層と接続されて
いるが、第二の溝には分離領域がない。この第一の溝７
と第二の溝11とは底部付近で、リンを拡散したｎ型拡散
領域13により接続されている。
この後、次のようにして周知の技術により１トランジ
スタ型メモリーセルができる。即ち、熱酸化により層間
絶縁膜20、及びゲート酸化膜21を形成し、情報読み出し
書込用のトランスファーゲートのゲート電極22を設け
（第10図）、さらにソース・ドレイン23a,23bを設け、
リンシリケートガラスの層間膜24、コンタクト孔25、及
びアルミ薄膜の配線26を設けて１トランジスタ型ダイナ
ミックメモリーを完成する（第11図）。
〔発明の効果〕
以上説明したように、本発明の半導体記憶装置によれ
ば、電荷蓄積部に於て反転層を対極とすることにより電
気容量を増大でき、キャリア供給用の電極を網状の埋込
拡散層とすることにより基板表面にバックゲートを伝え
ることができ、埋込拡散層に電位を供給する部分を電荷
蓄積部と類似の溝構造とすることで製造プロセスを簡略
化できる効果がある。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic memory having a three-dimensional structure in which the surface area of a semiconductor substrate such as silicon is effectively increased by providing irregularities on the surface of the substrate. The present invention relates to a semiconductor memory device. [Prior art] As a conventional dynamic memory semiconductor memory device,
For example, there is one in which an insulating film is provided on the surface of a fine groove provided on the surface of a semiconductor substrate, and the electrode material filled in the inside of the groove is used as a charge storage portion, and the substrate surface inside the groove is operated in an accumulation mode. . According to this semiconductor memory device, by increasing the impurity concentration on the substrate surface, it is possible to prevent the MOS capacitance from decreasing due to the spread of the depletion layer on the substrate surface. [Problems to be Solved by the Invention] However, according to the conventional semiconductor memory device, there is a disadvantage that the substrate potential characteristic of the MOSFET is deteriorated because the impurity concentration on the substrate surface is increased. In this case, this problem does not occur if only the inner wall of the groove is made highly concentrated, but the process for realizing it is difficult. Means for Solving the Problems The present invention has been made in view of the above, and has first and second grooves formed adjacent to a semiconductor substrate, and formed in the first groove. One electrode of the MOS capacitor, and the other electrode of the MOS capacitor, which is formed by being embedded in the semiconductor substrate and has a conductivity type opposite to that of the semiconductor substrate.
A common buried electrode serving as one of a source and a drain of a MOSFET formed adjacent to the MOS capacitor; and a MOSFET formed on the semiconductor substrate and having a predetermined potential formed around the second groove. A semiconductor memory device provided with the other of the source and the drain of the MOSFET supplied to the common buried electrode through the channel. According to the embodiment of the present invention, two types of grooves are provided on the surface of the semiconductor substrate to increase the MOS capacitance without deteriorating the substrate potential characteristics. The first type groove has a substrate on the inner surface on the bottom side, sandwiching a separation region consisting of an insulating thick film and a channel stopper provided at an intermediate portion of the inner surface,
A MOS capacitor comprising a capacitor insulating thin film, a capacitor electrode of a good conductor, and a first embedded electrode having a conductivity opposite to that of the substrate provided at least on a part of the substrate side; It has a substrate electrically connected to the capacitor electrode and a first electrode having an opposite conductivity. The second kind of groove is a second electrode as one of a source and a drain opposite to the substrate on the inner wall surface or the substrate surface near the opening, and a source and a drain opposite to the substrate in contact with the inner surface on the bottom side. A MOSFET comprising a second buried electrode as the other, a gate insulating thin film provided on the inner wall surface of the groove, and a good conductor as the gate electrode. The first and second types of grooves are arranged in an array, and the first and second embedded electrodes are bridged by a third embedded electrode having a conductivity opposite to that of the substrate. The first type groove serves as one storage node using the capacitor electrode as a charge storage portion, and information is written or read through the first electrode. The second groove is on the gate electrode
A potential for inverting the MOSFET is applied, and the potential and electric charge given to the second electrode are given to the first embedded electrode through the inversion layer, the second embedded electrode, and the third embedded electrode. It is like this. According to a preferred embodiment of the present invention, an inversion layer is formed on the surface of the substrate in the groove, and is used as a counter electrode of a capacitor electrode as a charge storage portion embedded in the structure via an insulating film. As a result, it is possible to use 100% of the MOS capacitor within the operating voltage range of the charge storage electrode without increasing the impurity concentration on the substrate surface. As a source for supplying minority carriers to this inversion layer, an electrode that is opposite in conductivity to the substrate and is connected to a constant potential changes the electrical conductivity between the deep portion of the substrate and the surface by the epitaxial growth method or well structure, and the groove extends over this junction. It is formed so as to reach the depth. In this case, when a structure in which MOSFETs and MOS capacitors are arranged at a high density, such as a dynamic RAM memory cell, there is a possibility that the back gate bias necessary for stabilizing the characteristics cannot be sufficiently given. According to the present invention, a buried diffusion layer which is continuous in a lattice with a trench portion serving as a storage node as a lattice point is used as a source electrode, and a back gate of a MOS structure and a deep portion of a substrate are formed so that semiconductor regions of the same conductivity are continuous. This is solved. Further, in this case, a structure for connecting the buried diffusion layer to a constant potential is required. However, in the present invention, the conductive material buried in the trench is used as the gate electrode, and the source / drain in contact with the vicinity of the trench bottom is formed. Using a trench formed as a MOSFET having a trench side wall portion as a gate region extending over a region as a buried diffusion layer on one side and the other side of the substrate and the opposite conductivity source / drain connected to a constant potential formed on the substrate surface, By applying a constant potential to the gate electrode, the gate region is inverted to supply the potential from the substrate surface to the buried diffusion layer. Hereinafter, the semiconductor memory device of the present invention will be described in detail. [Embodiment] FIGS. 1 to 11 show steps of manufacturing a semiconductor memory device according to an embodiment of the present invention. First, on the surface of a P-type silicon single crystal substrate 1, a well-known technique is used to form a separation region made of a high-concentration boron channel stopper 2 and a silicon dioxide (SiO 2 ) 3 having a film thickness of 4000 to 6000Å. Next, a silicon oxide film 4 of about 500 ° is formed by thermal oxidation of the substrate surface,
1 μm thick silicon nitride film (Si 3 N 4 ) by vapor deposition
Then, the nitride film 5, the oxide film 4 and the substrate 1 are etched using a photoresist 6 as a mask by a well-known photo-etching, and a first depth of 1.5 μm is reached from the surface of the substrate 1. Dig the groove 7. Thereafter, boron 8 is introduced only in the groove 7, especially in the side wall portion, by ion implantation at an angle to the normal line of the substrate 1 (FIG. 1). Next, an element isolation region is formed on the side wall of the groove 7. Therefore, after the resist 6 is peeled off, thermal oxidation of the substrate surface is performed. The surface of the substrate covered with the nitride film 5 is not oxidized,
The oxide film 9 having a thickness of 4000 to 8000Å can be attached only to the wall surface of the. At this stage, using the photoresist 10 as a mask by well-known photo-etching, as in the previous step, the second groove 11 is formed.
Is formed to a depth of 1.5 μm (FIG. 2). When the oxide film is removed by anisotropic plasma etching after the photoresist 10 is removed, only the bottom of the oxide film 9 inside the first groove 7 is removed, and the oxide film 9 can be left on the side wall portion ( (Fig. 3). At this stage, the etching of the substrate 1 is advanced using the nitride film 5 and the oxide film 9 as a mask, and both the first and second grooves are deepened to a depth of 5 μm. Next, high-concentration phosphorus 12 is introduced into the bottom of the groove by ion implantation parallel to the depth direction of the groove (FIG. 4). Next, one n-type diffusion region 13 connected between the first groove 7 and the second groove 11 and between the first grooves 7 is formed by heat treatment in an inert atmosphere. The n-type diffusion region 13 becomes the connected buried regions 13a and 13b (FIG. 5). The connection of the first grooves 7 is made by arranging the first grooves 7 in a lattice pattern as shown in FIG. At this time, the substrate surface can be a P-type region continuous from the deep portion. Next, after removing the nitride film 5, an oxide film 14 having a thickness of 250 Å is formed on the inner wall portion of the groove by thermal oxidation. This is used as an insulating film having a MOS structure. Further, the trenches are filled with silicon-doped polycrystalline silicon 15a, 15b, and this is used as an electrode of a MOS structure. Here, arsenic 17 is introduced onto the substrate surface by photolithography using the photoresist 16 as a mask (FIG. 7). Thereafter, the oxide film 4 is etched away by photolithography using a photoresist 18 to connect the polysilicon 15a in the first groove 7 and the arsenic diffusion layer 17 (FIG. 8). Then, phosphorus-doped polysilicon 19 having a film thickness of 5000 Å is deposited (FIG. 9). Thus, the main part of the present invention is completed. In the first trench 7, the polysilicon 15a in the trench is connected to the n-type layer on the surface electrically isolated from the substrate surface at the bottom of the trench by the isolation regions 8 and 9 surrounding the trench sidewall in an annular shape. However, there is no separation area in the second groove. This first groove 7
The second groove 11 and the second groove 11 are connected to each other near the bottom by an n-type diffusion region 13 in which phosphorus is diffused. After that, a one-transistor type memory cell is formed by a well-known technique as follows. That is, an interlayer insulating film 20 and a gate oxide film 21 are formed by thermal oxidation, a gate electrode 22 of a transfer gate for reading and writing information is provided (FIG. 10), and further, source / drain 23a and 23b are provided.
A one-transistor dynamic memory is completed by providing an interlayer film 24 of phosphor silicate glass, a contact hole 25, and a wiring 26 of an aluminum thin film (FIG. 11). [Effects of the Invention] As described above, according to the semiconductor memory device of the present invention, the electric capacity can be increased by using the inversion layer as the counter electrode in the charge storage portion, and the carrier supply electrode is embedded in a net shape. The back diffusion can be transmitted to the substrate surface by using the buried diffusion layer, and the manufacturing process can be simplified by forming the portion for supplying the potential to the buried diffusion layer with a groove structure similar to the charge storage portion. .
【図面の簡単な説明】
第１図より第５図及び第７図より第11図は本発明の一実
施例による半導体記憶装置の製造工程を示す縦断面図、
第６図は同じく平面図である。
符号の説明
１……シリコン基板
２、８……ボロン拡散層
３、４、９、14、20、21……酸化膜
５……窒化膜
６、10、16、18……フォトレジスト
７、11……溝、12、13……リン拡散層
15、19、22……ポリシリコン
17,23a,23b……ヒ素拡散層
24……PSG、25……コンタクト
26……アルミBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 5 and FIG. 7 to FIG. 11 are longitudinal sectional views showing a manufacturing process of a semiconductor memory device according to an embodiment of the present invention.
FIG. 6 is a plan view of the same. Description of reference numeral 1 ... Silicon substrate 2, 8 ... Boron diffusion layer 3, 4, 9, 14, 20, 21 ... Oxide film 5 ... Nitride film 6,10,16,18 ... Photoresist 7,11 … Groove, 12, 13… Phosphorus diffusion layers 15, 19, 22… Polysilicon 17,23a, 23b… Arsenic diffusion layers 24… PSG, 25… Contact 26… Aluminum
Claims (1)
の溝と、 前記第１の溝内に形成されたMOS容量の一方の電極と、 前記半導体基板に埋め込まれて形成され、前記半導体基
板と逆の導電形を有し、前記MOS容量の他方の電極，お
よび前記MOS容量に隣りあって形成されるMOSFETのソー
ス・ドレインの一方となる共通埋込電極と， 前記半導体基板に形成され、所定の電位を前記第２の溝
の周辺に形成される前記MOSFETのチャンネルを介して前
記共通埋込電極に供給する前記MOSFETのソース・ドレイ
ンの他方を備えたことを特徴とする半導体記憶装置。 ２．前記一方の電極をアレイ状に配置し、該アレイ状に
配置された前記一方の電極とそれぞれ対向する前記他方
の電極が前記共通埋込電極として共通に接続されている
ものであることを特徴とする特許請求の範囲第１項記載
の半導体記憶装置。 ３．前記一方の電極をアレイ状に配置し、該アレイ状に
配置された前記一方の電極とそれぞれ対向する前記他方
の電極が前記共通埋込電極として網状に接続されている
ものであることを特徴とする特許請求の範囲第１項記載
の半導体記憶装置。(57) [Claims] A first and a second formed adjacent to a semiconductor substrate;
A groove, one electrode of a MOS capacitor formed in the first groove, and formed to be embedded in the semiconductor substrate, having a conductivity type opposite to that of the semiconductor substrate, and the other of the MOS capacitor An electrode, a common buried electrode serving as one of a source and a drain of a MOSFET formed adjacent to the MOS capacitor, and a predetermined potential formed at the periphery of the second groove formed on the semiconductor substrate. A semiconductor memory device comprising: the other of a source and a drain of the MOSFET supplied to the common buried electrode through a channel of the MOSFET. 2. The one electrode is arranged in an array, and the other electrode, which is opposed to the one electrode arranged in the array, is connected in common as the common embedded electrode. The semiconductor memory device according to claim 1, wherein 3. The one electrode is arranged in an array, and the other electrode opposed to the one electrode arranged in the array is connected in a mesh as the common embedded electrode. The semiconductor memory device according to claim 1, wherein
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067383A JP2668873B2 (en) | 1987-03-20 | 1987-03-20 | Semiconductor storage device |
| DE3851649T DE3851649T2 (en) | 1987-03-20 | 1988-03-18 | Dynamic random access memory device composed of a plurality of single transistor cells. |
| EP88104391A EP0283964B1 (en) | 1987-03-20 | 1988-03-18 | Dynamic random access memory device having a plurality of improved one-transistor type memory cells |
| US07/171,094 US4969022A (en) | 1987-03-20 | 1988-03-21 | Dynamic random access memory device having a plurality of improved one-transistor type memory cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067383A JP2668873B2 (en) | 1987-03-20 | 1987-03-20 | Semiconductor storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63232458A JPS63232458A (en) | 1988-09-28 |
| JP2668873B2 true JP2668873B2 (en) | 1997-10-27 |
Family
ID=13343432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62067383A Expired - Fee Related JP2668873B2 (en) | 1987-03-20 | 1987-03-20 | Semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2668873B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5363327A (en) * | 1993-01-19 | 1994-11-08 | International Business Machines Corporation | Buried-sidewall-strap two transistor one capacitor trench cell |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58213464A (en) * | 1982-06-04 | 1983-12-12 | Nec Corp | Semiconductor device |
| JPS62208662A (en) * | 1986-03-07 | 1987-09-12 | Sony Corp | Semiconductor memory |
| JP2674992B2 (en) * | 1986-11-28 | 1997-11-12 | 株式会社日立製作所 | Plate wiring formation method in semiconductor memory device |
-
1987
- 1987-03-20 JP JP62067383A patent/JP2668873B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63232458A (en) | 1988-09-28 |
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