JPS58213464A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration and reliability by forming an insulated gate type field-effect transistor to the first side surface of a groove formed to a semiconductor substrate to a U-shaped form and forming a capacitance to a second side surface. CONSTITUTION:The insulated gate type field-effect transistor, which uses N type impurity diffusion layers 103, 104 as source and drain, an oxide film 105 as a gate insulating film and polycrystalline silicon 106 as a gate electrode, is formed to the first side surface of the U-shaped groove 102 formed to the P type silicon substrate 101. A capacitance section consisting of an N type impurity diffusion layer 109, an oxide film 107 and polycrystalline silicon 108 is formed to the second side surface. An area of the capacitance in which charges are stored is compensated by deepening the groove 102 even when a flat area of a memory cell is reduced because the memory cell constituted in this manner is formed by utilizing the side surfaces of the groove 102. Accordingly, the degree of integration of the semiconductor memory circuit device can be improved.

Description

[Detailed description of the invention] This release F! A relates to semiconductor devices], and particularly relates to semiconductor memory circuit devices.

In recent years, dynaN% type random access memory circuit devices (DRAMs) using insulated gate field effect transistors (OυS transistors) have low power consumption,
It is attracting attention because it has advantages such as a memory cell consisting of one transistor. A conventional memory cell is 1
It consists of a run lister (2 MOS) and a capacitor that stores charge, which is information. However, when the memory cell is shrunk to improve the degree of integration, the capacitor becomes smaller and the amount of charge stored increases. This caused problems such as soft errors caused by alpha rays.

An object of the present invention is to provide a semiconductor device with a remarkable improvement in the degree of integration and high reliability.

In this invention, the first groove of a U-shaped groove is formed in a semiconductor substrate.
The device is characterized in that an insulated gate field effect transistor is formed on the side surface of the device, and a capacitor is formed on the second side surface.

According to the present invention, in a dynamic random access memory circuit device, it is possible to reduce the number of memory cells without completely reducing the capacitance portion that stores electric charge, which is information, and to achieve high integration and reliability. A semiconductor device with high performance can be obtained.

Next, an embodiment of the present invention will be described with reference to the drawings. This embodiment relates to a semiconductor memory circuit device.

FIG. 1 is a cross-sectional view for explaining this embodiment.

FIG. 1 shows a memory cell of a dynamic two-order access memory circuit device constructed using the present invention. The first side surface of the U-shaped groove 102 formed in the P-type silicon substrate 101 (the N-type impurity diffusion layers 103 and 104 are
An insulated gate field effect transistor is formed using an oxide film 105'r as a drain, an oxide film 105'r as a gate insulating film, and a polycrystalline silicon 106 as a gate electrode, and an N-type impurity diffusion layer 109. Oxide film 107. polycrystalline silicon yi
A capacitive portion made of O8 is formed. The N-type impurity diffusion layer 104, which is the source of the insulated gate field effect transistor, and the N-type impurity diffusion layer 109, which is the capacitor, are as follows.
They are connected through an N-type impurity diffusion layer 110. The filled oxide film 111 is a k-th oxide film that separates memory cells, and is located in the opening 1 of the interlayer insulating film 112 in the N-type impurity diffusion layer 103.
Aluminum electrodes 114 connected throughout 13 are wiring electrodes for writing and reading information.

The memory cell formed in this way has an aluminum electrode 11
4 is a digit line, polycrystalline silicone) 106? A memory circuit is configured as a word line, and charge writing, that is, accumulation and exposure is performed as follows.

The charge is written by making the insulated gate field effect transistor formed on the first side surface fully conductive, and transferring the charge placed on the aluminum electrode 114 to the capacitor section formed on the second side surface and the P-type silicon substrate. 101 and N-type impurity diffusion layer 1
Reading is performed by accumulating charges in depletion layer capacitances formed in the capacitors 09 and 110, and reading is performed by turning on the insulated gate field effect transistors formed on the first side of the charges accumulated in the respective capacitors. , aluminum electrode 114
It is done by placing it on.

The memory cell configured in this way is formed by utilizing the side surfaces of the U-shaped groove formed in the silicon substrate, so even if the planar area of the memory cell is reduced, charges are accumulated. The area of the capacitance can be compensated for by deepening the U-shaped groove.

Therefore, the planar area of the memory cell can be reduced without reducing the capacitance area of the memory cell, and the degree of integration of the semiconductor memory circuit device can be improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor fefIt according to an embodiment of the present invention. In the figure, 101...P-type silicon substrate, 102...
...U-shaped groove, 103, 104, 109, 11
0...N-type impurity diffusion layer, 105...
Gate oxide film, 106.108...Polycrystalline silicon, 107...rR conversion #1 i i
...Field oxide film, 112... ...Interlayer insulating film, 113...Opening, 114.
...Aluminum electrode. Figure 1

Claims (1)

[Claims] An insulated gate field transistor is formed on a first side surface of a U-shaped groove formed in a semiconductor substrate. A semiconductor device characterized by having a capacitor formed on a second side surface.