JPS5978561A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the area occupation factor of a memory cell and thus contrive to increase capacitance by forming a memory capacitor between two conductive layers and between the first layer conductive layer and a substrate. CONSTITUTION:The clearance between the first layer conductive layer 5 and the substrate 1 is insulated by a thin insulation layer 21, and the memory capacitor is formed not only between the conductive layer 5 and the grounded second layer conductive layer 7 but also between the conductive layer 5 and the substrate 1. The amount of accumulated charges is increased by the amount of the capacitor formed between this conductive layer 5 and the substrate 1. Besides, the insulation layer 21 is sufficient by one formed in completely the same process as a gate insulation film 8 of a transfer transistor, and can be realized without the increase of the process. Therefore, the capacitor can be increased without increasing the occupation area, and then the integration degree of a semiconductor device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a semiconductor memory device, particularly to a capacitive element of a one-transistor dynamic random access memory device.

Conventional Structure and Its Problems A typical structure of a conventional dynamic random access memory device is shown in FIG. In FIG. 1, 1 is a P-type silicon substrate, 2 and 3 are n-diffusion regions, 41L and 4b are field oxide films, 6 is a conductive layer connected to the n+ diffusion region 2, and 6 is a thin insulating layer such as 5i02. , 7 is a grounded conductive layer, 8 is a gate insulating film, and 9 is a gate electrode of a transfer transistor. And the n diffusion region 3
is connected to the pit line 10, and the gate electrode is connected to the word line 11. In this device configuration, the conductive layers 5 and 7 form a pair of opposing electrodes on the field oxide film 4b with an insulating film 6 such as 5i02 interposed therebetween. Then, the signal charge from the bit line 10 is transferred to the transfer gate 9 and n
It is accumulated in the conductive layer 5 through the type diffusion region 2.

However, in the case of such a conventional device configuration, the memory capacitor is constituted only by the conductive layer 5 on the field oxide film 4b and the quantum, and therefore requires a relatively large area. In order to improve the integration density to increase the capacity of storage devices, the trend is to reduce the size and shape of each element, but reducing the area of the memory capacitor means increasing the capacity per capacitor and therefore the storage capacity. This reduces the amount of charge accumulated in the device, increasing the risk of malfunction and posing an impediment to increasing the degree of integration.

Purpose of the Invention The present invention solves the above-mentioned problems of the conventional technology by providing a memory capacitor not only between two IT layers but also between the first conductive layer and the substrate. The present invention provides a semiconductor memory device in which the area occupation rate of memory cells is reduced and the capacity is increased by forming the memory cells.

Structure of the Invention The present invention forms a capacitor of a memory cell by forming a first conductive layer between a semiconductor substrate and a second conductive layer with an insulating film interposed therebetween. Thereby, the area occupied by the capacitor can be reduced.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows an embodiment of the present invention.
The second conductive layer 5 and the substrate 1 are insulated by a thin insulating layer 21, and the memory capacitor is formed between the conductive layer 5 and the grounded second conductive layer 7. In addition, it is also formed between the conductive layer 5 and the substrate 1. As is clear from a comparison with FIG. 1, the amount of accumulated charge is increased by the amount of the capacitor formed between the conductive layer 5 and the substrate 1 compared to the conventional device.

However, the insulating layer 21 may be formed in exactly the same process as the gate insulating film 8 of the transnor transistor, and can be realized without increasing the number of steps compared to the conventional example.

In FIG. 2, when the voltage of the conductive layer 5 is increased above the threshold voltage, an inversion layer is formed on the surface of the substrate 1. The field oxide film 4b is in contact with this substrate surface inversion layer.
Although the field oxide film is insulated from the diffusion layer 2, the smaller the width of the field oxide film, the larger the opposing area between the conductive layer 6 and the substrate 1 becomes, and the amount of charge storage can be increased.

In FIG. 3, a P-type impurity is implanted into the substrate surface of the capacitor/layer formation part to form a P-type high concentration region 31 so that an inversion layer does not occur even when a high voltage is written to the conductive layer 5. This is what I did. With such a structure, the field oxide film 4b shown in FIG. 2 becomes unnecessary, and the opposing area between the conductive layer 5 and the substrate 1 can be further increased.

In fact, in the structure shown in FIG. 3, since no inversion layer is generated, no junction capacitance is generated between the surface of the substrate 1 and the substrate 1, and the amount of charge stored in the conductive layer 5 can be further increased.

Note that 5102 film can be used as the insulating films 6 and 8 and the insulating layer 21, but Si3N4 or T
A film such as a205 can be formed. By using such an insulating film, it is possible to further increase the amount of charge stored in the capacitive element.

Effects of the Invention As detailed above, according to the present invention, the cabling ratio can be significantly increased without increasing the occupied area, and excellent practical effects can be achieved in reducing the degree of integration of semiconductor devices. It is something that you have.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional configuration diagram showing an overview of a conventional dynamic random access memory device, and FIGS. 2 and 3 are cross-sectional configuration diagrams showing an overview of a dynamic random access memory device according to an embodiment of the present invention. be. 1-...P-type silicon substrate, 2,3...n-type diffusion region, 4a, 4b...field oxide film, 5,a, 9...
Conductive layer, 6, 8... Insulating film, 10... Bit line, 11-. Word line, 21 Insulating layer, 31...
P-type fossa concentration area. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (2)

[Claims] (1) A semiconductor substrate, a first conductor layer formed on the semiconductor substrate with an insulating layer interposed therebetween, and a second conductor layer formed on the first conductor layer with an insulating layer interposed therebetween. having a layer;
A semiconductor memory device in which the first conductor layer is used as a common electrode and capacitors formed between the semiconductor substrate and the second conductor layer are memory cell constituent elements. (2) A highly doped region formed by doping the surface of a region of the semiconductor substrate that forms a capacitive element with the first conductive layer with an impurity of the same conductivity type as that of the substrate at a high concentration, as claimed in claim 1. The semiconductor storage device described in .