JPH02270378A - Floating gate type memory device - Google Patents

Abstract

PURPOSE:To obtain such a floating gate type memory device that erroneous write is lessened in probability, the charge holding characteristic is improved, the structure is made simple, and its area is made small by a method wherein write is carried out only through charges produced in a single semiconductor junction provided to the periphery or the lower part of a charge storing floating gate. CONSTITUTION:A charge storing floating gate 1 is provided, and write is carried out only through charges occurred in a single semiconductor junction provided to the periphery or the lower part of the charge storing floating gate 1. For instance, when charges are written in the floating gate 1 while a ground potential 8 is given to an N<->-substrate 5 through the intermediary of an aluminum wiring layer 7, an avalanche breakdown occurs in a semiconductor junction between a P<+>-type impurity layer 2 and the N<->-type substrate 5 to produce negative charges if a negative potential 4 higher than an avalanche breakdown voltage is given to the P<+>-type impurity layer 2 through the intermediary of the aluminum wiring layer 3. The produced charges are stored in the floating gate 1, so that write is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to the structure of a floating gate type memory element.

[Prior Art] Conventionally, as shown in Fig. 2, in memory devices with floating gates, the gate of the MO3 transistor structure is always floating, and avalanche breakdown occurs at the semiconductor junction formed at the source or drain. Data was written using the electric charge generated.

[Problem to be Solved by the Invention 1] However, in the conventional MOS type floating gate structure, although writing can be performed from either the train or source junction, there is a high possibility that erroneous writing will occur in a non-writing state. Furthermore, since there is a path to the source and drain as a release path for the charges accumulated in the floating gate, there is a strong possibility that the charge retention characteristics will deteriorate.

Therefore, in the present invention, the write operation to the floating gate is performed only by a single semiconductor junction provided around or below the floating gate without using the MO5 type structure, thereby reducing the possibility of erroneous writing and reducing the accumulated The charge release path is also small (and the aim is to improve charge retention characteristics).

Furthermore, since there is only a single semiconductor junction, the structure is simple and the area can be made smaller than in the past.

[Means for Solving the Problems] The floating gate type memory device of the present invention has the following features: a) t! ! Floating gate for load accumulation, b)
It is characterized in that writing is performed using charges generated only from a single semiconductor junction provided around or below the floating gate.

[Function] Since the present invention has the above configuration, the possibility of writing errors in the floating gate type memory element is reduced and the charge retention characteristics are improved.

Furthermore, the structure becomes simple and the area can be reduced.

[Example 1] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is a structural sectional view of a floating type memory device showing an embodiment of the present invention.

1 is a floating gate for storing charge @ff4, and the material may be aluminum, polysilicon, or any other material that can store charge. 2 is an N-type semiconductor substrate 5
This is a P+ type impurity diffusion layer having conductivity properties opposite to that of the floating gate 1, and serves as a write terminal for writing charge into the floating gate 1. 3 is an aluminum wiring layer for establishing electrical conduction with the P+ type impurity diffusion layer 2, and 6 is an N native impurity diffusion layer for establishing conduction with the N- type semiconductor substrate 5. 7 is N
An aluminum wiring layer is used to establish conduction with the ten-type impurity layer 6, and 9 is an insulating layer such as SiO or 5iOz.

In FIG. 1, a ground potential 8 is applied to an N-substrate 5 via an aluminum wiring layer 7.

To explain the operation of writing charges into the floating gate l, when a negative potential 4 higher than the avalanche breakdown voltage is applied to the P type impurity layer 2 via the aluminum wiring layer 3, the semiconductor junction with the N- type substrate 5 is applied. A small avalanche breakdown occurs in the floating gate 1, and a charge is generated (in this example, a negative charge), and this charge is accumulated in the floating gate 1, and a write operation is performed. In FIG. 1, the polarity of the substrate is N type and the polarity of the impurity layer is P type, but the polarity may be reversed.

Structurally, the floating gate 1 of the P native impurity layer 2
The amount of overlap for floating gate 1 is
As long as the length is less than or equal to , there is no need for manufacturing precision.

FIG. 3 is a diagram of a floating gate type memory cell to which the present invention is applied.

31 is an N-type impurity well region, and 32 is an N-type impurity layer formation region, which is electrically connected to the N-type impurity well region 31. 33 is a floating gate, and 34 is a P-type impurity layer forming region which becomes a write terminal. As described above, according to the present invention, since the write terminal can be freely arranged with respect to the floating gate, it is also possible to effectively use the limited space and improve the degree of integration.

[Effect of the invention] According to the present invention as described above.

This reduces the possibility of erroneous writing in floating gate memory elements, improves charge retention, and also simplifies the structure, making it possible to reduce the area.

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of a floating gate type memory element to which the present invention is applied. Figure 2 shows the conventional MO
FIG. 3 is a cross-sectional view of the structure of a Type 3 floating gate memory device. FIG. 3 is a diagram of a floating gate type memory cell to which the present invention is applied. 1...Floating gate 2...P+ type impurity diffusion layer 3.7...Aluminum wiring layer 4...Writing potential 5...N- type semiconductor substrate 6... ... N0 type impurity diffusion layer 8 ... Ground potential 9 ... Insulator layer 11 ... Floating gate 12 ... P0 type impurity diffusion layer (drain) 13 .16.20 ... Aluminum wiring layer 14 ... Write potential 15 ... P 10 type impurity diffusion layer (source) 17 ...
...Ground potential 18...N- type semiconductor substrate 19...N-type impurity diffusion layer 21...Ground potential 22...Insulator layer 31...・N-type impurity well region 32...
N-type impurity layer formation region 33...Floating gate region 34...P-type impurity layer formation region Fig. 1 Fig. 2

Claims (1)

[Claims] 1) a) A floating gate for charge storage, and b) writing using charges generated only from a single semiconductor junction provided around or below the floating gate. A floating gate type memory device.