JPH02285681A - Floating gate type memory device - Google Patents

Abstract

PURPOSE:To make wide a difference between a write voltage and a wrong write voltage and to make it possible to offer a stable write condition by a method wherein a semiconductor region for data write use is divided into two regions, whose impurity concentrations are different from each other, and the region having a low impurity concentration is positioned on the side of a floating gate. CONSTITUTION:The impurity concentration of a P<-> impurity layer 3 is made thinner than that of a P<+> impurity layer 2. The layer 3 having the lower impurity concentration out of these two impurity layers is positioned on the side of a floating gate. A negative potential 5 is first applied to the layer 2. If the potential 5 is an avalanche breakdown voltage or higher between the layer 3 and an N<-> substrate 6, an avalanche breakdown voltage is caused in the semiconductor junction part between the layer 3 and the substrate 6 and charge is generated. This charge is stored in the floating gate 1 and a write operation is conducted. If the potential 5 is equal to an avalanche breakdown voltage between the layer 3 and the substrate 6 or lower, generated charge does not reach up to the gate 1 and an avalanche breakdown is not caused. Therefore, data can not be written.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a floating gate type memory device.

[Conventional technology]

Conventionally, a data write terminal of a memory element having a fluted gate has used a single impurity concentration semiconductor region having a polarity different from that of the semiconductor substrate under the floating gate, as shown in FIG.

During writing, a reverse voltage is applied to the semiconductor junction formed between the write terminal and the semiconductor substrate, and charges are written into the floating gate by avalanche breakdown. [Problems to be Solved by the Invention] However, in the conventional device, a semiconductor region with a high impurity concentration was used to reduce the resistance value due to the necessity of applying a potential to the write terminal.

Since the write voltage of a floating gate type memory element is determined by the avalanche breakdown voltage mentioned above, the higher the impurity concentration in the data write terminal portion, the lower the write voltage tends to be.

However, if the impurity concentration of the data write terminal becomes higher and the data write voltage becomes lower, the erroneous write voltage in the data non-write state will naturally also become lower, so the difference between the write voltage and the erroneous write voltage becomes smaller, reducing the write margin. There was a problem with that.

Therefore, in the present invention, the semiconductor region for data writing is divided into two regions with different impurity concentrations, the region with low impurity concentration is located on the floating gate side, and the region with high impurity concentration is placed in contact with the region with low impurity concentration. By doing so, data is written using avalanche breakdown that occurs between a region with a low impurity concentration and the semiconductor substrate during writing, and avalanche breakdown occurs only in a region with a high impurity concentration during non-writing, and the floating gate is This is intended to increase the write margin by widening the difference between the write voltage and the erroneous write voltage by adopting a configuration that does not have any influence.

[Means to solve the problem]

The floating gate type memory element of the present invention includes a) a floating gate 1 for charge storage provided on a semiconductor substrate, and b) a semiconductor region having a polarity different from that of the semiconductor substrate as a data writing terminal. C) The inside of the data writing semiconductor region is divided into two regions with different concentrations, and one of the regions with a lower concentration is located on the floating gate side.

[For production]

Since the present invention has the above configuration, it widens the difference between the write voltage and the erroneous write voltage of the floating gate type memory element, and enables a stable write state.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a structural sectional view of a floating type memory device showing an embodiment of the present invention.

Reference numeral 1 designates a floating gate for storing charge, and the material thereof may be aluminum, polysilicon, or any other material that can store charge. 2 is a P-type impurity layer having a conduction polarity opposite to that of the N-type semiconductor substrate 6, and 3 is a P--type impurity layer whose impurity concentration is lower than that of the P-type impurity layer 2. Since the P+ type impurity layer 2 and the P− type impurity layer 3 have the same polarity and are in contact with each other, conduction is established between them.

Reference numeral 4 denotes an aluminum wiring layer for establishing electrical conduction with the P-type impurity layer 2. Reference numeral 7 denotes an N0-type impurity layer for establishing conduction to the N-type semiconductor substrate 6. 8 is an aluminum wiring layer for establishing conduction with the N0 type impurity layer 7; 10 is SiO,
It is an insulating material layer such as 5i02.

In FIG. 1, the N-substrate 6 has an aluminum wiring layer 8.
A ground potential 9 is applied via.

To explain the operation of writing charges into the floating gate 1, the charge is written into the P+ type impurity layer 2 via the aluminum wiring layer 4.
A negative potential 5 is applied to.

If the potential 5 is higher than the avalanche breakdown voltage between the P- type impurity layer 3 and the N- type substrate 6, avalanche breakdown occurs in the semiconductor liquid junction and a charge is generated (in this example, a negative charge). And this charge is floating gate 1
This means that the write operation has been performed. The potential 5 is lower than the avalanche breakdown voltage between the P- type impurity layer 3 and the N- type substrate 6, and the potential 5 is lower than the avalanche breakdown voltage between the P+ type impurity layer 2 and the N-
When the avalanche breakdown voltage is higher than the avalanche breakdown voltage between the P+ type impurity layer 2 and the N- type substrate 6, avalanche breakdown occurs only between the P+ type impurity layer 2 and the N- type substrate 6, and the charges generated there are transferred to the P- type substrate 6.
Because of the type impurity layer 3, it cannot reach the floating gate 1 and data cannot be written.

If the potential 5 is lower than the avalanche breakdown voltage between the P+ type impurity layer 2 and the N- type substrate 6, avalanche breakdown does not occur anywhere, so data cannot be written.

In FIG. 1, the polarity of the substrate is N type and the polarity of the impurity layer is P type, but the polarity may be reversed.

Figure 3 shows write control MO3 to which the present invention is applied.
It is a floating gate type memory with a transistor.

3] is a charge storage floating gate 1, 32 is a P-
35 is a type impurity layer, 33 is a gate electrode of a write control MOS transistor, 34 is an aluminum wiring layer for establishing conduction to the gate electrode 33 and becomes a gate terminal;
is a P+ type impurity layer and serves as a source of the MO8I- run sister for write control. 36 is a P+ type impurity layer which serves as a drain of a write control MOS transistor.

Reference numeral 37 is an aluminum wiring layer for establishing conduction to the P+ type impurity layer 36 and serves as a drain terminal. 38 is an N- type semiconductor substrate, 39 is an N0 type impurity layer for establishing conduction to the N- type semiconductor substrate 38, and 40 is the N0 type impurity layer 3.
The aluminum wiring layer serves as a substrate electrode to provide electrical conduction. In FIG. 3, the write control MO3+- transistor source and the write voltage application impurity layer according to the present invention are shared.

In FIG. 3, when a ground potential 41 is applied to the substrate electrode 40 and a voltage (-v th) 42 higher than the write control MO3I-transistor threshold voltage is applied to the gate terminal 34, at 33.35.36. MO for write control configured
3) Run lister turns on.

In this state, when a voltage (-Vw) 4B higher than the avalanche breakdown voltage between the P-type impurity layer 32 and the N-type semiconductor substrate 38 is applied to the drain terminal 37, charges are accumulated in the floating gate 31. and data writing is completed.

Further, when the ground potential is applied to the gate terminal 34 (non-write state), the write control MOS transistor is turned off.
Since it is turned off, a write voltage (-V) is applied to the drain terminal 37.
w) Even if 4B is applied, no voltage is applied to the P-type impurity layer, and no data is written to the floating gate 31. Even if a noise-like potential were to be transmitted to the P+ type impurity layer, it would not exceed the write voltage (-Vw), and would be much smaller than (-Vw), so avalanche breakdown would occur. This is only between the P+ type impurity layer 35 and the N- type semiconductor substrate 38, and there is no possibility of erroneous writing.

Therefore, the concentration difference between the P- type impurity layer 32 and the P+ type impurity layer 35 is proportional to the difference in avalanche breakdown voltage, that is, the difference between the write voltage and the erroneous write voltage, and the write voltage margin can be widened by controlling the concentration. I can do it.

In FIG. 3, the polarity of the substrate is N type and the polarity of the impurity layer is P type, but the polarity may be reversed.

As described above, according to the present invention, it is possible to widen the difference between the write voltage and the erroneous write voltage, thereby making it possible to provide stable write conditions.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to widen the difference between the write voltage and the erroneous write voltage of a floating gate type memory element, making it possible to provide stable write conditions. .

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of a floating gate type memory device to which the present invention is applied. FIG. 2 is a structural cross-sectional view of a conventional single write terminal type floating gate type memory device. FIG. 3 is a structural sectional view of a floating gate type memory element with a write control MOS transistor to which the present invention is applied. 1 φ ・ ・ Kaiken ・ 2 ・ φ ・ ・ ・ φ 3 ・ ・ ・ ・ ・ 4.8・ ・ ・ ・ 5・ ・ ・ ・ ・ − 6・ ・ ・ ・ ・ ・ 7 ・ ・ ・ ・ ・ φ 9 Controversy ・ ・ ・ ・ ・ ・ 11 ・ ・ ・ ・ ・ 12 ・ ・ ・ ・ ・ ・ 13, 17 ・ ・ ・ 14 ・ ・ ・ ・ ・ ・ Floating gate P+ type impurity layer P- type impurity Layer Aluminum wiring layer Write voltage N- type semiconductor substrate N Raw impurity diffusion layer Ground potential Insulator layer Floating gate P Ten type impurity diffusion layer Aluminum wiring layer Write voltage 15... N- type semiconductor substrate 16... ...N0-type impurity diffusion layer 18...Ground potential 19...Insulator layer 31φ...Floating gate 32...
・P- type impurity diffusion layer 33... Gate electrode 34, 37, 40... Aluminum wiring layer 35... P-type impurity diffusion layer 36... P ten type impurity diffusion layer (drain) (writing voltage application terminal) 38...N- type semiconductor substrate 39...N native type impurity diffusion layer 41...Ground potential 42 ...Threshold voltage 43φ...Writing voltage 44...More than insulator layer

Claims (1)

[Claims] 1) a) A memory element comprising a floating gate for charge storage provided on a semiconductor substrate, and b) having only one semiconductor region having a polarity different from that of the semiconductor substrate as a data writing terminal. c) A floating gate type memory element, wherein the data writing semiconductor region is divided into two regions having different impurity concentrations, and one of the regions having a lower impurity concentration is located on the floating gate side.