JP2838925B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of obtaining a large signal voltage even if a MOS transistor which is a component for high integration is downsized.

[0002]

2. Description of the Related Art A semiconductor memory cell (hereinafter abbreviated as 1T cell) composed of one MOS transistor and one capacitor has a small number of components and can be easily miniaturized, so that it is widely used in highly integrated semiconductor memories. ing. This 1T
In the cell, the output voltage is proportional to the charge / discharge voltage difference of the capacitor. Here, the charge / discharge voltage difference is | V1-V0 | when the write voltages to the capacitors corresponding to the binary information are V0 and V1, respectively. Therefore, in order to highly integrate the 1T cell and to keep the output voltage at a sufficiently large value, it is necessary to reduce the size of the memory cell while maintaining a large charge / discharge voltage difference.

However, in order to reduce the size of the 1T cell,
It is necessary to reduce the size of the MOS transistor as a component thereof, and for that purpose, it is necessary to reduce the planar dimensions and the thickness of the gate insulator of the MOS transistor in accordance with the proportional reduction rule and to lower the operating voltage. Therefore, in the conventional 1T cell, the operating voltage, that is, 1
The difference in charge / discharge voltage for the T cell had to be reduced. As a result, the signal voltage from the downsized 1T cell has been reduced.

In order to keep the signal voltage from the 1T cell from lowering even if the size is reduced, it is necessary to reduce the charge / discharge voltage difference even if the MOS transistor is reduced. was there. However, as MOS transistors have become smaller and the gate insulator thickness has become smaller, this method has become impractical. This is because if the electric field applied to the gate insulator film increases to some extent, it is not possible to prevent reliability problems such as breakage of the gate insulator film.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the electric field applied to a gate insulator film of a MOS transistor even if the gate insulator film of the MOS transistor is thinned while keeping the charge / discharge voltage difference constant. An object of the present invention is to provide a semiconductor memory device capable of obtaining a large signal voltage even if the insulator film is reduced without reducing the reliability of the insulator film.

[0006]

According to the present invention, there is provided a semiconductor memory device comprising a memory cell comprising one MOS transistor and one capacitor, a word line connected to a gate electrode of the MOS transistor, and a selectable word line. Means for supplying the first voltage at the time and the second voltage at the time of the non-selection to control the conduction and cutoff of the MOS transistor, wherein the second voltage value is defined as the first voltage value.
By using the opposite sign, a depletion layer having a thickness of at least about the thickness of the gate insulating film is formed below the gate electrode when a maximum voltage is applied between the gate and the drain while the MOS transistor is shut off . Configuration.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a circuit diagram showing a semiconductor memory device of the present invention, showing a word line of the embodiment and a peripheral portion thereof. 101 in the figure is a word line,
102a and 102b are bit lines, 103a and 103b are switching-type enhancement nMOS transistors constituting a 1T cell, 104a and 104b are capacitors, and 105 is Von = 3V when a word line is selected, and Voff = -1V when non-selected. Word line driver,
Are respectively shown. In this embodiment, the MOS transistor 1
The threshold voltages Vth of 03a and 103b are about 0V, and the write voltages to the capacitors corresponding to the binary information are 0V and Von-Vth = 3V, respectively.

FIG. 1B is a sectional view showing the structure of the nMOS transistors 103a and 103b used in the circuit of FIG. 1A. In this figure, reference numeral 201 denotes a p-type silicon substrate; 202, an N-type high-concentration region serving as a drain (here, for convenience, connected to a capacitor);
3 is an N-type high-concentration region serving as a source; 204 is a gate electrode; 205 is a gate oxide film having a thickness of about 10 nm;
6,207, an N-type region having an impurity concentration of 10 ¹⁸ cm ⁻³ or less, and a drain 202 and a source 203, respectively.
And is provided below the gate electrode 204.

Reference numeral 208 denotes 3 V for the drain, 0 V for the source,
The equipotential lines showing the potential distribution when -1 V is applied to the gate electrode are shown. When such a voltage is applied, a depletion layer spreads from the surface of the MOS in the N-type region 206 as shown in the figure, and as a result, the voltage applied to the gate oxide film 205 becomes the maximum value Vo of the voltage applied between the gate and the drain.
It is reduced from n-Vth-Voff = 4V. The amount of reduction in the voltage applied to the gate oxide film 205 is determined by the division of the capacitance between the gate oxide film 205 and the depletion layer. Therefore, in order for the voltage reduction effect to have a substantial effect, it is necessary that the product of the thicknesses of the two and the relative permittivity be substantially the same. When the thickness of the depletion layer is extremely small, almost 4 V applied between the gate and the drain is applied to the gate oxide film 205, and the voltage reduction effect has no substantial effect.

The width of the depletion layer is determined by the concentration of the N-type region 206, the thickness of the gate oxide film 205, the flat band voltage of the MOS transistor, and the like. Assuming that the thickness of the gate oxide film 205 is 10 nm and the flat band voltage is 0 V, the width of the depletion layer is about 4.8 nm and 10 ¹⁹ when the impurity concentration of the N-type region 206 is 10 ¹⁸ cm ^−3. about 0.76nm when cm ^-3, is about 0.08nm when the 10 ²⁰ cm ^-3. From this, the impurity concentration of the N-type region is 10 ¹⁹ c
Above m ^-3 , the voltage reduction effect is small.

In the circuit shown in FIG. 1A, the threshold voltage of the nMOS transistor is 0 V, and the word line is
Since V is applied, 0 V (VO) or 3 V is applied to the memory cell.
(V1 = Von-Vth). Further, as for the voltage applied to the gate oxide film 205, there is a possibility that a maximum value of 4V may be applied when the gate voltage is -1V and the drain or source voltage is 3V, but actually, as described with reference to FIG. The N-type region 206 or 207 is depleted, and the voltage applied to the gate oxide film 205 becomes less than 4V.

In a conventional semiconductor memory device, the threshold voltage of an nMOS transistor is set to about 1 V, and OV and 3
In order to write V, 4 V or more was applied to the word line at the time of writing. In this case, there is a state where the source or the drain is 0 V and the gate is 4 V or more, and a voltage of 4 V or more is applied to the gate insulator film.

[0014]

As described above, in the semiconductor memory device of the present invention, the depletion layer is formed under the gate electrode when information "1" is written in a state where the MOS transistor forming the memory cell is cut off. Therefore, even if the write voltage difference is the same, the electric field applied to the gate insulating film of the MOS transistor can be reduced, so that a large signal voltage can be obtained without reducing the reliability of the gate insulating film even if the size is reduced. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram (FIG. 1 (a)) showing a word line and a peripheral portion thereof according to an embodiment of the present invention, which is used to explain a semiconductor memory device of the present invention; FIG. 1 is a cross-sectional view showing the structure of an nMOS transistor shown in FIG.
(B)).

[Explanation of symbols]

 101 Word line 102a, 102b Bit line 103a, 103b Capacitor 104a, 104b Bit line 105 Word line driver 201 P-type silicon substrate 202 Drain 203 Source 204 Gate electrode 205 Gate oxide film 206, 207 N-type region

Claims (1)

(57) [Claims] And 1. A memory cell comprising one MOS transistor and one capacitor, a word line connected to the gate electrode of the MOS transistor, a first voltage during selection to the word line, the second at the time of non-selection conduction of the MOS transistor by supplying a voltage, respectively, and means for controlling the cut-off, the first conductive said second voltage value
By setting the sign opposite to the pressure value, a depletion layer having a thickness of at least about the thickness of the gate insulating film is formed below the gate electrode when a maximum voltage is applied between the gate and the drain in a state where the MOS transistor is shut off. the semiconductor memory device being characterized in that as that.