JP3835455B2 - Driving method of nonvolatile latch - Google Patents

Description

  The present invention relates to a method for driving a nonvolatile latch, and more particularly to a method for driving a nonvolatile latch using a ferroelectric gate device.

  Semiconductor technology is being developed at a very rapid rate, and transistor miniaturization and circuit scale-up are advancing. However, there is a problem that power consumption increases due to an increase in leakage current of a fine transistor in a large scale integrated circuit.

  For this reason, attention has been focused on nonvolatile memories that retain information even when the power is turned off. By using a non-volatile memory, it is possible to reduce power consumption compared to a volatile memory such as SRAM or DRAM. In particular, a ferroelectric gate device having a MFMIS (Metal Ferroelectrics Metal Insulator Semiconductor) structure is composed of one transistor, and is expected as an ultimate memory.

  The ferroelectric gate device has a structure in which a ferroelectric thin film is formed as an insulating film between a floating gate electrode of the transistor and a control electrode which is an upper electrode of the transistor. The threshold value of the transistor is effectively changed by the spontaneous polarization generated in the ferroelectric thin film. Information is read by utilizing this phenomenon.

  A nonvolatile latch circuit using a ferroelectric gate device has been proposed in Patent Document 1. A schematic diagram of this circuit is shown in FIG. Ferroelectric gate devices each composed of the ferroelectric capacitor 101 and the n-type MOS transistor 104, and the ferroelectric capacitor 102 and the p-type MOS transistor 103 constitute an inverter.

  The relationship between input IN and output OUT is shown in FIG. Since the ferroelectric gate device constitutes an inverter, if the input value is “L”, the output value is “H”. If the input value is “H”, the output value is “L”. Furthermore, information is retained even when the power is turned off due to the spontaneous polarization of the ferroelectric.

As described above, the nonvolatile latch circuit using the ferroelectric gate device outputs a certain output value depending on the input value. Even when the power is turned off, the information is retained and is nonvolatile. In addition, Patent Documents 2 to 8 can be cited as prior art related to the present application. Patent Documents 2 to 4 disclose the basic configuration of a nonvolatile latch, and Patent Documents 5 to 8 disclose non-volatization by sandwiching a ferroelectric between a floating gate and a control electrode.
JP 2000-77986 A JP-A-2-199698 (especially FIG. 1) Japanese Examined Patent Publication No. 4-62159 (especially FIGS. 3 and 5) JP 10-510124 Gazette (especially front page) JP 11-54636 A (especially front page) Japanese Patent Laid-Open No. 11-8362 (especially front page) JP-A-10-27856 (especially front page) Japanese Patent Laid-Open No. 2002-358776 (especially front page)

  However, the conventional nonvolatile latch circuit as described above has the following problems.

  First, the magnitude of the voltage differs between when a positive voltage is applied to the input and when a negative voltage is applied. The voltage applied to the ferroelectric capacitor is used as a reference for the voltage at the floating terminal. When the input logical value is “H”, a positive voltage VFH determined by the coupling ratio of the ferroelectric capacitor and the capacitance Cox of the gate oxide film of the MOS transistor is applied to the ferroelectric capacitor. When the input logical value is “L”, a negative voltage VFL determined by the coupling ratio between the ferroelectric capacitor and the gate-source capacitance Cgs of the MOS transistor is applied to the ferroelectric capacitor. Since Cgs is much smaller than Cox, the size of VFL is larger than the size of VFH. Therefore, the polarization of the ferroelectric capacitor is easy to hold the input logic value “L”, but it is difficult to hold the input logic value “H”.

  Second, the signal delay is large. A ferroelectric capacitor is added to the gate capacitance of a normal MOS transistor. Since the gate capacitance of the MOS transistor is effectively increased, the delay of the signal from when a certain input value is input to when the output value is output increases.

  Therefore, the present inventors first devised the following nonvolatile latch circuit.

  FIG. 1 is a circuit diagram showing this nonvolatile latch circuit. In FIG. 1, 1 is a ferroelectric capacitor, 2 is a resistance element, and 3 is an n-type MOS transistor which is a first MOS transistor.

  As shown in FIG. 1, a ferroelectric capacitor 1 having a first input terminal CG that is a first terminal is connected to a floating gate FG that is a gate of an n-type MOS transistor 3. The resistance element 2 is connected to the drain of the n-type MOS transistor 3, and the connection terminal is used as the output terminal OG. The source of the n-type MOS transistor 3 is grounded, and the terminal other than the output terminal OG of the resistance element 2 is connected to the power source.

  By applying a positive voltage Vpp as a first voltage or a negative voltage −Vpp as a second voltage to the first input terminal CG, the polarization of the ferroelectric capacitor 1 is inverted, and the ferroelectric Information is written to the body capacitor 1. The operation principle will be described with reference to FIG.

  FIG. 2A shows an equivalent circuit of the ferroelectric capacitor 1 and the n-type MOS transistor 3. The ferroelectric capacitor 1 and the gate capacitance 3c of the n-type MOS transistor 3 are connected in series. As shown in FIG. 2A, the voltage Vf applied to the ferroelectric capacitor 1 is based on the floating gate FG, and the voltage Vox applied to the gate capacitance (Cox) 3c is based on the ground terminal. . Further, the charge induced in the ferroelectric capacitor 1 is Qf, and the charge induced in the gate capacitor 3c is Qox.

Now, assuming that the voltage Vpp is applied to the first input terminal CG,
Vpp = Vf + Vox (Formula 1)
It becomes. The charges induced in the lower electrode 1b of the ferroelectric capacitor 1 and the upper electrode 3a of the gate capacitor 3c are from the law of conservation of charge,
Qox−Qf = 0 (Formula 2)
It becomes. The charge Qox induced in the gate capacitance 3c is
Qox = CoxVox (Formula 3)
It becomes. Here, if (Equation 1) and (Equation 2) are substituted into (Equation 3),
Qf = Cox (Vpp−Vf) (Formula 4)
And corresponds to the straight line OX1 in FIG.

  On the other hand, the relationship between the charge Qf and the voltage Vf of the ferroelectric capacitor 1 shows a hysteresis characteristic as shown by a curve Ferro in FIG. An intersection A between the straight line OX1 and the curve Ferro is the ferroelectric charge Qf and the voltage Vf when the voltage Vpp is applied to the first input terminal CG. From this state, when the voltage of the first input terminal CG is returned to the ground, the straight line representing the gate capacitance becomes the straight line OX2 in FIG. An intersection B between the straight line OX2 and the curve Ferro is the charge Qf and the voltage Vf of the ferroelectric when the voltage Vpp is applied to the first input terminal CG and then returned to the ground. It can be seen from FIG. 2B that the voltage Vf at this time is −Vh. However, since the voltage Vf is based on the floating gate FG, the voltage of the floating gate FG becomes Vh when grounded.

  As described above, when the positive voltage Vpp is applied to the first input terminal CG and then returned to the ground, the positive voltage Vh is held in the floating gate FG due to the ferroelectric polarization and the voltage hysteresis characteristics. As can be seen from FIG. 2B, the magnitude of the holding voltage Vh depends on the shape of the curve Ferro, that is, the squareness ratio, the slope of the straight line Ox, that is, the gate capacitance, and the magnitude of the voltage applied to the first input terminal CG. Change. Similarly, when a negative voltage −Vpp is applied to the first input terminal CG and then returned to the ground, the negative voltage −Vh is held in the floating gate FG.

After applying a positive voltage Vpp to the first input terminal CG and then returning to the ground, the voltage Vh held in the floating gate FG must be set to be larger than the threshold value Vtn of the n-type MOS transistor 3. I must. The above settings can be achieved by appropriately determining the material, area, film thickness of the ferroelectric capacitor 1 and the gate capacitance of the n-type MOS transistor, that is, the gate area, the gate oxide film, and the voltage Vpp. Is possible. In this embodiment, as an example, strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ) is used as the material of the ferroelectric capacitor, its area is 30 [μm 2], and its film thickness is 300 [nm]. The gate area of the n-type MOS transistor is 500 [μm 2], the gate oxide film is 9 [nm], and the threshold Vtn is 0.2 [V]. The applied voltage Vpp was 5 [V]. The holding voltage Vh at this time is about 0.7 [V].

  Here, Vpp is set to 5 [V]. However, for the reason of saturating the polarization of the ferroelectric, the absolute value of the voltage Vpp applied to the control terminal may be equal to or higher than the power supply voltage Vdd which is a positive voltage. desirable. As an example, the power supply voltage Vdd is 3.3 [V].

  FIG. 3 is a timing chart of the circuit operation of such a nonvolatile latch circuit. At time t1, which is the first step, a positive voltage Vpp is applied to the first input terminal CG. At time t2, which is the second step after time t1, the voltage of the first input terminal CG is returned to ground. In this embodiment, as an example, 0 [V] is set. At this time, the voltage of the floating gate FG is maintained at Vh. Therefore, the n-type MOS transistor 3 is turned on, and a current of about 25 [μA] flows. By appropriately setting the resistance value of the resistance element 2, the logical value of the output terminal OG becomes “L”. In this embodiment, 1 [MΩ] is set as an example. Since the logical value “L” of the output terminal OG at time t2 is held by the polarization of the ferroelectric capacitor 1, it can be restored to the original state even when the power is turned off.

  At time t3, which is the third step after time t2, a negative voltage −Vpp is applied to the first input terminal CG. At time t4, which is the fourth step after time t4, the voltage of the first input terminal CG is returned to the ground, that is, 0 [V]. At this time, the voltage of the floating gate FG is kept at −Vh. Therefore, the n-type MOS transistor 3 is turned off. The logical value of the output terminal OG is “H”. Similarly, the logical value “H” of the output terminal OG at time t4 can be restored to the original state even when the power is turned off.

  Although the resistance value of the resistance element is 1 [MΩ] here, the resistance value is preferably between the channel resistance value in the on state and the channel resistance value in the off state of the n-type MOS transistor. The ON state here is a state in which the voltage Vh is held in the floating gate FG, and the OFF state is a state in which the voltage −Vh is held in the floating gate FG.

  As described above, the nonvolatile latch circuit applies a positive or negative voltage to the first input terminal CG and then returns to the ground, whereby the voltage of the floating gate FG is generated and the MOS transistor is controlled. The logic values “L” and “H” should be output according to the ON / OFF state of the transistor. Since this output value uses the polarization of the ferroelectric material, the information is retained even when the power is turned off.

  In Patent Document 1, the magnitudes of the positive and negative voltages applied to the ferroelectric capacitor are different. In this circuit operation, positive and negative voltages are applied to the first input terminal CG. The magnitudes of the positive and negative voltages applied to the ferroelectric capacitor are equal. Furthermore, since a voltage is not applied to the first input terminal CG in reading information when a positive or negative voltage is applied to the first input terminal CG and then returned to the ground, power consumption is reduced as compared with the conventional example. Can be made.

  However, the nonvolatile latch circuit shown in FIG. 1 has the following new problem.

  Even if the voltage Vpp is applied to the first input terminal CG to turn on the n-type MOS transistor 3, the ferroelectric gate device cannot take a large on / off ratio, and as a result, the output terminal OG. Voltage Vdd is always output, that is, the logical value “H” is always output.

  This problem will be specifically described with an example. It is assumed that the resistance of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off is about 100 times the resistance of the resistance element 2. In this case, since the resistance ratio of the resistance element 2: n-type MOS transistor 3 = 1: 100 is generated, the power supply voltage Vdd is directed to the output terminal OG, so that the high voltage Vdd is output as the logical value “H” to the output terminal OG. Is done.

  On the other hand, the magnitude of the resistance of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned on is about 10 times the magnitude of the resistance of the resistance element 2 and does not decrease. That is, under the above assumption, the resistance of the n-type MOS transistor 3 in the off state is 10. If it is a general MOS transistor, the on-state resistance is much smaller than the off-state resistance, so this problem does not occur. However, in a ferroelectric gate device, such an on / off ratio is increased. I can't take it.

  Turning on the n-type MOS transistor 3 means that a low voltage is output as a logical value “L” to the output terminal by allowing the power supply voltage to escape to the ground via the resistance element 2 and the n-type MOS transistor 3. However, as described above, since the resistance ratio of the resistance element 2: n-type MOS transistor 3 = 1: 10 is generated, the power supply voltage Vdd is directed to the output terminal OG. As a result, regardless of whether the n-type MOS transistor is on or off, the power supply voltage Vdd, which is a high voltage, is always output to the output terminal OG, and as a result, the logical value “H” is always output.

  The present inventors have found a problem inherent to such a ferroelectric gate device, and have completed the present invention to solve this problem.

The present invention for solving the above problems is a method of driving a nonvolatile latch,
This non-volatile latch
A ferroelectric capacitor 1;
n-type MOS transistor 3,
p-type MOS transistor 4 and
One end of the ferroelectric capacitor 1 is connected to the first input terminal CG,
The other end of the ferroelectric capacitor 1 is connected to the gate of the n-type MOS transistor 3,
The source of the n-type MOS transistor 3 is grounded,
An output terminal OG is connected to the drain of the n-type MOS transistor 3 and the drain of the p-type MOS transistor 4;
The second input terminal RG is connected to the gate of the p-type MOS transistor 4,
A positive voltage Vdd is input to the source of the p-type MOS transistor 4,
The driving method of the nonvolatile latch according to the present invention includes the following first step t5, second step t6, third step t7, and fourth step t8 in order,
In the first step t5, the first voltage Vpp is applied to the first input terminal CG to turn on the n-type MOS transistor 3, and the second input terminal so that the p-type MOS transistor 4 is turned off. Apply a second voltage Vdd to RG;
In the second step t6, the ground voltage is applied to the first input terminal CG to keep the n-type MOS transistor 3 in the on state, and the second voltage at the second input terminal RG is smaller than the second voltage Vdd. Voltage Vred1 is applied,
In the third step t7, a fourth voltage -Vpp having a polarity opposite to that of the first voltage Vpp is applied to the first input terminal CG to turn off the n-type MOS transistor 3, and the p-type MOS transistor 4 The fifth voltage Vdd is applied to the second input terminal RG so that is turned off,
In the fourth step t8, the ground voltage is applied to the first input terminal CG to maintain the n-type MOS transistor 3 in the OFF state, and the sixth voltage smaller than the second voltage Vdd is applied to the second input terminal RG. The voltage Vred2 is applied.

  The n-type field effect transistor 3 has the p-type field effect transistor 4 when the third voltage Vred1 is applied, rather than assuming that the resistance value of the n-type field effect transistor 3 is about 100 when the n-type field effect transistor 3 is off. When both of the resistance values are small and the resistance value of the n-type field effect transistor 3 is about 10 when the n-type field effect transistor 3 is on, the resistance value p is greater when the third voltage Vred1 is applied. The third voltage Vred1 is preferably set so that the resistance value of the type field effect transistor 4 increases.

  When the third voltage Vred1 is applied, the resistance value of the p-type field effect transistor 4 is different from the resistance value of the n-type field effect transistor 3 and the n-type field effect transistor 3 when the n-type field effect transistor 3 is off. It is preferably set to an intermediate value between the resistance value of the n-type field effect transistor 3 when the field effect transistor 3 is on.

  The third voltage Vred1 and the sixth voltage Vred2 are preferably the same potential.

  It is preferable that the absolute value of first voltage Vpp and the absolute value of fourth voltage -Vpp are the same.

  In the driving method of the nonvolatile latch circuit according to the present invention, a voltage smaller than the second voltage Vdd is applied to the second input terminal RG in the second step t6 when the n-type MOS transistor 3 is turned on. Thus, the resistance value of the p-type MOS transistor 4 can be set to an appropriate value. As a result, the resistance ratio between the p-type MOS transistor 4 and the n-type MOS transistor 3 can be set to an appropriate ratio. Therefore, when the n-type MOS transistor 3 is on, the power supply voltage is changed to the p-type MOS transistor. By letting it escape to the ground via the 4 and n-type MOS transistor 3, a low voltage can be output as the logical value “L” to the output terminal OG.

  In the driving method of the nonvolatile latch circuit of the present invention, after applying a positive or negative voltage to the first input terminal CG in the first step t5 and the third step t7, the second step t6 and the fourth step By returning to the ground at step t8, the voltage of the floating gate FG is generated, the n-type MOS transistor 3 is controlled, and the logical values “L” and “H” according to the on / off state of the n-type MOS transistor 3 Is output. Since this output value uses the polarization of the ferroelectric capacitor 1, the information is retained even when the power is turned off.

  In Patent Document 1, the magnitudes of the positive and negative voltages applied to the ferroelectric capacitor are different. However, in the circuit operation of the present invention, positive and negative voltages are applied to the first input terminal CG. The magnitudes of the positive and negative voltages applied to the ferroelectric capacitor 1 are equal.

  When a positive or negative voltage is applied to the first input terminal CG, the p-type MOS transistor 4 is turned off, so that current consumption can be reduced. Further, information obtained when a positive or negative voltage is applied to the first input terminal CG in the first step t5 and the third step t7 and then returned to the ground in the second step t6 and the fourth step t8. Since no voltage is applied to the first input terminal CG in reading, the power consumption can be reduced as compared with the conventional example.

(Configuration of nonvolatile latch circuit)
FIG. 4 is a circuit diagram showing the nonvolatile latch circuit according to the embodiment of the present invention. In FIG. 4, 1 is a ferroelectric capacitor, 3 is an n-type MOS transistor, and 4 is a p-type MOS transistor. One end (left side of FIG. 4) of the ferroelectric capacitor 1 is connected to the first input terminal CG. The other end of the ferroelectric capacitor 1 (the right side in FIG. 4) is connected to the gate of the n-type MOS transistor 3 via the floating gate FG. The source of the n-type MOS transistor 3 is grounded. An output terminal OG is connected to the drain of the n-type MOS transistor 3 and the drain of the p-type MOS transistor 4. A second input terminal RG is connected to the gate of the p-type MOS transistor 4. A positive voltage Vdd is input to the source of the p-type MOS transistor 4.

As described above, the circuit of this embodiment is almost the same as the circuit of FIG. The difference is that in this embodiment, a p-type MOS transistor 4 is used instead of the resistance element 2 in FIG. By using the p-type MOS transistor 4, current consumption can be reduced. When a positive voltage is applied to the first input terminal CG and information is written to the ferroelectric capacitor 1, a current flows through the resistance element 2 because the floating gate FG has a positive voltage in FIG. 1. However, in the circuit of this embodiment, when applying a positive voltage to the first input terminal CG, the p-type MOS transistor 4 is turned off to reduce current consumption during writing. One feature.
(Driving method of nonvolatile latch circuit)
FIG. 5 is a timing chart of the circuit operation of the nonvolatile latch circuit according to the embodiment of the present invention. The nonvolatile latch circuit driving method according to the first embodiment includes a first step t5, a second step t6, a third step t7, and a fourth step t8 in this order.
(About the first and second steps)
In the first step t5 (time t5), the first voltage Vpp is applied to the first input terminal CG to turn on the n-type MOS transistor 3, and the p-type MOS transistor 4 is turned off. A second voltage Vdd is applied to the second input terminal RG. Thereafter, in the second step t6 (time t6), the ground voltage is applied to the first input terminal CG to keep the n-type MOS transistor 3 on, and the second voltage is applied to the second input terminal RG. A third voltage Vred1 smaller than Vdd is applied.

  More specifically, at time t5, which is the first step, the p-type MOS transistor 4 is turned off by setting the voltage at the second input terminal RG to the power supply voltage Vdd, which is the second voltage. At the same time, the n-type MOS transistor 3 is turned on by applying a positive voltage Vpp to the first input terminal CG. At time t6, which is the second step after time t5, the voltage of the first input terminal CG is returned to ground. In the present embodiment, as an example, Vpp is 5 [V], Vdd is 3.3 [V], and the ground voltage is 0 [V].

  At time t6, since the ferroelectric capacitor 1 exists, the voltage of the floating gate FG is Vh (as an example, 2 to 3 [V]) even after the voltage of the first input terminal CG returns to the ground. Degree). Therefore, the n-type MOS transistor 3 is maintained in an ON state, and a current of about 25 [μA] flows in the above example. At this time, the voltage of the second input terminal RG of the p-type MOS transistor 4 is set to Vred1, which is the third voltage. By appropriately setting this Vred1, that is, by appropriately setting the channel resistance value of the p-type MOS transistor 4, the logical value of the output terminal OG becomes “L”.

  This will be described in detail. At this time t6, the p-type MOS transistor 4 is not completely turned on, but its channel resistance value is the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned on. Between the channel resistance value of the n-type MOS transistor 3 and the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off (preferably in the vicinity of the intermediate value, more preferably the intermediate value (that is, the average value)) Vred1 is set so that. At time t6, the n-type MOS transistor 3 is in the on state, so that the current from the power supply voltage Vdd is the p-type MOS transistor 4 (strictly the channel of the p-type MOS transistor 4) and the n-type MOS transistor 3 (strictly Flows through the channel of the n-type MOS transistor 3). Therefore, the logical value “L” is output to the output terminal OG.

  A more specific example will be described. At time t6, it is assumed that the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned on is 10, and the channel resistance of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off. Assume a value of 100. In this case, the channel resistance value of the p-type MOS transistor 4 at this time t6 is more than 10 and less than 100 (preferably about 50 which is near the intermediate value, more preferably the intermediate value (that is, the average value). 50), the third voltage Vred1 is set.

  In this way, the resistance ratio between the p-type MOS transistor 4 and the n-type MOS transistor 3 is set to an appropriate ratio (in the above preferred example, the resistance value of the p-type MOS transistor 4: the resistance value of the n-type MOS transistor 3 = 50: 10), when the n-type MOS transistor 3 is turned on, the power supply voltage is released to the ground via the p-type MOS transistor 4 and the n-type MOS transistor 3 to output A low voltage can be output as a logical value “L” to the terminal.

In this embodiment, as an example, the value of Vred1 is 2.5 [V]. Since the logical value “L” of the output terminal OG at time t6 is held by the polarization of the ferroelectric capacitor 1, it can be restored to the original state even when the power is turned off.
(About the third and fourth steps)
In the third step t7, the n-type MOS transistor 3 is turned off by applying a fourth voltage -Vpp having a polarity opposite to that of the first voltage Vpp to the first input terminal CG, and the p-type MOS The fifth voltage Vdd is applied to the second input terminal RG so that the transistor 4 is turned off.

  In the fourth step t8, the ground voltage is applied to the first input terminal CG to maintain the n-type MOS transistor 3 in the off state, and the second input terminal RG has a second voltage Vdd smaller than the second voltage Vdd. 6 voltage Vred2 is applied.

  At time t7, which is the third step after time t6, the voltage of the second input terminal RG is again set to the power supply voltage Vdd, the p-type transistor 4 is turned off, and then the fourth input to the first input terminal CG A negative voltage −Vpp is applied as the voltage of Here, although the absolute value (Vpp) of the fourth voltage and the absolute value (Vpp) of the first voltage are the same value, the first voltage turns on the n-type MOS transistor 3 at time t5. In addition, any value can be used as long as the ferroelectric capacitor 1 can maintain the state in which the n-type MOS transistor 3 is on even at the time t6 when the ground voltage is applied to the first input terminal CG. Similarly, the fourth voltage turns off the n-type MOS transistor 3 at time t7 and is also turned off at time t8 when the ground voltage is applied to the first input terminal CG. Any value that can be maintained is acceptable. Accordingly, the absolute value of the first voltage and the absolute value of the fourth voltage are not necessarily the same. However, when a voltage having the same polarity is applied to the ferroelectric capacitor 1, the polarization gradually and surely does not occur, and as a result, its life is shortened. Therefore, it is preferable that the absolute value (Vpp) of the fourth voltage and the absolute value (Vpp) of the first voltage be the same value from the viewpoint of always generating polarization and extending the lifetime.

  At time t8, which is the fourth step after time t7, the voltage of the first input terminal CG is returned to the ground, that is, 0 [V]. At this time, since the ferroelectric capacitor 1 exists, the voltage of the floating gate FG becomes −Vh. Therefore, the n-type MOS transistor 3 maintains the off state. Accordingly, the logical value of the output terminal OG is “H”.

  This will be described in detail. At time t8 as well as at time t6, the p-type MOS transistor 4 is not completely turned on, and the channel resistance value is the n-type MOS when the n-type MOS transistor 3 is turned on. A value between the channel resistance value of the transistor 3 and the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off (preferably near an intermediate value (more preferably an intermediate value)). In addition, Vred 2 is input to the gate of the p-type MOS transistor 4. At time t8, since the n-type MOS transistor 3 is in the off state, the resistance is higher than that of the p-type MOS transistor 4. Therefore, the power supply voltage from Vdd tends to flow from the p-type MOS transistor 4 (strictly, the channel of the p-type MOS transistor 4) toward the output terminal OG. Therefore, “H” is output to the output terminal OG.

  When the n-type MOS transistor 3 is off, it is not always necessary to set the resistance value of the n-type MOS transistor 3 as described above. This is because the p-type MOS transistor 4 is not completely turned on, and a certain amount of current flows from the power supply terminal to the output terminal OG without flowing through the n-type MOS transistor 3, so that the logical value “H” becomes the output terminal OG. Is output. As long as this is the case, the resistance value (strictly, the channel resistance value) of the p-type MOS transistor 4 turned off at time t8 should be larger than the resistance value of the p-type MOS transistor 4 turned on. Because it is good.

  However, from the viewpoint of surely outputting the logical value “H” to the output terminal OG at time t8 and facilitating the circuit configuration, as described above, the p-type MOS is also at time t8 as at time t6. The channel resistance value of the transistor 4 is the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned on, and the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off. It is preferable that Vred2 is input to the gate of the p-type MOS transistor 4 so as to be a value between 1 and 2 (preferably near an intermediate value (more preferably an intermediate value)). In this case, the third voltage Vred1 and the sixth voltage Vred2 are the same as shown as Vred in FIG.

  Similarly, the logical value “H” of the output terminal OG at time t8 can be restored to the original state even when the power is turned off. The term “on state” used in this specification refers to a state in which the n-type MOS transistor 3 (the channel thereof) has a low resistance because the voltage Vh is held in the floating gate FG. Similarly, the “off state” refers to a state in which the n-type MOS transistor 3 (channel) has a high resistance because the voltage of −Vh is held in the floating gate FG.

  As described above, the nonvolatile latch circuit according to the embodiment of the present invention uses the p-type MOS transistor 4 so that the p-type MOS transistor 4 is not completely turned on at time t6 (preferably time t6 and time t8). By controlling this, the logical value “L” can be reliably output to the output terminal OG when the n-type MOS transistor 3 is on. The logic values “H” and “L” output to these output terminals OG, including that the logic value “H” is output to the output terminals, use the polarization of the ferroelectric capacitor 1. Even if the power is cut off, the information is retained. In the conventional example, the magnitudes of the positive and negative voltages applied to the ferroelectric capacitor are different, but in the circuit operation of the present embodiment, positive and negative voltages are applied to the first input terminal CG. Therefore, the magnitudes of the positive and negative voltages applied to the ferroelectric capacitor 1 are equal.

  Further, when a positive or negative voltage is applied to the first input terminal CG, the p-type MOS transistor 4 is turned off, so that current consumption can be reduced. Furthermore, since a voltage is not applied to the first input terminal CG in reading information when a positive or negative voltage is applied to the first input terminal CG and then returned to the ground, power consumption is reduced as compared with the conventional example. Can be made.

  In the present embodiment, a MOS transistor is used as the MOS transistor, but it goes without saying that the circuit operation of the present embodiment can be obtained as long as the transistor is controlled by voltage. For example, a junction MOS transistor (JFET) can be operated. Although the resistance element is used in the present embodiment, a resistance change element using a phase change material or the like may be used.

(Application example of the present invention)
FIG. 6 is a circuit diagram showing a semiconductor circuit of an application example of the present invention. 5 is a pass transistor, 6 is a first logic circuit, and 7 is a second logic circuit.

  As shown in FIG. 6, the output of the first logic circuit 6 is connected to the input terminal IN of the pass transistor 5, and the input of the second logic circuit 7 is connected to the output terminal OUT of the pass transistor 5. Further, the output terminal OG of the nonvolatile latch circuit of FIG. 1 of the present invention is connected to the gate of the pass transistor 5, and the signal of the logic circuit is controlled by the nonvolatile latch circuit.

  When the output of the nonvolatile latch circuit is “L”, the logic circuits are disconnected and no logic signal is transmitted. When the output of the nonvolatile latch circuit is “H”, the logic circuits are connected and a logic signal is transmitted. Information written in the nonvolatile latch circuit is nonvolatile and is retained even when the power is turned off.

  As shown in FIG. 7, the nonvolatile latch circuit shown in FIG. 4 can be used instead of the nonvolatile latch circuit of FIG. Thereby, the current consumption at the time of writing can be further reduced.

  As described above, in this embodiment, the logic signal is controlled by the pass transistor, and the control information is held in the nonvolatile latch circuit, so that it can be restored even when the power is turned off. In addition, since the logic signal and the signal for controlling the nonvolatile latch circuit are separated, the logic signal is not delayed as in the conventional example, and it is possible to increase the speed.

  In the present embodiment, a pass transistor is used as an element for controlling a logic signal. However, the present invention is not limited to this. The element connected to the output of the nonvolatile latch circuit may be any semiconductor element as long as it is a semiconductor element that controls a logic signal. For example, a buffer that is an inverter may be connected to the output of the nonvolatile latch circuit.

  As described above, according to the present invention, there is provided a method for driving a nonvolatile latch circuit including a ferroelectric gate device that can output not only a logical value “H” but also a logical value “L”. The

The figure which shows the non-volatile latch circuit which was first devised by the present inventors (A) A diagram for explaining the operating principle of the present invention (a) A diagram showing an equivalent circuit of a ferroelectric capacitor and an N-type MOS transistor (b) A graph showing the charge-voltage characteristics of the ferroelectric capacitor Ferro and the gate capacitance Ox. Figure Timing chart of voltage at each terminal of the nonvolatile latch circuit shown in FIG. The figure which shows the circuit of embodiment of this invention Timing chart of voltage at each terminal of the circuit according to the embodiment of the present invention The figure which shows the circuit of the application example of this invention The figure which shows the circuit of the application example of this invention Diagram showing prior art circuit Timing chart of voltage at each terminal of the circuit of the prior art

Explanation of symbols

1: Ferroelectric capacitor 3: n-type MOS transistor 4: p-type MOS transistor CG: first input terminal RG: second input terminal OG: output terminal t5: first step (time t5)
t6: Second step (time t6)
t7: Second step (time t7)
t8: Second step (time t8)
Vpp: first voltage Vdd: second voltage, fifth voltage, positive voltage (power supply voltage)
Vred1: third voltage -Vpp: fourth voltage Vred2: sixth voltage

Claims (5)

A non-volatile latch driving method comprising:
The nonvolatile latch is
A ferroelectric capacitor;
an n-type MOS transistor;
a p-type MOS transistor,
One end of the ferroelectric capacitor is connected to a first input terminal;
The other end of the ferroelectric capacitor is connected to the gate of the n-type MOS transistor,
The source of the n-type MOS transistor is grounded,
An output terminal is connected to the drain of the n-type MOS transistor and the drain of the p-type MOS transistor,
A second input terminal is connected to the gate of the p-type MOS transistor;
A positive voltage is input to the source of the p-type MOS transistor,
The nonvolatile latch driving method includes a first step, a second step, a third step, and a fourth step in order,
In the first step, a first voltage is applied to the first input terminal to turn on the n-type MOS transistor, and the second input terminal so that the p-type MOS transistor is turned off. A second voltage is applied to
In the second step, a ground voltage is applied to the first input terminal to maintain the n-type MOS transistor in an on state, and a third voltage lower than the second voltage is applied to the second input terminal. Apply a voltage of
In the third step, a fourth voltage having a polarity opposite to that of the first voltage is applied to the first input terminal to turn off the n-type MOS transistor, and the p-type MOS transistor is turned off. A fifth voltage is applied to the second input terminal so that
In the fourth step, a ground voltage is applied to the first input terminal to maintain the off state of the n-type MOS transistor, and a sixth voltage smaller than the second voltage is applied to the second input terminal. Apply a voltage of. Any of the resistance values of the p-type field effect transistor when the third voltage is applied than the resistance value of the n-type field effect transistor when the n-type field effect transistor is off. Thigh is small,
The resistance value of the p-type field effect transistor is greater when the third voltage is applied than the resistance value of the n-type field effect transistor when the n-type field effect transistor is on. The method for driving a nonvolatile latch according to claim 1, wherein the third voltage is set.   The resistance value of the p-type field effect transistor when the third voltage is applied is the resistance value of the n-type field effect transistor when the n-type field effect transistor is off and the resistance value n The driving method of the non-volatile latch according to claim 2, wherein the non-volatile latch is set to an intermediate value between a resistance value of the n-type field effect transistor when the type field effect transistor is on.   4. The method for driving a nonvolatile latch according to claim 1, wherein the third voltage and the sixth voltage are voltages having the same potential.   5. The method of driving a nonvolatile latch according to claim 1, wherein an absolute value of the first voltage and an absolute value of the fourth voltage are the same. 6.

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