JP2004273099A - Driving method of nonvolatile latch - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a trouble that a logical value "H" is always outputted to an output terminal OG independently of on/off of a (n) type MOS transistor in a conventional nonvolatile latch circuit using a ferroelectric gate capacitor. <P>SOLUTION: A nonvolatile latch circuit is provided with a ferroelectric capacitor 1, a n type MOS transistor 3, and a p type MOS transistor 4, and after the n type MOS transistor 3 is turned on, third voltage Vred1 being smaller than second voltage Vdd which completely turns on the p type MOS transistor 4 is applied to a second input terminal RG connected to a gate of the p type MOS transistor 4. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a method for driving a nonvolatile latch, and more particularly, to a method for driving a nonvolatile latch using a ferroelectric gate device.

  Semiconductor technology is evolving at a very rapid rate, with miniaturization of transistors and large-scale circuits. However, there is a problem that power consumption increases due to an increase in leakage current of a fine transistor in a large-scale integrated circuit.

  For this reason, non-volatile memories that retain information even when the power is turned off are receiving attention. By using a nonvolatile memory, power consumption can be reduced as compared with a volatile memory such as an SRAM or a DRAM. In particular, a ferroelectric gate device having a MFMIS (Metal Ferroelectrics Metal Insulator Semiconductor) structure is expected to be the ultimate memory because it is composed of one transistor.

  The ferroelectric gate device has a structure in which, in a floating gate transistor, a ferroelectric thin film is formed as an insulating film between a floating gate electrode of the transistor and a control electrode which is an upper electrode thereof. The spontaneous polarization generated in the ferroelectric thin film effectively changes the threshold value of the transistor. By utilizing this phenomenon, information is read.

  A nonvolatile latch circuit using a ferroelectric gate device has been proposed in Patent Document 1. FIG. 8 shows a schematic diagram of this circuit. A ferroelectric gate device constituted by the ferroelectric capacitor 101 and the n-type MOS transistor 104 and a ferroelectric gate device constituted by the ferroelectric capacitor 102 and the p-type MOS transistor 103 constitute an inverter.

  FIG. 9 shows the relationship between the input IN and the output OUT. Since the ferroelectric gate device forms an inverter, if the input value is “L”, the output value is “H”. If the input value is “H”, the output value is “L”. Further, the information is retained even when the power is turned off due to the spontaneous polarization of the ferroelectric.

As described above, the nonvolatile latch circuit using the ferroelectric gate device outputs a certain output value depending on the input value. Even when the power is turned off, the information is retained and has non-volatility. In addition, Patent Documents 2 to 8 can be cited as prior arts related to the present application. Patent Documents 2 to 4 disclose the basic configuration of a nonvolatile latch, and Patent Documents 5 to 8 disclose non-volatization by interposing a ferroelectric substance between a floating gate and a control electrode.
JP-A-2000-77986 JP-A-2-199698 (especially FIG. 1) Japanese Patent Publication No. 4-62159 (especially, FIGS. 3 and 5) Japanese Patent Publication No. 10-510124 (particularly front page) JP-A-11-54636 (especially front page) JP-A-11-8362 (especially front page) JP-A-10-27856 (particularly front page) JP-A-2002-358776 (particularly front page)

  However, the conventional nonvolatile latch circuit as described above has the following problems.

  First, the magnitude of the voltage applied to the ferroelectric differs between when a positive voltage is applied to the input and when a negative voltage is applied. The voltage applied to the ferroelectric capacitor is used as a reference for the voltage of the floating terminal. When the input logic value is "H", a positive voltage VFH determined by the coupling ratio of the ferroelectric capacitor and the capacitance Cox of the gate oxide film of the MOS transistor is applied to the ferroelectric capacitor. When the input logic value is "L", a negative voltage VFL determined by the coupling ratio between the ferroelectric capacitor and the capacitance Cgs between the gate and the source of the MOS transistor is applied to the ferroelectric capacitor. Since Cgs is much smaller than Cox, the size of VFL is larger than the size of VFH. Therefore, for the polarization of the ferroelectric capacitor, the logical value “L” of the input is easily held, but the logical value “H” of the input is hardly held.

  Second, the signal delay is large. A ferroelectric capacitor is added to the gate capacitance of a normal MOS transistor. Since the gate capacitance of the MOS transistor is effectively increased, a signal delay from when a certain input value is input to when an output value is output increases.

  Therefore, the present inventors first devised the following nonvolatile latch circuit.

  FIG. 1 is a circuit diagram showing the nonvolatile latch circuit. In FIG. 1, 1 is a ferroelectric capacitor, 2 is a resistance element, and 3 is an n-type MOS transistor as a first MOS transistor.

  As shown in FIG. 1, a ferroelectric capacitor 1 having a first input terminal CG as a first terminal is connected to a floating gate FG as a gate of an n-type MOS transistor 3. The resistance element 2 is connected to the drain of the n-type MOS transistor 3, and the connection terminal is used as an output terminal OG. The source of the n-type MOS transistor 3 is grounded, and a terminal other than the output terminal OG of the resistance element 2 is connected to a power supply.

  By applying a positive voltage Vpp as a first voltage or a negative voltage −Vpp as a second voltage to the first input terminal CG, the polarization of the ferroelectric capacitor 1 is inverted, and the ferroelectric capacitor 1 is turned on. Information is written to the body capacitor 1. The operation principle will be described with reference to FIG.

  FIG. 2A shows an equivalent circuit of the ferroelectric capacitor 1 and the n-type MOS transistor 3. The ferroelectric capacitor 1 and the gate capacitance 3c of the n-type MOS transistor 3 are connected in series. As shown in FIG. 2A, the voltage Vf applied to the ferroelectric capacitor 1 is based on the floating gate FG, and the voltage Vox applied to the gate capacitance (Cox) 3c is based on the ground terminal. . The charge induced in the ferroelectric capacitor 1 is Qf, and the charge induced in the gate capacitance 3c is Qox.

Now, assuming that the voltage Vpp is applied to the first input terminal CG,
Vpp = Vf + Vox (Equation 1)
It becomes. The electric charge induced in the lower electrode 1b of the ferroelectric capacitor 1 and the upper electrode 3a of the gate capacitor 3c is calculated according to the charge conservation law.
Qox−Qf = 0 (Equation 2)
It becomes. The charge Qox induced in the gate capacitance 3c is
Qox = CoxVox (Equation 3)
It becomes. Here, by substituting (Equation 1) and (Equation 2) into (Equation 3),
Qf = Cox (Vpp-Vf) (Equation 4)
And corresponds to the straight line OX1 in FIG.

  On the other hand, the relationship between the charge Qf of the ferroelectric capacitor 1 and the voltage Vf shows a hysteresis characteristic as shown by a curve Ferro in FIG. The intersection A between the straight line OX1 and the curve Ferro is the charge Qf and the voltage Vf of the ferroelectric when the voltage Vpp is applied to the first input terminal CG. When the voltage of the first input terminal CG is returned to ground from this state, the straight line representing the gate capacitance becomes the straight line OX2 in FIG. 2B. The intersection B between the straight line OX2 and the curve Ferro is the charge Qf and the voltage Vf of the ferroelectric when the voltage Vpp is applied to the first input terminal CG and then the ground is returned to the ground. FIG. 2B shows that the voltage Vf at this time is −Vh. However, since the voltage Vf is based on the floating gate FG, the voltage of the floating gate FG becomes Vh with respect to the ground.

  As described above, when the positive voltage Vpp is applied to the first input terminal CG and then returned to the ground, the positive voltage Vh is held at the floating gate FG due to the polarization of the ferroelectric and the hysteresis characteristics of the voltage. As can be seen from FIG. 2B, the magnitude of the holding voltage Vh depends on the shape of the curve Ferro, ie, the squareness ratio, the slope of the straight line Ox, ie, the gate capacitance, and the magnitude of the voltage applied to the first input terminal CG. Change. Similarly, when a negative voltage -Vpp is applied to the first input terminal CG and then returned to the ground, the negative voltage -Vh is held at the floating gate FG.

After applying a positive voltage Vpp to the first input terminal CG and then returning it to ground, the voltage Vh held by the floating gate FG must be set to be higher than the threshold value Vtn of the n-type MOS transistor 3. Must. The above setting can be achieved by appropriately determining the material, area, and film thickness of the ferroelectric capacitor 1 and the gate capacitance of the n-type MOS transistor, that is, the gate area, the gate oxide film, and the magnitude of the voltage Vpp. It is possible. In the present embodiment, as an example, strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ) is used as the material of the ferroelectric capacitor, the area is 30 [μm 2], and the film thickness is 300 [nm]. The gate area of the n-type MOS transistor was 500 [μm2], the gate oxide film was 9 [nm], and the threshold value Vtn was 0.2 [V]. The applied voltage Vpp was set to 5 [V]. The holding voltage Vh at this time is about 0.7 [V].

  Although Vpp is set to 5 [V] here, the absolute value of the voltage Vpp applied to the control terminal may be equal to or higher than the positive power supply voltage Vdd because the polarization of the ferroelectric is saturated. desirable. As an example, the power supply voltage Vdd is set to 3.3 [V].

  FIG. 3 is a timing chart of the circuit operation of such a nonvolatile latch circuit. At time t1, which is the first step, a positive voltage Vpp is applied to the first input terminal CG. At a time t2 which is a second step after the time t1, the voltage of the first input terminal CG is returned to the ground. In the present embodiment, it is set to 0 [V] as an example. At this time, the voltage of the floating gate FG is maintained at Vh. Therefore, n-type MOS transistor 3 is turned on, and a current of about 25 [μA] flows. By appropriately setting the resistance value of the resistance element 2, the logical value of the output terminal OG becomes “L”. In the present embodiment, it is set to 1 [MΩ] as an example. Since the logic value "L" of the output terminal OG at the time t2 is held by the polarization of the ferroelectric capacitor 1, it is possible to return to the original state even if the power is cut off.

  At a time t3, which is a third step after the time t2, a negative voltage -Vpp is applied to the first input terminal CG. At a time t4, which is a fourth step after the time t4, the voltage of the first input terminal CG is returned to the ground, that is, 0 [V]. At this time, the voltage of the floating gate FG is maintained at -Vh. Therefore, n-type MOS transistor 3 is turned off. The logical value of the output terminal OG becomes “H”. The logic value "H" of the output terminal OG at the time t4 can also be returned to the original state even if the power is cut off.

  Here, the resistance value of the resistance element is set to 1 [MΩ], but it is preferable that the resistance value be between the channel resistance value in the ON state and the channel resistance value in the OFF state of the n-type MOS transistor. Here, the ON state is a state in which the voltage of Vh is held in the floating gate FG, and the OFF state is a state in which the voltage of -Vh is held in the floating gate FG.

  As described above, this nonvolatile latch circuit applies a positive or negative voltage to the first input terminal CG and then returns to the ground, thereby generating the voltage of the floating gate FG and controlling the MOS transistor. Logic values "L" and "H" should be output according to the ON / OFF state of the transistor. Since this output value uses the polarization of the ferroelectric, the information is retained even when the power is turned off.

  Further, in Patent Document 1, the magnitudes of the positive and negative voltages applied to the ferroelectric capacitor are different. However, in this circuit operation, since the positive and negative voltages are applied to the first input terminal CG, The magnitudes of the positive and negative voltages applied to the ferroelectric capacitor are equal. Further, in reading information when a positive or negative voltage is applied to the first input terminal CG and then returned to the ground, no voltage is applied to the first input terminal CG. Can be done.

  However, the nonvolatile latch circuit shown in FIG. 1 has the following new problem.

  Even if the voltage Vpp is applied to the first input terminal CG to turn on the n-type MOS transistor 3, the on / off ratio cannot be made large in the ferroelectric gate device, and as a result, the output terminal OG , The voltage Vdd is always output, that is, the logical value “H” is always output.

  This problem will be specifically described with an example. It is assumed that the resistance of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off is about 100 times the resistance of the resistance element 2. In this case, since the resistance ratio of the resistance element 2: the n-type MOS transistor 3 = 1: 100 occurs, the power supply voltage Vdd goes to the output terminal OG, and the high voltage Vdd is output to the output terminal OG as a logical value “H”. Is done.

  On the other hand, when the n-type MOS transistor 3 is turned on, the resistance of the n-type MOS transistor 3 does not decrease to about 10 times the resistance of the resistance element 2. That is, under the above assumption, the resistance of the n-type MOS transistor 3 when it is off is 10. In the case of a general MOS transistor, such a problem does not occur because the resistance at the time of on is much smaller than the resistance at the time of off, but in a ferroelectric gate device, such an on / off ratio is increased. I can't take it.

  Turning on the n-type MOS transistor 3 means that a low voltage is output as a logical value “L” to the output terminal by releasing the power supply voltage to the ground via the resistance element 2 and the n-type MOS transistor 3. However, as described above, since the resistance ratio of the resistance element 2: the n-type MOS transistor 3 = 1: 10 is generated, the power supply voltage Vdd goes to the output terminal OG. As a result, regardless of whether the n-type MOS transistor is on or off, the power supply voltage Vdd, which is a high voltage, is always output to the output terminal OG, and as a result, the logical value "H" is always output.

  The present inventors have found a problem unique to such a ferroelectric gate device, and have completed the present invention in order to solve this problem.

The present invention for solving the above problems is a method for driving a nonvolatile latch,
This non-volatile latch is
A ferroelectric capacitor 1;
an n-type MOS transistor 3,
and a p-type MOS transistor 4.
One end of the ferroelectric capacitor 1 is connected to a first input terminal CG,
The other end of the ferroelectric capacitor 1 is connected to the gate of the n-type MOS transistor 3,
The source of the n-type MOS transistor 3 is grounded,
An output terminal OG is connected to the drain of the n-type MOS transistor 3 and the drain of the p-type MOS transistor 4,
The second input terminal RG is connected to the gate of the p-type MOS transistor 4, and
The positive voltage Vdd is input to the source of the p-type MOS transistor 4,
A method for driving a nonvolatile latch according to the present invention includes the following first step t5, second step t6, third step t7, and fourth step t8 in order,
In a first step t5, a first voltage Vpp is applied to the first input terminal CG to turn on the n-type MOS transistor 3 and turn off the p-type MOS transistor 4 so that the second input terminal is turned off. Applying a second voltage Vdd to RG,
In the second step t6, the ground voltage is applied to the first input terminal CG to maintain the ON state of the n-type MOS transistor 3, and the third input terminal RG is connected to the third input terminal RG at a voltage lower than the second voltage Vdd. Voltage Vred1 is applied,
In a third step t7, a fourth voltage -Vpp having a polarity opposite to the first voltage Vpp is applied to the first input terminal CG to turn off the n-type MOS transistor 3 and turn off the p-type MOS transistor 4 Is turned off, a fifth voltage Vdd is applied to the second input terminal RG,
In the fourth step t8, the ground voltage is applied to the first input terminal CG to maintain the off state of the n-type MOS transistor 3, and the second input terminal RG is connected to the sixth input terminal RG which is lower than the second voltage Vdd. Is applied.

  When the third voltage Vred1 is applied, the p-type field-effect transistor 4 has a lower resistance than the assumption that the resistance of the n-type field-effect transistor 3 is about 100 when the n-type field-effect transistor 3 is off. When the third voltage Vred1 is applied, when the third voltage Vred1 is applied, when the third voltage Vred1 is applied, the resistance value is smaller than the resistance value of the n-type field-effect transistor 3 when the n-type field-effect transistor 3 is on. Voltage Vred1 is preferably set such that the resistance value of type field effect transistor 4 increases.

  The resistance value of the p-type field effect transistor 4 when the third voltage Vred1 is applied is equal to the resistance value of the n-type field effect transistor 3 when the n-type field effect transistor 3 is off and the n-type field-effect transistor 3. It is preferable that the resistance value is set to an intermediate value between the resistance value of the n-type field effect transistor 3 when the field effect transistor 3 is turned on.

  It is preferable that the third voltage Vred1 and the sixth voltage Vred2 have the same potential.

  It is preferable that the absolute value of the first voltage Vpp and the absolute value of the fourth voltage −Vpp are the same.

  In the driving method of the nonvolatile latch circuit according to the present invention, a voltage smaller than the second voltage Vdd is applied to the second input terminal RG in the second step t6 when the n-type MOS transistor 3 is turned on. By doing so, the resistance value of p-type MOS transistor 4 can be set to an appropriate value. This makes it possible to set the resistance ratio between the p-type MOS transistor 4 and the n-type MOS transistor 3 to an appropriate ratio. Therefore, when the n-type MOS transistor 3 is turned on, the power supply voltage is reduced to the p-type MOS transistor. 4 and the n-type MOS transistor 3 allow the output terminal OG to output a low voltage as a logical value “L” by escaping to ground.

  In the method for driving the nonvolatile latch circuit according to the present invention, after the positive or negative voltage is applied to the first input terminal CG in the first step t5 and the third step t7, the second step t6 and the fourth step By returning the voltage to the ground at step t8, the voltage of the floating gate FG is generated to control the n-type MOS transistor 3, and the logical values "L" and "H" according to the on / off state of the n-type MOS transistor 3. Is output. Since this output value uses the polarization of the ferroelectric capacitor 1, the information is retained even when the power is turned off.

  In Patent Document 1, the magnitudes of the positive and negative voltages applied to the ferroelectric capacitor are different. However, in the circuit operation of the present invention, since the positive and negative voltages are applied to the first input terminal CG, The magnitudes of the positive and negative voltages applied to the ferroelectric capacitor 1 are equal.

  When a positive or negative voltage is applied to the first input terminal CG, the p-type MOS transistor 4 is turned off, so that current consumption can be reduced. Furthermore, after a positive or negative voltage is applied to the first input terminal CG in the first step t5 and the third step t7, the information is returned to the ground in the second step t6 and the fourth step t8. In the read operation, no voltage is applied to the first input terminal CG, so that power consumption can be reduced as compared with the conventional example.

(Configuration of nonvolatile latch circuit)
FIG. 4 is a circuit diagram showing a nonvolatile latch circuit according to the embodiment of the present invention. In FIG. 4, 1 is a ferroelectric capacitor, 3 is an n-type MOS transistor, and 4 is a p-type MOS transistor. One end (the left side in FIG. 4) of the ferroelectric capacitor 1 is connected to the first input terminal CG. The other end (the right side in FIG. 4) of the ferroelectric capacitor 1 is connected to the gate of the n-type MOS transistor 3 via the floating gate FG. The source of the n-type MOS transistor 3 is grounded. The output terminal OG is connected to the drain of the n-type MOS transistor 3 and the drain of the p-type MOS transistor 4. The second input terminal RG is connected to the gate of the p-type MOS transistor 4. The positive voltage Vdd is input to the source of the p-type MOS transistor 4.

As described above, the circuit of this embodiment is almost the same as the circuit of FIG. The difference is that a p-type MOS transistor 4 is used in this embodiment instead of the resistance element 2 in FIG. By using the p-type MOS transistor 4, current consumption can be reduced. When a positive voltage is applied to the first input terminal CG to write information in the ferroelectric capacitor 1, the floating gate FG has a positive voltage in FIG. However, in the circuit according to the present embodiment, when a positive voltage is applied to the first input terminal CG, the current consumption at the time of writing can be reduced by turning off the p-type MOS transistor 4. This is one feature.
(Driving method of nonvolatile latch circuit)
FIG. 5 is a timing chart of the circuit operation of the nonvolatile latch circuit according to the embodiment of the present invention. The method for driving the nonvolatile latch circuit according to the first embodiment includes a first step t5, a second step t6, a third step t7, and a fourth step t8 in this order.
(About the first and second steps)
In the first step t5 (time t5), the n-type MOS transistor 3 is turned on by applying the first voltage Vpp to the first input terminal CG, and the p-type MOS transistor 4 is turned off. The second voltage Vdd is applied to the second input terminal RG. Thereafter, in a second step t6 (time t6), the ground voltage is applied to the first input terminal CG to keep the n-type MOS transistor 3 on, and the second voltage is applied to the second input terminal RG. A third voltage Vred1 smaller than Vdd is applied.

  More specifically, at time t5, which is the first step, the voltage of the second input terminal RG is set to the power supply voltage Vdd, which is the second voltage, so that the p-type MOS transistor 4 is turned off. At the same time, the n-type MOS transistor 3 is turned on by applying a positive voltage Vpp to the first input terminal CG. At a time t6 which is a second step after the time t5, the voltage of the first input terminal CG is returned to the ground. In the present embodiment, as an example, Vpp is 5 [V], Vdd is 3.3 [V], and the ground voltage is 0 [V].

  At time t6, since the ferroelectric capacitor 1 exists, even after the voltage of the first input terminal CG returns to the ground, the voltage of the floating gate FG becomes Vh (for example, 2 to 3 [V]). Degree) is held. Therefore, the n-type MOS transistor 3 is kept on, and in the above example, a current of about 25 [μA] flows. At this time, the voltage of the second input terminal RG of the p-type MOS transistor 4 is set to the third voltage Vred1. By appropriately setting Vred1, that is, by appropriately setting the channel resistance value of the p-type MOS transistor 4, the logical value of the output terminal OG becomes “L”.

  This will be described in detail. At this time t6, the p-type MOS transistor 4 is not completely turned on, but the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned on is changed. Between the channel resistance value of the n-type MOS transistor 3 and the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off (preferably near the intermediate value, more preferably the intermediate value (that is, the average value)). ) Is set. At time t6, since n-type MOS transistor 3 is on, current from power supply voltage Vdd is applied to p-type MOS transistor 4 (strictly, the channel of p-type MOS transistor 4) and n-type MOS transistor 3 (strictly). Flows through the channel of the n-type MOS transistor 3). Therefore, the logical value “L” is output to the output terminal OG.

  A more specific example will be described. At time t6, the channel resistance of n-type MOS transistor 3 when n-type MOS transistor 3 is turned on is assumed to be 10, and the channel resistance of n-type MOS transistor 3 when n-type MOS transistor 3 is turned off is assumed. Assume a value of 100. In this case, the channel resistance value of the p-type MOS transistor 4 at the time t6 is set to be more than 10 and less than 100 (preferably at about 50 which is near the intermediate value, more preferably at the intermediate value (that is, the average value). 50)), the third voltage Vred1 is set.

  In this case, the resistance ratio between the p-type MOS transistor 4 and the n-type MOS transistor 3 is set to an appropriate ratio (in the more preferable example, the resistance value of the p-type MOS transistor 4: the resistance value of the n-type MOS transistor 3). = 50: 10), the power supply voltage is released to the ground via the p-type MOS transistor 4 and the n-type MOS transistor 3 when the n-type MOS transistor 3 is on, so that the output A low voltage can be output to the terminal as a logical value “L”.

In the present embodiment, as an example, the value of Vred1 is set to 2.5 [V]. Since the logical value "L" of the output terminal OG at the time t6 is held by the polarization of the ferroelectric capacitor 1, it is possible to return to the original state even when the power is cut off.
(About the third and fourth steps)
In the third step t7, the n-type MOS transistor 3 is turned off by applying a fourth voltage -Vpp having a polarity opposite to the first voltage Vpp to the first input terminal CG, and the p-type MOS transistor is turned off. A fifth voltage Vdd is applied to the second input terminal RG so that the transistor 4 is turned off.

  In the fourth step t8, a ground voltage is applied to the first input terminal CG to keep the n-type MOS transistor 3 in the off state, and the second input terminal RG has the second input terminal RG smaller than the second voltage Vdd. 6 is applied.

  At a time t7, which is a third step after the time t6, the voltage of the second input terminal RG is set to the power supply voltage Vdd again, the p-type transistor 4 is turned off, and then the fourth input terminal CG is connected to the first input terminal CG. A negative voltage -Vpp is applied as the voltage of. Here, the absolute value (Vpp) of the fourth voltage is the same as the absolute value (Vpp) of the first voltage, but the first voltage turns on the n-type MOS transistor 3 at time t5. In addition, any value may be used as long as the ferroelectric capacitor 1 can maintain the state in which the n-type MOS transistor 3 is turned on at the time t6 when the ground voltage is applied to the first input terminal CG. Similarly, the fourth voltage turns off the n-type MOS transistor 3 at time t7, and then turns off the same at time t8 when the ground voltage is applied to the first input terminal CG. Any value that can be maintained may be used. Therefore, it is not always necessary to make the absolute value of the first voltage equal to the absolute value of the fourth voltage. However, when a voltage of the same polarity is applied to the ferroelectric capacitor 1, the polarization gradually does not surely occur, and as a result, its life is shortened. Therefore, from the viewpoint of ensuring that polarization always occurs and extending the life, it is preferable that the absolute value (Vpp) of the fourth voltage and the absolute value (Vpp) of the first voltage be the same.

  At a time t8, which is a fourth step after the time t7, the voltage of the first input terminal CG is returned to the ground, that is, 0 [V]. At this time, since the ferroelectric capacitor 1 exists, the voltage of the floating gate FG becomes -Vh. Therefore, n-type MOS transistor 3 maintains the off state. Therefore, the logical value of the output terminal OG becomes “H”.

  More specifically, at time t8, similarly to time t6, the p-type MOS transistor 4 is not completely turned on, and the channel resistance value is the n-type MOS transistor when the n-type MOS transistor 3 is turned on. A value (preferably near an intermediate value (more preferably, an intermediate value)) between the channel resistance value of the transistor 3 and the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off. Vred2 is input to the gate of the p-type MOS transistor 4. At time t8, since the n-type MOS transistor 3 is in the off state, the resistance becomes higher than that of the p-type MOS transistor 4. Therefore, the power supply voltage from Vdd tends to flow from the p-type MOS transistor 4 (strictly, the channel of the p-type MOS transistor 4) to the output terminal OG. Therefore, "H" is output to the output terminal OG.

  When the n-type MOS transistor 3 is off, it is not necessary to set the resistance value of the n-type MOS transistor 3 as described above. This is because the p-type MOS transistor 4 is not completely turned on, and a certain amount of current flows from the power supply terminal to the output terminal OG without flowing through the n-type MOS transistor 3, so that the logical value “H” is output from the output terminal OG. Is output to As long as this is the case, if the resistance value (strictly, the channel resistance value) of the p-type MOS transistor 4 turned off at the time t8 is larger than the resistance value of the p-type MOS transistor 4 turned on. Because it is good.

  However, from the viewpoint of reliably outputting the logical value "H" to the output terminal OG at the time t8 and facilitating the circuit configuration, the p-type MOS transistor is also used at the time t8 as in the case of the time t6. The channel resistance value of the transistor 4 is the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned on, and the channel resistance value of the n-type MOS transistor 3 when the n-type MOS transistor 3 is turned off. It is preferable that Vred2 be input to the gate of the p-type MOS transistor 4 so as to be a value (preferably near the intermediate value (more preferably, the intermediate value)). In this case, the third voltage Vred1 and the sixth voltage Vred2 have the same voltage as shown as Vred in FIG.

  Similarly, the logic value "H" of the output terminal OG at the time t8 can be returned to the original state even if the power is cut off. Note that the term “on state” used in this specification indicates a state in which the n-type MOS transistor 3 (channel) has a low resistance because the voltage of Vh is held in the floating gate FG. Similarly, the “off state” indicates a state in which the (-channel) of the n-type MOS transistor 3 has a high resistance because the voltage of −Vh is held in the floating gate FG.

  As described above, the nonvolatile latch circuit according to the embodiment of the present invention uses the p-type MOS transistor 4 so that the p-type MOS transistor 4 is not completely turned on at time t6 (preferably at time t6 and time t8). , The logical value “L” can be reliably output to the output terminal OG when the n-type MOS transistor 3 is turned on. Since the logical values “H” and “L” output to these output terminals OG include the fact that the logical value “H” is output to the output terminal, the polarization of the ferroelectric capacitor 1 is used. Even if the power is turned off, the information is retained. Further, in the conventional example, the magnitudes of the positive and negative voltages applied to the ferroelectric capacitor are different, but in the circuit operation of the present embodiment, the positive and negative voltages are applied to the first input terminal CG. Therefore, the magnitudes of the positive and negative voltages applied to the ferroelectric capacitor 1 are equal.

  Further, when a positive or negative voltage is applied to the first input terminal CG, the p-type MOS transistor 4 is turned off, so that current consumption can be reduced. Further, in reading information when a positive or negative voltage is applied to the first input terminal CG and then returned to the ground, no voltage is applied to the first input terminal CG. Can be done.

  In the present embodiment, a MOS transistor is used as the MOS transistor. However, it goes without saying that the circuit operation of the present embodiment can be obtained as long as the transistor is controlled by a voltage. For example, it can operate with a junction type MOS transistor (JFET) or the like. In this embodiment, a resistance element is used, but a resistance change element using a phase change material or the like may be used.

(Application example of the present invention)
FIG. 6 is a circuit diagram showing a semiconductor circuit of an application example of the present invention. 5 is a pass transistor, 6 is a first logic circuit, and 7 is a second logic circuit.

  As shown in FIG. 6, the output of the first logic circuit 6 is connected to the input terminal IN of the pass transistor 5, and the input of the second logic circuit 7 is connected to the output terminal OUT of the pass transistor 5. Further, the output terminal OG of the nonvolatile latch circuit of FIG. 1 of the present invention is connected to the gate of the pass transistor 5, and the signal of the logic circuit is controlled by the nonvolatile latch circuit.

  When the output of the nonvolatile latch circuit is "L", the logic circuits are disconnected, and no logic signal is transmitted. When the output of the nonvolatile latch circuit is “H”, the logic circuits are connected to each other, and the logic signal is transmitted. The information written in the nonvolatile latch circuit has non-volatility and is retained even when the power is shut off.

  As shown in FIG. 7, the nonvolatile latch circuit shown in FIG. 4 can be used instead of the nonvolatile latch circuit shown in FIG. As a result, current consumption during writing can be further reduced.

  As described above, in the present embodiment, the logic signal is controlled by the pass transistor, and the control information is held in the nonvolatile latch circuit, so that the control signal can be restored even when the power is cut off. Further, since the logic signal and the signal for controlling the nonvolatile latch circuit are separated from each other, there is no delay in the logic signal as in the conventional example, and it is possible to increase the speed.

  In this embodiment, a pass transistor is used as an element for controlling a logic signal. However, the present invention is not limited to this. The element connected to the output of the nonvolatile latch circuit may be any element as long as it is a semiconductor element for controlling a logic signal. For example, a buffer which is an inverter may be connected to the output of the nonvolatile latch circuit.

  As described above, according to the present invention, there is provided a method of driving a nonvolatile latch circuit including a ferroelectric gate device capable of reliably outputting not only the logical value “H” but also the logical value “L”. You.

FIG. 2 is a diagram showing a nonvolatile latch circuit first devised by the present inventors; FIG. 3A is a diagram illustrating an operation principle of the present invention, FIG. 3B is a diagram illustrating an equivalent circuit of a ferroelectric capacitor and an N-type MOS transistor, and FIG. 3B is a diagram illustrating the charge-voltage characteristics of the ferroelectric capacitor Ferro and the gate capacitor Ox. Figure Timing chart of the voltage of each terminal of the nonvolatile latch circuit shown in FIG. FIG. 2 is a diagram illustrating a circuit according to an embodiment of the present invention. Timing chart of voltage of each terminal of the circuit according to the embodiment of the present invention Diagram showing a circuit of an application example of the present invention Diagram showing a circuit of an application example of the present invention Diagram showing prior art circuit Timing chart of voltage of each terminal of conventional circuit

Explanation of reference numerals

1: Ferroelectric capacitor 3: n-type MOS transistor 4: p-type MOS transistor CG: first input terminal RG: second input terminal OG: output terminal t5: first step (time t5)
t6: Second step (time t6)
t7: Second step (time t7)
t8: Second step (time t8)
Vpp: first voltage Vdd: second voltage, fifth voltage, positive voltage (power supply voltage)
Vred1: third voltage -Vpp: fourth voltage Vred2: sixth voltage

Claims (5)

A method for driving a nonvolatile latch, comprising:
The nonvolatile latch includes:
A ferroelectric capacitor,
an n-type MOS transistor;
and a p-type MOS transistor,
One end of the ferroelectric capacitor is connected to a first input terminal,
The other end of the ferroelectric capacitor is connected to a gate of the n-type MOS transistor,
The source of the n-type MOS transistor is grounded,
An output terminal is connected to a drain of the n-type MOS transistor and a drain of the p-type MOS transistor,
A second input terminal is connected to a gate of the p-type MOS transistor;
A positive voltage is input to the source of the p-type MOS transistor,
The method of driving the nonvolatile latch includes a first step, a second step, a third step, and a fourth step in order,
In the first step, a second voltage is applied to the first input terminal so that the n-type MOS transistor is turned on and the p-type MOS transistor is turned off. A second voltage is applied to
In the second step, a ground voltage is applied to the first input terminal to maintain the ON state of the n-type MOS transistor, and a third voltage smaller than the second voltage is applied to the second input terminal. Apply the voltage of
In the third step, a fourth voltage having a polarity opposite to that of the first voltage is applied to the first input terminal to turn off the n-type MOS transistor and turn off the p-type MOS transistor. Applying a fifth voltage to the second input terminal so that
In the fourth step, a ground voltage is applied to the first input terminal to maintain the off-state of the n-type MOS transistor, and a sixth input terminal, which is lower than the second voltage, is applied to the second input terminal. Is applied. Any of the resistance values of the p-type field-effect transistor when the third voltage is applied is higher than the resistance value of the n-type field-effect transistor when the n-type field-effect transistor is off. Is small,
The resistance of the p-type field effect transistor when the third voltage is applied is larger than the resistance of the n-type field effect transistor when the n-type field effect transistor is on. The method according to claim 1, wherein the third voltage is set so that the third voltage is set.   When the third voltage is applied, the resistance of the p-type field effect transistor is equal to the resistance of the n-type field effect transistor when the n-type field effect transistor is off. 3. The method of driving a nonvolatile latch according to claim 2, wherein when the type field effect transistor is turned on, the value is set to an intermediate value between the resistance value of the n type field effect transistor.   4. The method according to claim 1, wherein the third voltage and the sixth voltage have the same potential. 5.   5. The method according to claim 1, wherein an absolute value of the first voltage is the same as an absolute value of the fourth voltage.

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