JPH04256361A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a non-volatile semiconductor memory device which has adequately fast write and read speed, is free from restriction of read frequency, enables adequate polarization, is resistant to noises and has less leak current. CONSTITUTION:A structure which is provided with a P-well region 2, a ferroelectrics film 7 formed on a main surface of the P-well region 2, an electrode 5 formed on the ferroelectric film 7 and P<+>-regions 12, 13 formed at one end side and the other end side of the ferroelectric film 7.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

0002

2. Description of the Related Art Conventional semiconductor memory devices include those described, for example, in "Integrated Circuit Engineering (2), Circuit Technology Edition, co-authored by Hisayoshi Yanai and Minoru Nagata, published by Corona Publishing, pp. 128-131." FIG. 10 is a circuit diagram of the MOS-RAM type storage device described in the above-mentioned document, and (a
) shows a 6MOS static type, (b) shows a 4MOS dynamic type, (c) shows a 3MOS dynamic type, and (d) shows a 1MOS dynamic type. However, in the above-mentioned MOS-RAM type semiconductor memory device, the MOS
Since information is stored depending on the ON or OFF state of the FET, there is a problem that the stored information disappears when the power to the storage device is turned off, that is, the storage is volatile.

Next, as a second conventional example, EPROM
(erasable-programmable RO
M), E2PROM (electrically-er
There are non-volatile transistors such as (as described in "Fundamentals of Semiconductor Devices" published by Ohm Publishing Co., Ltd., pp. 188-189). This type retains memory even if the power is turned off. However, in the second conventional example, the writing speed is very slow. For example, the write cycle time of DRAM is 150
ns, whereas in E2PROM it is 107ns.
(For example, described in "Nikkei Microdevice" published by Nikkei McGraw-Hill, May 1989 issue, p. 58)
. Therefore, there is a problem that it cannot be used as a RAM.

Next, as a third conventional example, there is a memory using a ferroelectric film as a capacitor (for example, described in "Nikkei Micro Device" published by Nikkei McGraw-Hill, April 1989 issue, pp. 66-67). be. This device retains its memory even when the power is turned off, and can write and read information at high speed. However, in the third conventional example, since polarization inversion is performed during readout, the ferroelectric film becomes fatigued, so there is a problem in that the number of readouts is limited.

Next, as a fourth conventional example, Japanese Patent Laid-Open No. 57
There is one described in JP-172771. In this conventional example, the gate capacitor of the MOSFET is constructed by connecting a capacitor using a ferroelectric film and a capacitor using an oxide film in series, so that the gate capacitor of the MOSFET is connected in series with the oxide film capacitor and the Si capacitor, regardless of whether the power is on or off. A nonvolatile memory is constructed by storing electric charge at the substrate interface. FIG. 11 is an equivalent circuit diagram of the gate capacitor portion in the above device. In FIG. 11, 200 is a ferroelectric film capacitor, 201 is an oxide film capacitor, C1 is the capacitance of the ferroelectric film capacitor 200, Q1 is the charge of the ferroelectric film capacitor 200, and C2 is the oxide film capacitor 201.
, Q2 is the charge of the oxide film capacitor 201, V0 is the gate voltage, V1 is the voltage of the ferroelectric film capacitor 200, and V2 is the voltage of the oxide film capacitor 201. However, the fourth conventional example has the following problems. That is, V1+V2=V0, V1=Q1/C1, V
2=Q2/C2 Q1=Q2 (charge conservation law)
}
...(Math. 1) Since C1≫C2 (generally the left equation holds) holds, V1≒(C2/C1)V0, V2≒V
0 (Equation 2), and almost no voltage is applied to the ferroelectric film capacitor 200. Therefore, there is a drawback that the ferroelectric film cannot be sufficiently polarized. Furthermore, if V0 is increased in order to increase V1, there is also the drawback that the oxide film of the oxide film capacitor 201 will undergo dielectric breakdown. Furthermore, since the ferroelectric film cannot be polarized sufficiently, Q2 is also small, and therefore the difference between the storage contents "1" and "0" of the storage device cannot be made sufficiently large. Therefore, there is a problem in that information is easily reversed by noise applied to the signal line.

[0006] Next, as a fifth conventional example, there is
There is one described in the -46680 publication. FIG. 12 is an equivalent circuit diagram of the fifth conventional example. In Figure 12, 3
00 is a ferroelectric film capacitor, 301 is an oxide film capacitor, 302 is a semiconductor, and 303 is a write line. In this device, a write voltage is applied to a ferroelectric film capacitor 300 and an oxide film capacitor 301, and a charge -Q1
, Q2 to change the conductivity of the semiconductor 302 to store information. The problems of the fifth conventional example are the same as those of the fourth conventional example.

Next, as a sixth conventional example, there is
There is one described in JP-229350. However, in this conventional example, polarization inversion is performed when reading information, which causes fatigue of the ferroelectric material, which poses a problem in that the number of readings is limited.

Next, as a seventh conventional example, "Hama
Kawa Y. , Matsui Y. , Higum
aY. and Nakagawa T. , “A N
onvolatile Memory FET Usi
ng PLT Film Gate,”Interna
tionalElectron Devices Me
eting, Tcchnical Digest, Paper No. 14.6, pp. 294-297, Dec. 1
977” or “Matsui Y., Nakano
H. , Okuyama M. , Nakagawa
T. and HamakawaY. , “PbTiO3
Thin Film Gate Nonvolati
le Memory FET,” 1979 Proc.
eedings of the 2nd Meeting
on Ferroelectric Materia
ls and Their Applications
, Paper No. F-8, pp. 239-244, 19
There are some listed in 79. The above conventional example is
A typical MOSFET has a structure in which a ferroelectric film is used instead of a gate oxide film. However, in the seventh conventional example, leakage flows from the drain to the source through the interface state even when the storage device is in the off state due to the interface state generated at the interface between the ferroelectric film and the Si substrate. The problem is that the current is large. Furthermore, the electric field due to the polarization of the ferroelectric material terminates at the above interface level, and S
There is also the problem that an inversion layer is not sufficiently formed on the surface of the i-substrate.

[0009]

[Problems to be Solved by the Invention] As mentioned above, the memory in the first conventional example is volatile, the writing speed in the second conventional example is slow, and the number of reads is limited in the third example. In the fourth and fifth embodiments, the polarization of the ferroelectric film is small, so the information is easily inverted by noise applied to the signal line, and in the sixth embodiment, the number of readouts is limited. , the seventh embodiment had various problems such as large leakage current.

The present invention has been made in order to solve the various problems of the prior art as described above.
It is an object of the present invention to provide a non-volatile semiconductor memory device which has a sufficiently high read speed, has no limit on the number of reads, has sufficient polarization, is resistant to noise, and has low leakage current.

[0011]

[Means for Solving the Problems] In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the invention according to claim 1, a ferroelectric film is formed on the main surface of the semiconductor region of the first conductivity type, an electrode is formed thereon, and a ferroelectric film is formed on the main surface of the semiconductor region of the first conductivity type. , has a structure in which high concentration impurity regions of the first conductivity type are formed at one end and the other end of the ferroelectric film, respectively. Furthermore, in the invention according to claim 2,
The structure according to claim 1 is formed of P type and N type, and has a structure in which they are complementary connected.

0012

[Operation] The present invention is configured to retain memory by changing the resistance value of a semiconductor region using polarization of a ferroelectric film. That is, either a depletion layer or an accumulation layer is formed in the semiconductor region in accordance with the polarity of the polarization charge of the ferroelectric film, thereby increasing or decreasing the electrical resistance of the semiconductor region. The case where the depletion layer grows corresponds to the OFF state, and the case where the accumulation layer grows corresponds to the ON state.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a first embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the first embodiment. In addition,
Transistors 110, 111, and 112 connected to the word line WL and the pair of bit lines BL and BL are parts formed outside the memory device of this embodiment. The memory device of this embodiment is a junction field effect transistor (hereinafter referred to as JFE).
This is a modification of the JFET (abbreviated as T), and has a structure in which the gate of the JFET is replaced with a ferroelectric film. In this embodiment, a depletion layer is formed inside the semiconductor region by polarization of the ferroelectric film, and the width of a channel through which current flows inside the semiconductor is changed. In other words, the current control effect of the ferroelectric film is
Like a normal JFET, this is based on the change in effective cross section due to channel depletion. In this memory device, either a depletion layer or an accumulation layer is formed in the semiconductor region in accordance with the polarity of the polarized charges, thereby increasing or decreasing the electrical resistance of the semiconductor region. The case where the depletion layer grows corresponds to the OFF state, and the case where the accumulation layer grows corresponds to the ON state. In addition, in order to increase the difference in electrical resistance between the ON state and the OFF state, O
In the FF state, the semiconductor region is sufficiently thinned so that the channel can be pinched off at the depletion layer, or at both the depletion layer and the depletion layer at the junction of the semiconductor region and the semiconductor substrate. Form into a thin layer.

Using a storage device having the above configuration, FIG.
As shown in the equivalent circuit of
8, 10, 11) 101 and a P-type resistor with a ferroelectric gate (memory device formed in a P-type semiconductor, 2 in Figure 1)
, 5, 7, 12, 13) 102 are connected in a complementary manner, the N-type resistor 101 or the P-type resistor 1
Since one of the circuits 02 is always in the OFF state, it is possible to eliminate the current component that constantly flows through the entire circuit.

[0015] This will be explained in detail below. In Figure 1, N
P well regions 2 and 3 are formed on the main surface of a mold substrate 1. Furthermore, an electrode 5 is formed on the main surface of the P-well region 2 with a ferroelectric film 7 interposed therebetween. Furthermore, P+ regions 12 and 13 are formed on the main surface of the P well region 2 at positions offset from the ferroelectric film 7 at one end and the other end of the ferroelectric film 7, respectively. Further, an N-well region 4 is provided on the main surface of the P-well region 3, and an electrode 6 is formed on the main surface of the N-well region 4 via a ferroelectric film 8. Further, N+ regions 10 and 11 are formed on the main surface of the N-well region 4 at positions offset from the ferroelectric film 8 at one end and the other end of the ferroelectric film 8, respectively. Further, an N+ region 9 is formed on the main surface of the N-type substrate 1,
A P+ region 14 is formed on the main surface of the P well region 3. Then, electrode 5 and electrode 6 are connected to input terminal 103 via transistor 110, P+ region 13 and N+ region 10 are connected to output terminal 104, N+ region 11 is connected to VDD via transistor 111, and P+ region 12 is connected to VSS via transistor 112. Further, N+ region 9 is connected to VDD, and P+ region 14 is connected to VSS. The transistor 110 opens and closes in response to signals from the word line WL, the transistor 111 from one bit line BL, and the transistor 112 from the other bit line BL. Note that the pair of bit lines BL and BL have mutually opposite polarity characteristics (if one is high, the other is low), and the transistors 111 and 112 are transistors with mutually opposite polarities. Therefore transistors 111 and 112
When one is ON, the other is also ON, and when one is OFF, the other is also OFF.

Next, the operation will be explained. First, the relationship between the polarization charge of the ferroelectric film and the applied electric field will be explained. FIG. 3 is a characteristic diagram showing the relationship between the polarization charge of the ferroelectric film and the applied electric field. As shown in FIG. 3, after the ferroelectric film is polarized by applying an electric field, it retains the residual polarization Pr even when the electric field is reduced to zero. In order to make the polarization zero, it is necessary to apply an electric field Ec (coercive electric field) in the opposite direction to the above electric field.

Next, the operation of this storage device will be explained. FIG. 4 is a time chart for writing, and FIG. 5 is a time chart for reading. First, Figure 4, Figure 1, Figure 2
Data writing will be explained based on the following. As shown in section (i) of FIG.
L￣ is high and ON) and the transistor 11
After turning on all 0, 111, and 112, input terminal IN
(corresponding to 103), when a positive voltage is applied to the ferroelectric film 7
, 8 are polarized and induce negative charges on the main surfaces of the P well region 2 and the N well region 4. In other words, a depletion layer is formed on the main surface of the P-well region 2. When the depletion layer comes into contact with the depletion layer generated at the junction between the P-well region 2 and the N-type substrate 1,
The P-type resistor 102 has a significantly high resistance. On the other hand, electrons are induced in the main surface of the N-well region 4, and the resistance of the N-type resistor 101 decreases. As a result, High is output to the output terminal OUT (corresponding to 104). Also, (ii) in Figure 4
As shown in the section, even if the input terminal IN is set to 0 in the above state, residual polarization remains in the ferroelectric film, so the output terminal O
The high level of UT is maintained. In other words, "1" is stored. Furthermore, (iii) and (iv) in FIG.
As shown in the section, even if the power is once turned off and then turned on again, the residual polarization does not change, so a High level appears at the output terminal OUT. In other words, memory is non-volatile. Next, consider the case where a negative voltage is subsequently applied to the input terminal IN, as shown in section (v) in FIG. The ferroelectric materials 7 and 8 are polarized so that positive charges are induced on the main surfaces of the P-well region 2 and the N-well region 4. Therefore, a depletion layer is generated on the main surface of the N-well region 4, and the resistance of the N-type resistor 101 becomes extremely high. On the other hand, holes are induced in the main surface of the P-well region 2, and the resistance of the P-type resistor 102 becomes low. As a result, a low level appears at the output terminal OUT. In other words, "0" is stored (the memory of "1" is erased).

Next, data reading will be explained based on FIG. 5. During reading, word line WL is OF
Leave the F signal state as is, and set the pair of bit lines BL and BL￣ to the ON signal state. As shown in FIG. 5, after "1" is written, the VDD voltage, that is, High is output to the output terminal OUT. Further, after "0" is written, the VSS voltage, that is, low, is output to the output terminal OUT. As described above, during readout, the polarization of the ferroelectric film is not inverted. Therefore, there is no risk of fatigue of the ferroelectric film even if reading is performed frequently. Also, No. 160 of “Dielectric Phenomenology” published by the Institute of Electrical Engineers of Japan.
As described on pages 1 to 161, polarization reversal of the ferroelectric film is extremely fast, about 10 ns, so in this embodiment, both writing and reading can be performed at high speed.

Next, the band structure in this embodiment will be explained. FIG. 9 shows an electrode 5 provided on the main surface of the P-type region 2.
, which shows the band structure of the ferroelectric film 7 and the main surface of the semiconductor. In FIG. 9, (o), (i), (ii), (
The band structure of v) corresponds to (o), (i), (ii), and (v) of the writing time chart shown in FIG. 4, respectively. In addition, in FIG. 9, EfM is the Fermi level of the electrode, Ef is the Fermi level of the P-type semiconductor, and Ec
is the potential at the bottom of the conduction band of the semiconductor, and Ev is the potential at the top of the valence band of the semiconductor. FIG. 9(o) shows an initial state where no voltage is applied. In this state, no charges are induced on the surface of the P-type region 2. Figure 9
(i) shows the band structure when a positive voltage is applied to the input. In this state, a depletion layer is formed on the main surface of the P-type region 2. FIGS. 9(ii) and (iv) show the band structures when the input voltage is removed. In this state, the depletion layer charge on the main surface of the P-type region 2 is retained due to the residual polarization of the ferroelectric material. Therefore, the band on the main surface of the P-type region 2 is kept bent. FIG. 9(v) shows the band structure when a negative voltage is applied to the input. In this state, the band on the main surface of the P-type region 2 bends toward the higher electron potential, and holes are induced. In the memory device of this embodiment, as shown in FIG. 5, no input voltage is applied when reading the memory. Therefore, the band structure described above does not change when reading the memory. Note that N-type region 4
The band structure of the storage device provided on the main surface of the device can also be explained in the same manner as above.

Next, a method for manufacturing the device shown in FIG. 1 will be explained. FIG. 8 is a cross-sectional view showing the manufacturing process of the device shown in FIG. First, as shown in FIG. 8(a), P well regions 2 and 3 are formed on the main surface of an N type substrate 1. Next, an N-well region 4 is provided on the main surface of the P-well region 3. Next, the above N
A LOCOS oxide film 50 is formed on the main surface of the mold substrate 1, the main surfaces of the P-well regions 2 and 3, and the main surface of the N-well region 4 where no element will be formed. Next, FIG. 8(b)
), on the main surfaces of the P-well region 2 and the N-well region 4, the portion where the ferroelectric film is to be formed is
In order to eliminate dangling bonds at the interface between the semiconductor region and the ferroelectric film,
Inject fluorine F. Next, as shown in FIG. 8(c),
Ferroelectric films 7 and 8 are formed on the main surfaces of the P-well region 2 and the N-well region 4, and the ferroelectric film 7
An electrode 5 is formed on the ferroelectric film 8, and an electrode 6 is formed on the ferroelectric film 8. Next, as shown in FIG. 8(d), the N-type substrate 1
N+ region 9 on the main surface of P well region 2, P+ regions 12 and 13 on the main surface of N well region 4, and N+ region 10 on the main surface of N well region 4.
, 11 and a P+ region 14 are formed on the main surface of the P well region 3, respectively. Thereafter, the device shown in FIG. 1 is completed by performing necessary wiring.

Next, FIG. 6 is a sectional view of a second embodiment of the present invention. In FIG. 6, a P well region 21 and an N well region 22 are formed on the main surface of a semiconductor substrate 20 with an insulating layer 23 in between. Furthermore, an electrode 5 is provided on the main surface of the P-well region 21 with a ferroelectric film 7 interposed therebetween. Further, on the main surface of the P well region 21, P+
Regions 12 and 13 are formed. Furthermore, an electrode 6 is provided on the main surface of the N-well region 22 with a ferroelectric film 8 interposed therebetween. Also,
N+ regions 10 and 11 are formed on the main surface of the N-well region 22 at positions offset from the ferroelectric film 8 at one end and the other end of the ferroelectric film 8, respectively. Then, electrode 5 and electrode 6 are connected to input terminal 103 via transistor 110, and P+ region 13 and N+ region 10 are connected to output terminal 104.
, N+ region 11 is connected to VDD through transistor 111, and P+ region 12 is connected to VSS through transistor 112. The equivalent circuit of the embodiment shown in FIG. 6 is the same as the circuit shown in FIG. 2, the writing time chart is the same as FIG. 4, and the reading time chart is the same as FIG. 5.

Next, the operation will be explained. First, writing will be explained based on FIGS. 4 and 6. In Figure 4 (
In the i) section, a depletion layer is generated from the main surface of the P well region 21 directly under the ferroelectric film 7 to the interface between the well region and the insulating layer 23, and the P-type resistor 102 has a significantly high resistance. As a result, High is output to the output terminal 104. Furthermore, sections (ii), (iii), and (iv) in FIG. 4 are the same as in the embodiment of FIG.
is stored in a non-volatile state. Next, in the section (v) of FIG. 4, holes are induced in the main surface of the P-well region 21, and the resistance of the P-type resistor 102 becomes low. In addition, N directly below the ferroelectric film 8
From the main surface of the well region 22 to the well region and the insulating layer 23
A depletion layer is generated up to the interface, and the P-type resistor 101 becomes extremely high in resistance. As a result, the output terminal 104 has a low
appears. In other words, "0" is stored (the memory of "1" is erased). Note that the reading operation is the same as that of the embodiment shown in FIG.

Next, FIG. 7 is a sectional view of a third embodiment of the present invention. In this embodiment, in the memory device shown in the embodiment of FIG. It is characterized by the fact that it overlaps with The operation is the same as in the embodiment of FIG. 1, but in this embodiment, the P+ region and the N
Since a portion of the + region overlaps with the ferroelectric film, there is an advantage that the chip area can be reduced.

[0024]

As described above, according to the present invention, the resistance of the semiconductor region is changed using the polarization of the ferroelectric film, and information is stored using the resistance. The following effects can be obtained. (i) It is nonvolatile because residual polarization is used for memory retention. (ii) Since the polarization reversal of the ferroelectric film is sufficiently fast, both writing and reading can be performed at high speed. (iii) Since the polarization is not inverted when reading information, there is no limit to the number of times the information can be read. (iv) Since all the gate voltage for writing information is applied to the ferroelectric film, the polarization of the ferroelectric film can be sufficiently inverted with a low gate voltage. Therefore, it is resistant to noise. (v) Even if some interface states occur at the interface between the ferroelectric film and the Si substrate, the present memory device will operate as long as a depletion layer can be formed within the Si substrate. (vi) The present memory device operates even if the gate and the high concentration impurity layer serving as the electrode are offset. Therefore, when the present memory device is in the off state, no leakage current due to the interface state flows.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a first embodiment of the invention.

FIG. 2 is an equivalent circuit diagram of the first embodiment.

FIG. 3 is a characteristic diagram showing the relationship between polarization charge of a ferroelectric material and applied electric field.

FIG. 4 is a time chart during writing in the first embodiment.

FIG. 5 is a time chart at the time of reading in the first embodiment.

FIG. 6 is a sectional view of a second embodiment of the invention.

FIG. 7 is a sectional view of a third embodiment of the invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 9 is a diagram showing an electrode formed on the main surface of the P-type region, a ferroelectric film, and a band structure of the P-type region in the first embodiment.

FIG. 10 is a circuit diagram of a first conventional example.

FIG. 11 is an equivalent circuit diagram of a gate capacitor portion in a fourth conventional example.

FIG. 12 is an equivalent circuit diagram of a fifth conventional example.

[Explanation of symbols]

1... N-type semiconductor substrate 2, 3... P well region 4... N well region 5, 6... Electrode 7, 8... Ferroelectric film 9, 10, 11... N+ region 12, 13, 14... P+ region 20... Semiconductor Substrate 21...P well region 22...N well region 23...Insulating layer 101...N-type resistor 102 having a ferroelectric material at its gate...P-type resistor 103 having a ferroelectric material at its gate...Input terminal 104...Output terminals 110, 111 , 112...Transistor 200...Ferroelectric film capacitor 201...Oxide film capacitor 300...Ferroelectric capacitor 301...Oxide film capacitor 302...Semiconductor 303...Write line WL...Word line BL, BL￣...Bit line

Claims (2)

[Claims] 1. A semiconductor region of a first conductivity type; a ferroelectric film formed on a main surface of the semiconductor region of the first conductivity type; an electrode formed on the ferroelectric film; A semiconductor memory device comprising, on a main surface of a semiconductor region, highly concentrated impurity regions of a first conductivity type formed at one end and the other end of the ferroelectric film. 2. A semiconductor region of a first conductivity type; a ferroelectric film formed on a main surface of the semiconductor region of the first conductivity type; an electrode formed on the ferroelectric film; a first conductivity type high concentration impurity region formed on one end side and the other end side of the ferroelectric film on the main surface of the semiconductor region;
a semiconductor memory device, a second conductivity type semiconductor region, a ferroelectric film formed on a main surface of the second conductivity type semiconductor region, and an electrode formed on the ferroelectric film; a second semiconductor memory device comprising a second conductivity type high concentration impurity region formed on one end side and the other end side of the ferroelectric film, respectively, on the main surface of the semiconductor region; A semiconductor memory device characterized by being connected.