JPH0383289A - Mos type semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce power consumption in a memory cell and to improve the speed of a read/write action by setting the threshold of a MOS transistor constituting the memory cell larger than that of a MOS transistor constituting a peripheral equipment. CONSTITUTION:The bias voltage of a second P well 3 in the second N-channel MOS transistor TR 5 constituting the peripheral equipment is 0V. Thus, a drain current increases and the action speed of TR 5 can be improved. In such a case, a sub-threshold current about 10<-10>A flows, for example, even if a gate voltage is 0V. On the other hand, the substrate bias of -3V is impressed on the first P well 2 of a first N-channel MOSTR 4 constituting the memory cell from a substrate bias generation circuit 6 in such a case, and the sub-threshold current of respective TR is set to be less than 10<-12>A. Thus, the power consumption of the memory cell can considerably be reduced and the speed of reading and writing can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor memory device, and particularly to a MOS type semiconductor memory device that reads and writes data at high speed.

[Prior Art] In a MOS type semiconductor memory device, when the set value of the threshold voltage is changed, the circuit operating state changes as follows. That is, when the threshold value of the MOS transistor is large, the drive current of the MOS transistor decreases, and the operating speed of the circuit decreases, resulting in a decrease in the speed of reading and writing data. This is due to the characteristic of the MOS transistor that the drain current in the saturation region is approximately proportional to the square of the difference between the gate voltage and the threshold voltage. On the other hand, if the threshold value of the MOS transistor is small,
Although the operating speed of the circuit is improved, the subthreshold current that flows when the gate-source voltage is OV increases. For this reason, in the case of static RAM (SRAM), the data retention current of the memory cells increases, and the power consumption of the entire semiconductor storage device consisting of tens of thousands of memory cells becomes extremely high.Furthermore, dynamic RA
In the case of M (DRAM), the accumulated charges are discharged in a subthreshold 7JX flow, making it impossible to hold data. In either case, a fatal malfunction will occur as a storage device.

For this reason, in conventional MOS semiconductor memory devices, the threshold values of the MOS transistors constituting the device are set to values that ensure normal operation as a memory device.

Problems to be Solved by the Invention] However, in the conventional MOS type semiconductor memory device described above, in order to ensure normal memory operation, MO8! - Since the threshold value of the transistor is set to a certain degree, there is a problem that the driving current in the peripheral circuit becomes small and the operating speed of the circuit decreases.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a MOS type semiconductor memory device which can satisfy both normal circuit operation and high speed.

[Means for Solving the Problems] A MOS semiconductor memory device according to the present invention includes a memory cell composed of a MOS transistor and its peripheral circuit, in which a MOS transistor constituting the memory cell The threshold value of is set larger than the threshold value of the MOS transistor forming the peripheral circuit.

The MOS transistor constituting the memory cell has, for example, a source-substrate reverse bias voltage applied thereto that is higher than that of the MOS transistor constituting the peripheral circuit.

Further, when a MOS transistor is formed in a P-type or N-type semiconductor well, the MOS transistor forming the memory cell has a source-well reverse bias larger than that of the MOS transistor forming the peripheral circuit. It may also be one to which a voltage is applied.

[Function] According to the present invention, since the threshold value of the MOS transistor constituting the memory cell is set larger than the threshold value of the MOS transistor constituting the peripheral circuit, the drive current in the memory cell can be reduced. Furthermore, the drive current in the peripheral circuits can be increased. Therefore, it is possible to ensure normal data retention operation within the memory cell, and the operation speed of peripheral circuits such as single output buffers, decoders, and word drivers is improved, and as a result, the speed of read and write operations is increased. can be improved.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic diagram showing the main parts of a MOS type semiconductor memory device according to a first embodiment of the present invention.

A first P layer is applied to the N-type semiconductor substrate 1 by a selective diffusion process.
The well 2 and the second P well 3 are formed independently. The first P well 2 has a drain 4a1 and a source 4a.
A first N-channel MOS transistor 4 is formed which includes a gate 4C and a gate 4C. In addition, the second P well 3
The drain 5a, the source 5b and the gate) 5c
A second N-channel MOS transistor 5 is formed.

On the other hand, the memory cells constituting this semiconductor memory device are constructed as shown in FIG. 2, for example.

That is, between the power supply V[)D and the ground GND, there is a CMOS inverter circuit consisting of a P channel MOS transistor 7a and an N channel MOS transistor 8a, and a CMOS inverter circuit consisting of a P channel MOS transistor 7b and an N channel MOS transistor 8b. These input terminals and output terminals are connected to each other, and transfer gates 9a and 9b are respectively connected to each output terminal.

First N-channel MOS transistor 4 in FIG.
corresponds to the transistors 8a, 8b and transfer gates 9a, 9b of the memory cell described above, and the voltage from the substrate bias generation circuit 6 is applied to the first P well 2 with respect to the potential (OV) of the source 4b. A source-to-well reverse bias voltage of -3V is applied.

Further, the second N-channel MO8 transistor 5 constitutes peripheral circuits such as a human output buffer, a decoder, and a word driver, and when the potential of its source 5b is set to OV, the second P well 3 is set to OV. It is set.

Next, the operation of the MO8 type semiconductor memory device configured as described above will be explained.

FIG. 3 is a graph showing drain current versus drain voltage when OV and -3V are applied as substrate biases of an N-channel MO8 transistor, and FIG. 4 is a graph showing drain current versus gate voltage. When the substrate bias is OV, the threshold voltage of the transistor is low, for example, 0.5V from OV, so the drive current of the transistor becomes large. On the other hand, when the substrate bias is 13V, the threshold voltage of the transistor varies from 0.5V to 1.5V, for example. Since the voltage increases to OV, the drive current of the transistor becomes smaller.

In this embodiment, since the bias voltage of the second P well 3 of the second N-channel MO8 transistor 5 constituting the peripheral circuit is Ov, the drain current increases.
The operating speed of the second N-channel MOS transistor 5 is increased, and the data read/write speed can be increased. In this case, as shown in FIG. 4, even if the gate voltage is Ov, the voltage is 10-'. A subthreshold current of about A flows. However, since the peripheral circuit has a much smaller number of transistors than the memory cell section, the influence of an increase in current consumption due to subthreshold current is very small.

On the other hand, since a substrate bias of -3V is applied from the substrate bias generation circuit 6 to the first P well 2 of the first N-channel MO8 transistor 4 constituting the memory cell, each transistor constituting the memory cell The subthreshold current of the memory cell can be reduced to 10-''A or less. Therefore, the power consumption of the memory cell can be sufficiently reduced. In this case, although the operating speed of the transistor is reduced, the operation of the memory cell is There is no problem with that.

Incidentally, MO8 type semiconductor integrated circuits are becoming more and more highly integrated as their element dimensions are reduced year by year.

Therefore, gate oxide films with a thickness of less than Ion11 have come to be manufactured. In this case, the withstand voltage of the gate oxide film also decreases, so it is necessary to lower the power supply voltage from the conventional 5V to about 3V to ensure reliability. However, as mentioned above, the drain current in the saturation region of a MOS transistor is equal to twice the difference between the gate voltage and the threshold voltage.
It is approximately proportional to the power of Therefore, when the threshold voltage is kept constant, when the voltage approaches the threshold voltage, the drain current decreases rapidly, and the circuit speed decreases extremely.

In this regard, according to the MOS type semiconductor integrated circuit shown in Fig. 1, transistors with small threshold voltages are used in the peripheral circuits, so the drain current decreases rapidly even at lower power supply voltages than in the past. This will not occur, and an extreme drop in circuit speed can be prevented.

FIG. 5 is a diagram showing the power supply voltage dependence of the delay time per 11 data stages. When compared at a power supply voltage of 2.5V, the present invention can increase the circuit speed by about 20% compared to the conventional technology.

FIG. 6 is a block diagram showing the structure of a MOS type semiconductor memory device according to a second embodiment of the present invention.

This embodiment differs from the first embodiment in that a P-type semiconductor substrate 10 is used to form a double diffusion well to form an N-type MOS transistor. That is, N is added to the P-type semiconductor substrate 10 by a selective diffusion process.
A well 11 is formed, and a first P well 12 and a second P well 13 are independently formed inside and outside this N well 11, respectively. A first N-channel MO8 transistor 14 is formed in the first P-well 12 and includes a drain 14a, a source 14b, and a gate 14C. Further, the second P well 13 has a drain 15a.
A second N-channel MO8 transistor 15 consisting of a source 15b and a gate 15c is formed.

The first N-channel MO8 transistor 14 constitutes a memory cell as described above, and its source 14b
A source-to-well reverse bias voltage of 13 V from the substrate bias generation circuit 16 is applied to the first P well 12 with respect to the potential (OV).

Further, the second N-channel MO8 transistor 15 constitutes peripheral circuits such as an input/output buffer, a decoder, and a word driver, and when the potential of its source 15b is set to OV, the P-type semiconductor substrate 10 is set to OV. has been done.

In this circuit, by particularly reducing the junction depth of the P-well 12, the amount of charge collected in the diffusion layer when α particles are incident can be structurally reduced.

Therefore, according to this embodiment using this double diffusion well, in addition to the above-mentioned effects due to optimization of the threshold voltage,
It also has the advantage of preventing soft errors caused by α rays.

Note that in each of the above embodiments, the threshold values of the memory cell transistor and the peripheral circuit transistor are set to different values by optimizing the substrate bias or well bias. In addition to this, you can change the gate oxide film thickness,
The concentration of the substrate or well may also be changed. However, compared to these methods, the method of optimizing the substrate bias or well bias described above has the advantage that it does not particularly increase the number of manufacturing steps and does not cause an increase in manufacturing cost.

[Effects of the Invention] As described above, the present invention provides MO
The threshold value of the S transistor is the MO that constitutes the peripheral circuit.
Since the threshold value is set larger than the threshold value of the S transistor, the drive current in the memory cell becomes smaller, which makes it possible to reduce power consumption in the memory cell and ensure normal data retention operation. By increasing the driving current in the peripheral circuits, the operating speeds of peripheral circuits such as human output buffers, decoders, and word drivers can be improved, and the speeds of read and write operations can be improved.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an MO5 type semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a memory cell in the same semiconductor memory device, and FIG. 3 is a characteristic diagram of drain current of a MOS transistor. , FIG. 4 is a characteristic diagram of the subthreshold current of the MOS transistor, and FIG. 5 is a characteristic diagram showing the delay time of the peripheral circuit in the same embodiment compared to the conventional example.
FIG. 6 is a schematic diagram of an MO5 type semiconductor memory circuit according to a second embodiment of the present invention.

Claims (3)

[Claims] (1) In a MOS semiconductor memory device having a memory cell constituted by a MOS transistor and its peripheral circuit, the MOS transistor constituting the memory cell is
An MO characterized in that a threshold value thereof is set larger than that of a MOS transistor constituting the peripheral circuit.
S-type semiconductor memory device. (2) The MOS transistor according to claim 1, wherein the MOS transistor forming the memory cell is applied with a source-substrate reverse bias voltage higher than that of the MOS transistor forming the peripheral circuit. type semiconductor memory device. (3) The MOS transistor according to claim 1, wherein the MOS transistor constituting the memory cell has a source-well reverse bias voltage applied thereto that is greater than that of the MOS transistor constituting the peripheral circuit. type semiconductor memory device.