JPH05110108A - Eprom - Google Patents

Abstract

PURPOSE:To obtain an EPROM capable of low-voltage operation by enabling the readout voltage of a control gate to be OV. CONSTITUTION:When a floating gate 2 stores no charges (erasure state), a memory transistor becomes depletion type by a channel-doped N region 7; when the floating gate 2 stores charges (write-in state), it becomes enhanced type. Therefore, the readout voltage of the control gate 1 can be OV.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to an EP for storing data.
The present invention relates to an erasable programmable read only memory (ROM), and particularly to an EPROM capable of low voltage operation.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view of a memory cell of a conventional N-channel type EPROM. This memory cell has a source (source region) 4 and a drain (drain region) 5 which are formed on a P-type silicon substrate (semiconductor substrate) 8 at predetermined intervals, and a region between the source 4 and the drain 5. A floating gate 2 and a control gate 1 are arranged above and above each other with a space therebetween. A control gate terminal 9 is connected to the control gate 1, and a drain terminal 11 is connected to the drain 5. The source 4 is connected to the GND 12, and the P-type silicon substrate 8 is connected to the GND 13.

FIG. 5 is an equivalent circuit diagram of the memory cell of FIG. In FIG. 5, 15 is the floating gate 2 and P
A capacitance C ₁ between the silicon substrate 8 and 16 is a capacitance C ₂ between the control gate 1 and the floating gate 2, and a capacitance 17 is C ₃ between the floating gate 2 and the drain 5. Next, the operation will be described. When the potentials of the control gate 1, the floating gate 2, the source 4, and the drain 5 are respectively set to V _CG , V _FG , V _S , and V _D , the potential V _FG of the floating gate 2 is V _FG = (C ₂ / C _T ) V _CG + become _{(C 3 / C T) V} D -Q F / C T ··· (1). Here, C _T = C ₁ + C ₂ + C ₃ and Q _F are electric charges accumulated in the floating gate 2. The threshold voltage V _th of the memory transistor of the EPROM is defined by V _th = (C _T / C ₂ ) V _T + Q _F / C ₂ (2) V _T is a threshold voltage when the floating gate transistor is operated as a normal MOS transistor. When Q _F = 0 in the equation (2), the erased state is obtained, and the threshold voltage V _TO at that time is expressed as V _TO = (C _T / C ₂ ) V _T (3).

When writing data, by setting V _D > V _CG -V _th , the memory transistor causes avalanche breakdown, and hot electrons generated near the drain 5 are injected into the floating gate 2 and accumulated. It is done by being done. When a large amount of charge Q _F is accumulated in the floating gate 2, the potential V _FG of the floating gate 2 is lowered from the equation (1), the pinch-off amount of the memory transistor is increased, and the injection of electrons into the floating gate 2 is finished. By accumulating the charge Q _{F in} the floating gate 2, the threshold voltage V _th of the memory transistor of the EPROM becomes as shown in equation (2), and V _th rises by Q _F / C _{2 with} respect to the erased state.

Therefore, the relationship between the control gate potential V _CG and the source / drain current I _{ds in} the erased and written states is as shown in FIG. The read operation is, for example, V _CG ≈5
V and V _D ≈0.5 to 2 V are set so that writing does not occur during reading. V _th > 5 V and V _th <depending on the presence or absence of accumulated charge Q _{F in} the floating gate 2, respectively.
Since it becomes 5 V (≈1 V), by setting the voltage of the control gate 1 to V _CG ≈5 V, the source-drain is ON in the erased state and the source / drain is OFF in the written state to determine the state information. Is possible.

[0006]

Since the conventional EPROM is constructed as described above, the voltage V _CG for reading becomes lower as the power supply voltage becomes lower, so that the source / drain currents in the erased state and the written state are reduced. There is a problem that the difference between I _ds becomes small and it becomes impossible to judge the erased state and the written state, that is, there is a problem that a low voltage operation cannot be performed.

The present invention has been made to solve the above problems, and an object thereof is to obtain an EPROM capable of operating at a low voltage.

[0008]

E according to the invention of claim 1
The PROM is an element that constitutes one memory cell, and is a source region (source 4) of a memory transistor, a drain of the memory transistor, and a source of the select transistor, which are formed on a semiconductor substrate (P-type silicon substrate 8) at predetermined intervals. And a drain region (drain 6) of the select transistor, and a channel dope region (N region 7 by channel doping) is provided between the source region and the region also serving as the source. The floating gate 2 and the control gate 1 are arranged above the channel dope region with a space therebetween, and the select gate 3 is arranged with a space above the region between the region also serving as the source and the drain region. It was done.

In the EPROM according to the second aspect of the present invention, the source region (source 4) of the memory transistor formed on the semiconductor substrate (P-type silicon substrate 8) at a predetermined interval is provided as an element constituting one memory cell. ) And the drain region (drain 14) of the memory transistor, and a channel dope region (N region 7 by channel dope) is provided near the source region side of the region between the source region and the drain region. The floating gate 2 and the control gate 1 are arranged above each other with a space therebetween, and the select gate 3 is arranged above the region between the channel dope region and the drain region with a space therebetween.

[0010]

In the EPROM according to the first aspect of the invention, 1
One memory cell is composed of two transistors, and when the charge is not accumulated in the floating gate 2 (in the erased state), it becomes a depletion type memory transistor by the channel dope region, and when the charge is accumulated in the floating gate 2. In the write state, the memory transistor becomes an enhanced type. Therefore, the read voltage of the control gate 1 can be set to OV.

In the EPROM according to the second aspect of the present invention, one memory cell is formed in one transistor, and when no charge is stored in the floating gate 2 (in the erased state), a depletion type is formed by the channel dope region. It becomes a memory transistor, and when the electric charge is accumulated in the floating gate 2 (in a write state), it becomes an enhanced type memory transistor. Therefore, the read voltage of the control gate 1 can be set to OV.

[0012]

EXAMPLES Example 1. FIG. 1 is an EP according to the invention of claim 1.
It is sectional drawing of the memory cell of ROM. In this memory cell, it is a region (source region) 4 of a memory transistor formed on a P-type silicon substrate (semiconductor substrate) 8 at predetermined intervals, and also serves as a drain of the memory transistor and a source of a select transistor. The drain and source 5 and the drain (drain region) 6 of the select transistor are provided, and the N region 7 by channel doping is provided between the source 4 and the drain and source 5,
The floating gate 2 and the control gate 1 are arranged above the N region 7 at intervals, and the select gate 3 is arranged above the region between the drain / source 5 and the drain 6 at intervals. There is. A control gate terminal 9 is connected to the control gate 1, and a select gate terminal 10 is connected to the select gate 3. A drain terminal 11 of the select transistor is connected to the drain 6 of the select transistor. The source 4 of the memory transistor is connected to the GND 12, and the P silicon substrate 8 is connected to the GND 13.

Next, the operation of the EPROM according to this embodiment will be described. When the electric charge is not accumulated in the floating gate 2, the memory cell is of the depletion type due to the channel dope (N region 7), so that the threshold voltage V _th of the memory transistor becomes V _th <OV. Therefore, in the erased state, when a positive voltage is applied to the drain 5 of the memory transistor, the control gate 1
The voltage V _CG and the current I _ds between the source 4 and the drain 5 of the memory transistor are as shown in FIG.

When writing data to the memory transistor, voltage is applied to the control gate 1 and the drain 5 of the memory transistor so that the drain voltage V _D of the memory transistor and the voltage V _FG of the floating gate 2 become V _D > V _FG. When V _CG and V _D are applied, the memory transistor undergoes avalanche breakdown, and hot electrons are generated near the drain 5 of the memory transistor. Since this hot electron has energy enough to exceed the energy barrier of the gate oxide film, it is pulled by the potential of the floating gate 2, electrons are accumulated in the floating gate 2, and the threshold voltage V _th of the memory transistor rises. When V _th > 0 and a positive voltage is applied to the drain 5 of the memory transistor, the V _CG -I _ds characteristic in the written state becomes the enhanced type transistor characteristic as shown in FIG.

Therefore, the read voltage applied to the control gate 1 can be made OV, and the memory transistor is turned on and off in the erased state and the written state, respectively, as shown in FIG. By applying a positive voltage to the drain 6 and the select gate 3 of the select transistor, a positive voltage is applied to the source 5 of the select transistor, that is, the drain 5 of the memory transistor, and the memory transistor cell can be selected. Since the voltage of the drain 5 of the memory transistor is normally set to 0.5V to 2.0V, the voltages of the drain 6 and the select gate 3 of the select transistor can be lowered, and the EPROM according to this embodiment can operate at a low voltage. Becomes

As described above, the EPR of the above embodiment
The OM is such that the N-type memory transistor is channel-doped to be a depletion type in an erased state and an enhanced type in a written state, that is, when electrons are accumulated in the floating gate. Also, an N-type transistor is arranged in series with the memory transistor,
By connecting the drain of the memory transistor and the source of the N-type transistor, the memory cell is selected by turning on and off the N-type transistor. Since the memory transistor is a depletion type in this way,
V _th <OV in erased state, V _th > OV in written state
Becomes Therefore, the read voltage of the control gate, that is, the word line becomes OV. Read voltage is OV
Therefore, the memory cell cannot be selected only by the bit line and the word line, so the memory cell is selected by the enhanced transistor.

Embodiment 2. FIG. 2 is a sectional view of a memory cell of an EPROM according to an embodiment of the present invention. This memory cell has a source 4 of a memory transistor and a drain 14 of the memory transistor which are formed on a P-type silicon substrate 8 with a predetermined space therebetween, and a region between the source 4 and the drain 14 is closer to the source 4 side. A channel-doped N region 7 is provided, a floating gate 2 and a control gate 1 are arranged above the N region 7 with a space therebetween, and a select gate with a space above the region between the N region 7 and the drain 14. 3 are arranged.
The other components are the same as those in FIG. In the EPROM of the first embodiment described above, one memory cell is composed of two transistors.
The ROM has one memory cell in one transistor.

Next, the operation of the second embodiment will be described. To write data, a positive voltage is applied to each of the select gate 3, the control gate 1, and the drain 14 of the memory transistor, and the voltage V _{SG of} the select gate 3,
The voltage V _D of the drain 14 of the memory transistor is V _SG <
When it is set to V _D , hot electrons due to avalanche breakdown are generated near the drain 14 of the memory transistor. The hot electrons are injected into the select gate 3 having a positive potential, but the hot electrons are also injected into the floating gate 2 by adjusting the gate oxide film thicknesses and voltages of the floating gate 2 and the select gate 3. You can Although the injection efficiency of hot electrons into the floating gate 2 is lower than that of the first embodiment, the operation is similar to that of the first embodiment, and the erased state and the write state when a positive voltage is applied to the select gate 3 and the drain 14 of the memory transistor are written. The V _CG -I _ds characteristic of the state is as shown in FIG. 3, and the read voltage of the control gate 1 becomes OV as in the first embodiment. The voltage of the drain 14 of the memory transistor is normally 0.5V
Since the voltage is set to about 2.0 V, the EPROM according to the second embodiment can also operate at a low voltage.

[0019]

As described above, according to the invention of claim 1,
One memory cell has a source region of a memory transistor formed at a predetermined interval on a semiconductor substrate, a region that also serves as a drain of the memory transistor and a source of the select transistor, and a drain region of the select transistor. A channel dope region is provided between the region also serving as the source, and the floating gate and the control gate are arranged above the channel dope region at intervals, respectively, and between the region also serving as the source and the drain region. Since the select gates are arranged at intervals above the region, they become depletion type memory transistors in the erased state and enhance type memory transistors in the written state, which allows the read voltage of the control gate to be OV. , Motion Voltage is limited to a select transistor, thus there is an advantage that it provides a low voltage operation capable EPROM.

According to the invention of claim 2, in one memory cell, the source region side of the region between the source region of the memory transistor and the drain region of the memory transistor which are formed on the semiconductor substrate at a predetermined interval. A channel dope region is provided close to the channel dope region, a floating gate and a control gate are arranged above the channel dope region at intervals, and a select gate is provided above the region between the channel dope region and the drain region. Since one memory cell is arranged in one transistor, the space is smaller than that of the invention of claim 1 and the effect is similar to that of the invention of claim 1. ..

[Brief description of drawings]

FIG. 1 is a sectional view of a memory cell of an EPROM according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of an EPROM memory according to an embodiment of the present invention.

FIG. 3 shows V _CG -I _{ds of} an EPROM according to an embodiment of the present invention.
It is a figure which shows a characteristic.

FIG. 4 is a cross-sectional view of a memory cell of a conventional EPROM.

FIG. 5 is an equivalent circuit diagram of a conventional EPROM.

FIG. 6 is a diagram showing V _CG -I _ds characteristics of a conventional EPROM.

[Explanation of symbols]

1 Control Gate 2 Floating Gate 3 Select Gate 4 Source of Memory Transistor (Source Region) 5 Drain of Memory Transistor and Source of Select Transistor (Dual Region) 6 Drain of Select Transistor (Drain Region) 7 N Region by Channel Doping (Channel) Doped region 8 P-type silicon substrate (semiconductor substrate) 14 Memory transistor drain (drain region)

Claims (2)

[Claims] 1. A source region of a memory transistor formed on a semiconductor substrate at a predetermined interval, a region serving as a drain of a memory transistor and a source of a select transistor, as an element constituting one memory cell.
Having a drain region of the select transistor, a channel dope region is provided between the source region and the region also serving as the source, and a floating gate and a control gate are arranged at intervals above the channel dope region, An EPROM characterized in that select gates are arranged at intervals above a region between the region also serving as the source and the drain region. 2. An element constituting one memory cell, which has a source region of a memory transistor and a drain region of the memory transistor, which are formed on a semiconductor substrate at predetermined intervals, and between the source region and the drain region. A channel dope region is provided closer to the source region side of the region, and a floating gate and a control gate are arranged above the channel dope region at intervals, respectively, and above the region between the channel dope region and the drain region. An EPROM characterized in that select gates are arranged at intervals.