JP3422812B2 - Rewriting method of nonvolatile semiconductor memory cell - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory (hereinafter referred to as "EEPROM") memory cell rewriting method.
It can be used for a semiconductor memory device having a built-in memory.

[0002]

[Prior art]

(Reference 1) Single-transistor electrically programmable memory device and method of manufacturing the same Patent application publication Sho 61-127179 (Reference 2) CMOS VLSI design Supervised by Takuo Sugano 1989 P172-173 (Reference 3) Current state of flash memory And future prospects The Institute of Electronics, Information and Communication Engineers ICD91-134 (Reference 4) Flash memory using word negative voltage erase method ICD91-135 (Reference 5) 16M flash cell technology converges Nikkei Microdevice July 1991 Issue (Reference 6) Flash EEPROM cell scaling based on tunn
el oxide thinning limitations. 1991 VLSI symposium technology (Reference 7) "Silicon thermal oxide film and its interface" pp355-371 Realize Co., Ltd.

An electrically rewritable and non-volatile memory storage element (hereinafter referred to as an EEPROM memory cell) is
Many have been proposed since the early 1980s. Among them, a typical example is an EEPROM memory cell having a floating gate as a charge retention layer,
It is described in 3, 4.

An EEPROM memory cell having a floating gate has a crystalline semiconductor silicon substrate and a source portion and a drain portion (for example, boron as an impurity) formed by doping an impurity opposite to a substrate impurity on the substrate surface. In the case of a doped P-type substrate, the source part and the drain part are in contact with the arsenic or phosphorus-doped N-type layer), the channel region for conducting minority carriers between the source part and the drain part, and the upper part of the channel region. A thin oxide film and a floating gate formed of polycrystalline conductive polysilicon in contact with the upper part of the thin oxide film;
And a control gate formed of polycrystalline polysilicon in contact with an upper portion of the floating gate.

The principle of storage of the EEPROM memory cell is to inject and store charges (electrons or holes) in the floating gate to allow the threshold voltage (threshold voltage) of the memory cell to be seen from the control gate. Is
The voltage applied to the control gate when minority carriers are induced in the channel region is changed. As a method for injecting charges into the floating gate, there are conventional examples as shown in FIGS. 7 and 8 (for example, the conventional examples are described in Documents 1 and 2).

In the conventional example shown in FIGS. 7 and 8, one MOS-type enhancement N-channel transistor (20 to 21 in FIG. 7) is used to select and store 1-bit information.
22 to 23) and one memory cell (24 to 25 to 26 to 27 in FIG. 7) having the floating gate. In FIG. 7, 4-bit information can be selected and stored.

In FIG. 7, 200 and 201 are word lines, 200 is connected to the gates of 18, 20 and 21, and 201 is connected to the gates of 19, 22 and 23. 203 and 204 are bit lines, 203 is connected to the drains of 20 and 22, and 204 is connected to the drains of 21 and 23. Reference numerals 18 and 19 denote MOS type enhancement N-channel transistors for byte selection, and drains of 18 and 19 are sense lines 202.
It is connected to the. Transistors 18, 19, 20, 2
The threshold voltage of 1, 22, 23 is, for example, 1 V (volt)
Is. 18 sources to 24 and 25 control gates,
The source of 19 is connected to the control gates of 26 and 27. 20 sources and 24 drains, 21 sources and 25 drains, 22 sources and 26 drains, 23
Source and 27 drain are connected to each other by an N-type impurity diffusion layer.

FIG. 8 is a sectional view taken along the line AB of FIG. 7, showing one bit. 220 is a P-type silicon substrate, 205 ', 208 and 203' are N-type impurity diffusion layers, 223 and 224 are silicon thermal oxide films (also referred to as gate oxide films) on the channels, and 225 is 223.
Silicon oxidization film (eg 2
The film thicknesses of 23 and 224 are 50 nanometers and the film thickness of 225 is 10 nanometers. 226 is a floating gate formed of, for example, polycrystalline polysilicon, 20
6 is a control gate formed of, for example, polycrystalline polysilicon, 227 is an interlayer insulating film between 226 and 206 (for example, a thermal oxide film of about 25 nanometers), and 200 is formed of, for example, polycrystalline polysilicon. The gate was opened.
Reference numeral 228 is an insulating layer, 203 is a bit line mainly made of aluminum, and 229 is a contact portion connecting 203 and 203 '. The polysilicons 200 and 206 are electrically connected to other memory cells, but the floating gates are electrically insulated from the other memory cells.

FIG. 9 shows an electrically equivalent circuit of the memory cells of FIGS. 7 and 8. In FIG. 9, 206 is a control gate, which is a voltage Vg.
The voltage Vd is applied to the drain at 208, the voltage Vs is applied to the source at 205, and the voltage Vsub is applied to the substrate at 220. In FIG. 8, the oxide films 224 and 225 and the interlayer insulating film 227 can be electrically expressed as capacitance, and the capacitance between 226 and 206 can be represented by Cip, 22.
Let Csub be the capacitance between 6 and 208. 22
Reference numeral 6 denotes a floating gate. When this voltage is Vf, Vf is Cip (Vg-Vf) = Cs (Vf-Vs) + Csub (Vf-Vsub) + Cd (Vf-Vd).・ (1) When Vs = Vsub = Vd = 0V in the equation (1), Vf ＝ Vg ・ Rp where Rp = Cip / (Cip + Cd + Csub + Cs) ・ ・ ・ (2) It Rp is called a coupling ratio, and generally Rp = 0.55 to 0.7.

A conventional method of rewriting and reading the memory cells shown in FIGS. 7 and 8 will be described below. Table 1 shows an example of each node voltage in each operation mode. Rewriting is divided into writing and erasing. Consider the case where the memory cell 24 of FIG. 7 is selected.

[0011]

[Table 1]

When writing 24, 200 is set to 2
By opening 0V, 202 to 0V, 203 to 20V, and 205, 18, 20, and 21 are turned on, and 2
06 is 0V and 208 is about 18V (20V-the threshold voltage of the transistor 20 (including the substrate effect)). As a result, a voltage of about 7 V is induced in the floating gate 226. Since the film thickness of 225 is 10 nanometers, 2
The potential difference between 26 and 208 causes a Farrer-Nordheim tunnel current to flow in 225. The Farrer-Nordheim tunnel current generally flows when an electric field of 10 megaelectron volts / centimeter (MeV / cm) or more is applied to a thin oxide film. Due to this Farrer-Nordheim tunnel current, holes are injected from 208 to 226, and the threshold voltage of the memory cell becomes low (for example, if the initial threshold voltage of the memory cell is 2 V, then −2 after writing). ~ -3V). At this time, 204 is 0
With respect to V, since 201 is 0V, no high voltage is applied to the memory cells other than 24, so that no data is written.

At the time of erasing, 200, for example, 20V, 20
By applying 20V to 2 and 0V to 203,
206 becomes about 18V and 208 becomes 0V. This makes 2
Approximately 11 V is induced in 26, a Farrer-Nordheim tunnel current flows through 225, electrons are injected into 226, and the threshold voltage of the memory cell becomes high (for example, 6 to
7V). Since 201 is 0V at this time, 207 is in an open state and 26 and 27 are not erased. But 204
Is 0V, so 25 is erased like 24. In other words, at the time of erasing, all memory cells connected to the same node as 206 are erased and the threshold voltage becomes high.

At the time of reading 24, for example, 5 is added to 200.
By applying 3V to V, 202 and 2V to 203,
18 and 20 are turned on, and the drain of 24 is 2
V, the control gate becomes 5V. At this time, if the threshold voltage of the memory cell is as high as 6 to 7 V, the memory cell is in the off state and no current flows between the drain and the source. When the threshold voltage of the memory cell is as low as −2 to −3 V, the memory cell is in the ON state and a current flows between the drain and the source. The stored information is read out depending on the presence or absence (or the magnitude) of this current.

[0015]

2. Description of the Related Art In the above-mentioned conventional example, since the charge is injected by utilizing the Farrer-Nordheim tunnel current upon rewriting, a relatively small current (for example, 10 picoampere per memory cell from 10 picoampere per memory cell) at the time of rewriting. It has the advantage of requiring only 1000 picoamps. However, as a drawback, in order to selectively perform writing in the memory array, 20, 21, 2 in FIG.
2 and 23, another transistor for separating the memory cells from each other is required (see 20, 21, 2 in FIG. 7).
It will be understood that when there are no 2 and 23, when writing to 24 memory cells, they are also written to 26 memory cells). Therefore, if one isolation transistor is provided for each bit, the occupied area is required to be, for example, 80 to 150 (square micron). When the memory cells are integrated on a large scale, this drawback hinders the increase in size.

[0016]

Therefore, the present invention provides a rewriting method of an EEPROM memory cell which enables rewriting and reading with a single power supply voltage and facilitates lowering of the power supply voltage, and selects at the time of writing. The present invention provides a memory cell having a minimum transistor configuration that does not require a separation transistor for writing data selectively.

[0017]

In order to solve the above-mentioned problems, the present invention has a plurality of EEPROM memory cells arranged in a matrix, and when a selected memory cell is written, the control gate of the memory cell is grounded. Lower first
Voltage is applied to the drain of the memory cell, and a second voltage higher than the ground potential is applied to the drain of the memory cell. Due to the potential difference between the first voltage and the second voltage, the charge is injected from the charge injection layer of the memory cell. The at least one second memory cell that is not selected and has a control gate electrically common to the control gate of the selected memory cell by pulling the memory cell to the drain by a tunneling phenomenon. A third voltage, which is lower than the second voltage, is applied to the drain, and the third voltage is a voltage that does not cause the tunnel phenomenon even with a potential difference from the first voltage of the control gate, A first voltage is applied to a control gate of at least one unselected third memory cell having a drain electrically common to the drain of the selected memory cell. A fourth voltage that is higher than the second voltage and is lower than the second voltage is applied, and the fourth voltage is a voltage that does not cause the tunnel phenomenon even in the potential difference from the second voltage of the drain of the memory cell. And a CHE (Channel Hot Electron) injection for erasing the EEPROM memory cell, and a negative charge is injected into the charge injection layer of the memory cell to bring the memory cell to the erase level. We have proposed a rewriting method characterized by this.

[0018]

According to the present invention, the charge is extracted from the charge injection layer to the drain by using the tunnel phenomenon when writing to the EEPROM memory cell, but unlike the conventional case, the control gate of the selected memory cell is negatively charged. High and low voltage applied to the drain (for example, 5V and 0
V) controls the presence or absence of the tunnel phenomenon, that is, the presence or absence of writing. A negative voltage is applied to the control gate of the selected memory cell, and the control gate of an unselected memory cell in which the selected memory cell and drain are electrically common is higher than the negative voltage and lower than the threshold voltage of the memory cell. A tunneling phenomenon is prevented by applying a voltage (for example, if the negative voltage is -8 V and the threshold voltage of the memory cell is 2 V, the voltage of the control gate of the non-selected memory cell is 0 V, for example).

Here, the tunnel phenomenon means either a Farrer Nordheim tunnel or a direct tunnel. Further, the charge injection layer does not mean only a floating gate of polysilicon, but also a layer such as an insulating layer made of nitride capable of injecting charges.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 7 show an embodiment of the present invention. In FIG. 1, 10, 11, 12, and 13 are EEPROM memory cells having a floating gate as a charge injection layer, for example, and have a drain terminal, a source terminal, a control gate terminal, and a floating gate. Reference numerals 100 and 101 denote word lines, and an arbitrary word line is selected / unselected by a decoder circuit in the column direction. 100 is connected to 10 control gates and 11 control gates, and 101 is connected to 12 control gates and 13 control gates. Bit lines 102 and 103 are selected by a decoder circuit in the column direction. 102 is connected to 10 drains and 12 drains, 103 is 11
Is connected to the drains of and. 10
Reference numeral 4 denotes a source line, to which sources 10, 11, 12, 13 are connected.

FIG. 2 shows a sectional view of the EEPROM memory cell of this embodiment. This is what is seen on the plane AB of FIG. Reference numeral 105 is a semiconductor silicon P-type substrate, and 104 'and 102'
Is an N-type diffusion layer serving as a source and a drain. 10
Between 2'and 104 ', a channel region 11 that induces a conductive layer (channel) of electrons according to a gate voltage value.
0, and a thin insulating film 106 (for example, a thickness of 1
There is a thermal oxide film of 0 nm. The width of the channel region is, for example, 0.6 to 1 micron.

A floating gate 109 made of conductive polycrystalline polysilicon is provided on the thin insulating film, and the thickness of 109 is, for example, 150 nanometers.
A thin insulating layer (for example, a 25-nm-thick insulating layer formed of an oxide film and a nitride film) 107 is provided above 109, and a control gate formed of, for example, conductive polycrystalline polysilicon is provided above 107. There are 100. The thickness of 100 is, for example, 250 nanometers. A bit line 102 is mainly made of aluminum, and is connected to 102 ′ through a contact portion 108. Between 102 and 100 is an insulating layer 111. The threshold voltage of the memory cell when no charges are injected into the floating gate is, for example, 2V.

FIG. 3 shows a plan view of the memory cell in this embodiment. Reference numeral 150 is an N-type diffusion layer (drain, source and source line of memory cell), 151 is a word line (= control gate), 152 is a floating gate, 154 is a bit line, and 153 is a contact portion. The occupied area for one bit of the memory cell in FIG. 3 is, for example, 1 to 10 (square micron).

An embodiment of the rewriting method of the present invention will be described with reference to FIGS. 1, 2, 3 and 4. FIG. 4 shows the applied voltage at the time of writing in FIG. First 10
At the time of writing, the voltage of 100 is set to Vw1 and, for example, Vw1 = −8V is applied. The voltage of 102 is set to Vprg1 and, for example, Vprg1 = 6V is applied. Furthermore, the voltage of 105 is Vs
ub, for example, Vsub = 0V, the voltage of 104 is Vas, and 104 is left open, for example. The voltage relationship at this time is Vprg1> Vsub to 0> Vw1. At this time, since a negative voltage is applied to the control gate, the memory cells 10, 1
1 is in the off state and no channel is formed.

When the above voltage is introduced into the equation (1) and the coupling ratio is set to 0.6, the potential difference between the floating gate 109 and the drain 102 'becomes about 10.5V. Due to this potential difference, a Farrer-Nordheim tunnel current flows, and electrons are extracted from 109 to 102 '. The memory cell to be written is in the erase level in advance, and the threshold voltage becomes low because electrons are extracted. To prevent the threshold voltage from becoming too low,
The threshold voltage can be set to, for example, 2 V by appropriately setting the writing time or the like.

Further, in writing 10 times, the voltage of 101 is set to Vw2, and Vw2 = 0V is applied (Vw2> Vw1).
Then, when the voltage of 103 is set to Vprg2 and 0V is applied, for example, a potential difference of 8V is generated between the control gate and drain of 11, and thus the floating gate of 11 has about 7V.
Although a voltage of V is induced, the Farler-Nordheim current does not occur at this potential difference, and the threshold voltage of 11 does not change. Also, there are about 5. between the 12 control gates and drains.
A potential difference of 5 V is generated, but of course, even with this potential difference, the Farrer-Nordheim tunnel does not occur, and the threshold voltage of 12 does not change. In No. 13, since there is no potential difference between the drain and the source, there is no change in the threshold value.

Next, a method of erasing in one embodiment of the present invention will be described. FIG. 5 shows the applied voltage at the time of erasing. In erasing the memory cell of 10, the voltage of 100 is set to Vers1, for example, Vers1 = 12V is applied, the voltage of 104 is set to Vse1, for example, Vse1 = 5V, and the voltage of 102 is set to Vse2, for example, Vse2 = 0V is applied. . In this case Vers1>Vse1> Vse2
There is a voltage relationship of ≧ 0V. Since 12V is applied to the control gate of 10 and 5V to the source and 0V to the drain, hot electrons are generated near the source and CHE injection occurs.
Threshold voltage becomes high. At this time, the voltage of 101 is Vers
2 and, for example, Vers2 = 0V is applied (Vers1> Vers
2) The control gate of the memory cell 12 is 0V and the drain is 0V.
V and source are 5 V, 12 remains in the off state, and its threshold voltage does not change.

Further, the voltage of 103 is set to Vse3, for example, Vse3 =
When 5V is applied (Vse3 = Vse1> Vse2), the control gate of 11 becomes 12V, the drain becomes 5V, and the source becomes 5V. Since the control gate voltage is 12 V, 11 turns on and a channel is formed, but since there is no potential difference between the drain and source, no channel current flows and CHE injection does not occur. Since the Farrer-Nordheim tunnel current does not occur because the potential difference is small, the threshold voltage of 11 does not change. Also, 13 control gates have 0V and drains have 5V.
Although V and 5 V are applied to the source, the threshold voltage of 13 does not change because it is off and the potential difference is small.

Next, the timing of voltage application in this embodiment is shown in FIG. 6 and will be described below. As described above, in order to raise the threshold of the memory cell 10 by CHE injection and change it to the erased state, Vers1 (= 12) is set to 100.
V), Vse2 for 102 (= 0 V), Vse1 for 104 (= 5)
V) must be applied. By the way, Vse3 (= 5V) is applied to 103 in order to prevent a potential difference between the drain and the source of the non-selected memory cell 11, but the timing of applying this voltage is the same as the timing of applying Vse1 to 104. Moreover, it is preferable that Vers1 (= 12V) is not applied to 100, that is, 0V. This is because if either 103 or 104 is biased to 5V and one of them is at 0V, that is, a potential difference between the source and drain of the memory cell 11 is instantaneously generated, and at that time, 100 Vers1 ( =
This is because CHE injection occurs instantaneously when 12 V) is applied, and the erase operation is mistakenly performed.

For the above reason, as shown in FIG. 6, first, Vse1 = Vse3 = 5V is applied to 103 and 104 at the same time, respectively, and then Vers1 = 12V is applied to 100 as an erase pulse. It has become possible to prevent According to the above method, if 103
Even if the timing of applying Vse1 = Vse3 = 5V to and 104 is slightly deviated due to the circuit operation, at the moment when the potential difference occurs between the source and drain of the non-selected memory cell 11, Vers1 = 12V is set to 100. Not applied (0
V), the threshold voltage fluctuation due to CHE injection does not occur.

Although a voltage value is shown for the purpose of explaining the present embodiment, this voltage value is changed depending on the structure of the memory cell, particularly the capacitance value of the oxide film or the interlayer insulating film and the coupling ratio value. What is necessary is just to satisfy the relations described in the claims.

As described above, according to the write method of the embodiment of the present invention, it is possible to realize a memory array which does not require the necessary isolation transistor while using the tunnel phenomenon, and occupies a large area compared with the prior art. Can be reduced. Furthermore, according to the present invention, at the time of reading, the voltage applied to the drain of the memory cell can be made higher than that of the prior art because channel hot electron injection is not used for writing (for example, 1 V in the prior art).
On the other hand, in the embodiment of the present invention, the on-current of the memory cell at the time of reading can be made larger than 2V.

As a result, according to the embodiment of the present invention, the reading speed at the time of reading can be increased. Further, according to the embodiment of the present invention, since the Farrer-Nordheim tunnel current is used for rewriting, there is an advantage that a low voltage can be easily realized with a single power supply voltage. Further, according to the embodiment of the present invention, erasing is an operation of increasing the threshold voltage of the memory cell and does not cause the problem of overerasing during erasing.

Next, the effect of the erasing method in one embodiment of the present invention will be described. According to the present embodiment, the Farrer-Nordheim tunneling at the drain is used for writing, and the CHE injection from the source direction is used for erasing, which has the following advantages over the prior art. One is that in the prior art, at the time of erasing, selective erasing was only possible in byte units (or word units or sector units), whereas in the embodiment of the present invention, erasing in bit units is enabled. There is. Moreover, according to the structure of the non-volatile semiconductor memory device in the embodiment of the present invention shown in FIG. 1, in the prior art, in order to erase in byte units (or word units or sector units), the byte ( Alternatively, it is necessary to prepare a transistor for word or sector selection separately from the memory cell, or source line in byte units (word, sector)
However, according to this embodiment,
It is possible to realize erasing on a bit-by-bit basis without using these extra transistors. As a result, there is an advantage that the memory cell which is not necessary in the conventional technique is not rewritten and the area occupied by the memory array can be reduced.

Further, in the erase mode in the embodiment of the present invention, the source line is connected to the unselected bit line connected to the unselected memory cell located on the same control gate as the selected memory cell. Since the same potential is applied, it is possible to prevent the unselected cells from being erased by mistake. Moreover, the erase pulse during the erase operation is applied to the control gate after applying the same potential as the source line to the non-selected bit line, so if the same potential is applied to the non-selected bit line and the source line. Even if the timing is slightly deviated due to the circuit operation, at the moment when the potential difference occurs between the source and drain of the non-selected memory cell, the voltage is not applied to the control gate (0V), so CHE injection is performed. There is also an advantage that the threshold voltage fluctuation due to does not occur.

Further, when reading stored information from a memory cell, a constant voltage is applied to the drain of the selected memory cell and the source is grounded to read the information both in the present invention and in the prior art. However, according to the embodiment of the present invention, by performing the CHE injection from the source direction,
Accidental erasure due to drain voltage (erroneous writing in conventional technology)
There is an advantage that the drain voltage at the time of reading can be set higher than that of the conventional technique, and the reading speed can be further improved. Also, since the drain voltage during reading and the source voltage during erasing are independent, CH
Another advantage is that lowering the E injection voltage is easier than in the prior art.

Although some typical embodiments of the present invention have been described above, the present invention can be implemented with some application or improvement without impairing the gist of the present invention. However, it goes without saying that they are included in the scope of the present invention. Furthermore, the present invention does not limit the structure of the memory cell. A structure that can realize the rewriting method within the scope of the claims is sufficient.

[0038]

According to the present invention described in detail above, the non-volatile semiconductor memory which has the above-mentioned structure can be rewritten and read with a single power supply voltage and can easily be made to have a low power supply voltage. A cell rewriting method can be provided, and by selectively writing at the time of writing, it is possible to use a memory cell having a minimum transistor configuration that does not require a separation transistor, and thus to improve the degree of integration. be able to.

[Brief description of drawings]

FIG. 1 is a diagram showing an electrical connection of a memory cell according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a memory cell portion according to an embodiment of the present invention.

FIG. 3 is a plan view of a memory cell according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining an applied voltage in writing in the embodiment shown in FIG.

FIG. 5 is a diagram for explaining an applied voltage at the time of erasing in the embodiment shown in FIG.

6 is a diagram showing the timing of voltage application during erase in the embodiment shown in FIG.

FIG. 7 is a diagram showing electrical connection of memory cells in a conventional example.

FIG. 8 is a sectional view of a memory cell portion in a conventional example.

9 is a diagram showing an electrically equivalent circuit of the memory cell of FIGS. 7 and 8. FIG.

[Explanation of symbols]

10 cell transistor (selection) 11, 12, 13 cell transistors (non-selected) 100, 101 word line (control gate) 102,103 bit line 102 'Drain diffusion layer (N +) 104 source line 104 'Source diffusion layer (N +) 105 P type silicon substrate 105 'substrate potential 106 thin insulating film 107 insulating layer 108 contacts 109 floating gate 110 channel area 111 Interlayer insulation film 112 High concentration P type diffusion layer 113 photoresist 114 BF2 ion 115 Arsenic ion

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/792 (56) References JP-A-3-74881 (JP, A) JP-A-4-105368 (JP, A) Kaihei 4-186768 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 16/02 G11C 16/04 H01L 27/115 H01L 29/788 H01L 29/792

Claims (6)

(57) [Claims] 1. A plurality of electrically rewritable nonvolatile semiconductor memory cells, wherein the plurality of memory cells are arranged in a matrix, and the memory cells include a drain electrode, a source electrode, and the source. A channel region between the electrode and the drain electrode, a thin insulating film on the channel region and a control gate electrode, and a charge injection layer between the control gate electrode and the channel region, The plurality of memory cells have a write level depending on the result of writing and an erase level depending on the result of erasing. When writing to the selected memory cell, a first voltage lower than the ground potential is applied to the control gate electrode of the memory cell. Then, a second voltage higher than the ground potential is applied to the drain electrode of the memory cell so that the first voltage and the second voltage are Due to the potential difference, charges are extracted from the charge injection layer of the memory cell to the drain electrode by a tunnel phenomenon to bring the memory cell to a write level, and at the time of writing, the control gate electrode of the selected memory cell is electrically connected to A third voltage lower than the second voltage is applied to the drain electrode of at least one unselected second memory cell having a control gate electrode connected to A voltage that does not cause the tunnel phenomenon even with a potential difference from the first voltage of the control gate electrode of the second memory cell, and is electrically connected to the drain electrode of the selected memory cell during the writing. The control gate electrode of at least one unselected third memory cell connected to the The tunnel voltage even when the fourth voltage is higher than the write level of the memory cell and the fourth voltage is different from the second voltage of the drain electrode of the third memory cell. The voltage of the non-volatile semiconductor memory cell is a voltage that does not cause the above-mentioned memory cell, and in erasing the selected memory cell, negative charges are injected into the charge injection layer of the memory cell to set the erase level. . 2. To erase the selected memory cell, a fifth voltage is applied to a control gate electrode of the memory cell and a sixth voltage higher than a ground potential is applied to a source electrode of the memory cell, By injecting hot electrons (electrons thermally excited) from the channel region of the memory cell into the charge injection layer of the memory cell by the fifth voltage and the sixth voltage, the memory cell is set to the erase level. The method for rewriting a nonvolatile semiconductor memory cell according to claim 1, wherein the nonvolatile semiconductor memory cell is rewritten. 3. At least one unselected second memory cell having a control gate electrically connected to the same control gate as the selected memory cell when erasing the selected memory cell. 3. The rewriting method for a nonvolatile semiconductor memory cell according to claim 2, wherein a seventh voltage higher than the ground potential is applied to the drain electrode of. 4. The non-volatile semiconductor memory cell rewriting according to claim 3, wherein the sixth voltage and the seventh voltage are at the same level when erasing the selected memory cell. method. 5. When erasing the selected memory cell, the sixth voltage applied to the source electrode of the second memory cell and the seventh voltage applied to the drain electrode are simultaneously applied or one of them is applied first. 4. The rewriting method of a nonvolatile semiconductor memory cell according to claim 3, wherein the fifth voltage is applied to the control gate after that. 6. When erasing the selected memory cell, the sixth voltage application to the source electrode of the second memory cell and the seventh voltage application to the drain electrode are simultaneously performed. The non-volatile semiconductor memory cell rewriting method according to claim 3,