JP2682393B2 - Static type semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static semiconductor memory device, and more particularly to improvement of a memory cell using a thin film transistor as a load.

[0002]

2. Description of the Related Art As a memory cell of a static semiconductor memory device, there is one using a complementary flip-flop. That is, as shown in FIG. 5, a P-channel type MOS (generally speaking, MIS) transistor Q1 for load,
Q2 and N-channel type MOS transistors Q3 and Q4 for driving are connected in series between the power supply Vcc and GND, and 2
One inverter is configured and the input and output of these inverters are connected to each other. In addition, the node N1 of each inverter,
N2 is connected to bit lines BL and * BL via N channel MOS transistors Q5 and Q6 as transfer gates. Further, the gates of the MOS transistors Q5 and Q6 are connected to the word line WL.

Recently, a thin film transistor (TF) has been used as the load P-channel MOS transistors Q1 and Q2 shown in FIG.
It is known that T) is used to achieve high integration and reduce power consumption (see Japanese Patent Laid-Open No. 14565/1990). An example of a static memory cell using a thin film transistor will be described with reference to FIGS. 6 is a plan view and FIG. 7 is a sectional view taken along the line AA of FIG.

P1, P2, and P3 are N ^- type impurity regions provided in the P ⁻ type single crystal silicon substrate 1 (FIG. 7), for example, and serve as source regions and drain regions of the transistors Q3 to Q6. The first wiring layers S1, S2, S3 are
Field provided on the oxide film 2 and the gate oxide film 3 (FIG. 7), polycrystalline silicon layer and the refractory metal disposed thereon _{(MoSi 2, Ti n Si 2} , TiSi 2, WSi 2) layer A polycide layer formed of the transistors Q3 to Q6
Acts as a gate electrode of. In addition, the polycide layer S1
Also functions as a word line WL. Second layer wiring layer GND
Is a polycide layer or a refractory metal silicide layer provided via the insulating layer 4 (FIG. 7), to which a ground potential is applied. The third wiring layers TG1 and TG2 are the insulating layers 5
The polycrystalline silicon layer provided via (FIG. 7) acts as the gate electrodes of the thin film transistors Q1 and Q2. The fourth wiring layers TB1 and TB2 are polycrystalline silicon layers crystallized by annealing the non-crystallized silicon provided via the insulating layer 6 (FIG. 7), and are the source regions of the thin film transistors Q1 and Q2. Functions as a channel region and a drain region. In this case, the channel region ^{is, 1 × 10 12 ~1 × 10} 13 / cm ² or about N-type impurity atoms (e.g. P, A _S) is injected, also in the source and drain regions, 1 × 10 ¹⁵ ~ 1 x 10
^{About 16} / cm ² P-type impurity atoms (for example, B) are implanted. The fifth wiring layer (bit line) BL, * BL is
It is an aluminum layer formed through the insulating layer 7 (FIG. 7).

C1 to C11 are contacts, which operate as follows. C1 ... Transfer gate Q5 and bit line BL are connected. C2 ... Transfer gate Q6 and bit line * BL are connected. C3 ... Connects the drain of the MOS transistor Q3 and the gate of the MOS transistor Q4. C4 ... Wiring layer S2 and gate TG of thin film transistor Q2
2 is connected. C5 ... Gate TG2 of thin film transistor Q2 and thin film transistor
The wiring layer TB1 which is the drain region of the transistor Q1 is connected. C6 ... Impurity regions P2 and MO of the transfer gate Q6
It is connected to the gate S3 of the S transistor Q3. C7 ... Drain regions P3 and M of the MOS transistor Q4
It is connected to the gate S3 of the OS transistor Q3. C8 ... Wiring layer S3 and gate TG of thin film transistor Q1
Connect with 1. C9 ... The gate TG1 of the thin film transistor Q1 is connected to the drain region TB2 of the thin film transistor Q2. C10 ... Connects the source region P3 of the MOS transistor Q4 and the ground potential line GND. C11 ... Connects the source region P1 of the MOS transistor Q3 and the ground potential line GND.

Next, the operation of the memory cell when reading / writing the static semiconductor memory device of FIGS. 5 to 7 will be described. First, when writing data "1" to the selected memory cell, each bit line BL, * BL is set to high level ("1") and low level ("0"), and these levels are set to transfer gates Q5 and Q6. Are transmitted to the storage nodes N1 and N2, respectively. At this time, the high level written in the node N1 is the transfer gate Q.
V _cc due to the threshold voltage V _{TN of} 5 and the substrate bias effect α
−V _TN −α, for example, when V _CC = 3V, V _TN
= 0.7V and α = 0.3V, it is about 2V.
This high level activates in the direction of turning off the thin film transistor Q2 and in the direction of turning on the MOS transistor Q4. Further, the low level of the node N2 activates in a direction of turning on the thin film transistor Q1 and in a direction of turning off the MOS transistor Q3. Then, after a time sufficiently longer than the time constant determined by the capacitance and resistance of these transistors and the storage node, the voltage of the node N1 is supplied from V _CC -V _TN -α because the MOS transistor Q4 is turned on. It goes to the voltage level V _CC . When writing data “0”, the levels of the bit line pair BL, * BL are reversed,
The memory cell operates in reverse.

Next, reading will be described assuming that the information stored in the memory cell is data “1”, that is, the thin film transistor Q1 and the MOS transistor Q4 are on, and the thin film transistors Q2 and Q3 are off.
Since the bit line pair BL, * BL is pulled up to the power supply voltage V _CC level by the load transistor (not shown) of the bit line, the word line WL becomes high and the bit line pair BL, * BL is selected. Then, the low level of the node N2 discharges the power supply potential of the bit line * BL via the MOS transistors Q6 and Q4, and continues to fall only while the word line WL is selected. On the other hand, the high level of the node N1, that is, the bit line BL is connected to the MOS transistor Q3.
Remains high because it is off. That is, the bit line BL and the bit line * BL are respectively V _CC ,
The voltage becomes V _CC -V _B (V _B : potential lowered during the period when the word line WL is selected), and this difference potential is amplified by a sense amplifier (not shown) and read. The minimum power supply voltage of the power supply voltage V _CC at which reading and writing can be performed is referred to as a drivable power supply voltage limit value.

However, when the static semiconductor memory device is miniaturized and the channel width of the transfer gate transistor is reduced, the narrow channel effect is caused.
The threshold voltage V _TN of the transfer gate transistor tends to be higher than that of a transistor having the same channel length and a wide channel width. Therefore, as mentioned above,
The potential of the node immediately after writing the high level is V _CC -V
Since it becomes _TN- α, the tendency for V _TN to increase due to the progress of miniaturization is that the potential of the node V _CC -V immediately after writing is high.
_TN- α is made lower than the power supply voltage V _CC , and as a result, the memory cell becomes unstable. As an actual value, V _CC -V _TN -α immediately after writing is 1.8 V when V _CC = 3 V because V _TN is increased by about 0.2 V. The most important thing in such a read / write operation is not to destroy the cell data, and for that purpose, it is necessary to quickly bring the memory cell into a stable state. That is, as described above, the potential V _CC -V _TN- immediately after writing to the node N1.
To bring α to V _CC quickly.

Next, the data holding voltage will be described.
After the power supply voltage V _CC within a certain operation guarantee is set to V _CC1 and the data is written in the memory cell, the memory cell is set to the standby state, and after a certain time, the power supply voltage V _CC is lowered to V _CC2 to hold the data. At the time of reading, the power supply voltage V _CC2 is raised to V _CC1 and after a certain time, the chip is selected and read by the above read operation. It refers to lower values of the voltage V _CC2 write reading of data is possible in such a case the data holding voltage. Generally, the data holding voltage V _CC2 is finally determined by the node leak current LN of the diffusion layer and the sub-threshold leak current LS of the transistor Q3 unless some electric charge is supplied to the high-level node N1. The data reaches the ground potential GND level and data cannot be held correctly. Therefore, it is necessary to supply the charges by the thin film transistor Q1. If the ON current IONV _CC2 of the thin film transistor Q1 and the leak currents LN and LS have the following relationship when V _CC = V _CC2 , the high potential of the node N1 can be held. IONV _CC2 >> LN + LS That is, IONV _CC2 is better than LN + LS, so that data can be held stably and the data holding voltage V _CC2 can be lowered. As an actual value, I
ONV _CC2 is about 1 × 10 ^-9 A, LN is 1 × 10 ^-13 A
, LS is about 1 × 10 ^-15 A, V _CC2 is 1.8V
It is about.

[0010]

However, the above-mentioned conventional memory cell adopts a multi-layer wiring structure to reduce the area, and aluminum bit lines BL, * BL are formed above the thin film transistor via the insulating layer 7. Is wired. Moreover, the aluminum bit lines BL and * BL on the channel region of the thin film transistor connected to the high level node are at the V _CC level during the above-described writing and standby (during data retention). The threshold voltage of the thin film transistor is about 0.2V higher than that when there is no influence of the bit line. As a result, at the time of writing, to V _CC -V _TN -α of the high level node becomes V _CC, or cells increases the time required to stabilize a high drivable supply voltage correctly can write There is a problem of becoming.
Further, during data retention, there is a problem that the current IONV _CC2 decreases and the above-mentioned data retention voltage V _CC2 rises. That is, the memory cell having the conventional structure shown in FIGS. 5 to 7 has a problem that the drivable power supply voltage value and the data holding voltage are deteriorated by about 0.3V. Also,
Electric field to the channel region of the thin film transistor
Channels are shielded by a shield electrode to reduce the influence.
There is one that protects an area (see Japanese Patent Laid-Open No. 4-2995).
No. 68). However, in this case, this seal
Since the electrode is formed in a layer separate from the ground potential layer,
There is a problem that the number of manufacturing steps increases and the manufacturing cost is high.
Was. Therefore, the object of the present invention is to increase the manufacturing cost.
Without reducing the drivable power supply voltage and the data holding voltage of the static memory cell.

[0011]

In order to solve the above-mentioned problems, the present invention provides a load transistor and a drive transistor.
Static type semiconductor having memory cells consisting of
In storage devices, electric fields from conductive layers other than memory cells
Of the reference potential layer for preventing the influence of
The quasi-potential layer is composed of the same layer.

[0012]

According to the above means, the influence of the electric field inside the memory cell by the conductor outside the memory cell, for example, the bit line is eliminated.

[0013]

1 is a plan view showing a first embodiment of a static semiconductor memory device according to the present invention, and FIG. 2 is a line B- of FIG.
It is a B sectional view. 1 and 2, the polycrystalline silicon layers TG1 and TG2 as the gate electrodes of the thin film transistors Q1 and Q2 are used as the second wiring layer, and the polycrystalline silicon layers as the source region, the channel region, and the drain region of the thin film transistors Q1 and Q2 are used. This is different from the conventional static memory cell shown in FIGS. 6 and 7 in that the layers TB1 and TB2 are the third wiring layer and the ground potential layer GND is the fourth wiring layer. That is, the channel regions of the thin film transistors Q1 and Q2 serve as the gate electrodes of the polycrystalline silicon layers TG1 and T2.
It is narrowed by G2 and the ground potential layer GND.

In this way, the thin film transistors Q1 and Q2 are
When the ground potential layer GND is arranged with respect to the channel region of, since the ground potential layer GND is at the ground potential level, the influence of the electric field on the channel regions of the thin film transistors Q1 and Q2 can be reduced. Furthermore, the ground potential layer GND
Is between the aluminum wiring BL and the polycrystalline silicon layer TB1 as the channel region, and the polycrystalline silicon layer TB
Since the gate electrode TG1 is opposed to the gate electrode TG1 with the bit line 1 interposed therebetween, the bit line BL of V _CC level at the time of writing and standby (data holding) described in FIGS.
* BL can directly block the electric field effect on the channel region of the thin film transistor. Therefore, the influence of other electric fields on the channel region of the thin film transistor is reduced, and V _CC −V _TN −
Since α increases by about 0.3 V, the time required for the memory cell to stabilize during writing can be reduced. Further, since the current IONV _CC2 at the time of holding data can be increased about 10 times, the memory cell becomes stable. The circuit operation in this case is the same as that of the above-mentioned conventional example, and therefore the description thereof is omitted.

FIG. 3 is a plan view showing a second embodiment of the static semiconductor memory device according to the present invention, and FIG. 4 is a C of FIG.
FIG. 4 is a sectional view taken along line C of FIG. In FIGS. 3 and 4, the polycrystalline silicon layers TB1 and TB2 as the source region, channel region and drain region of the thin film transistors Q1 and Q2 are used as the third wiring layer, and the polycrystalline silicon layers as the gate electrodes of the thin film transistors Q1 and Q2 are used. The layers TG1 and TG2 are connected to the fourth
The difference from the conventional static type memory cell shown in FIGS. 6 and 7 is that the wiring layer is formed. That is, also in this case, the channel regions of the thin film transistors Q1 and Q2 serve as the gate electrodes of the polycrystalline silicon layers TG1 and TG2 and the ground potential layer G.
Narrowed by ND.

In this way, also in the second embodiment, as in the first embodiment, the time until the memory cell becomes stable at the time of writing can be reduced, and the current at the time of holding data is increased by 10 times. Since it can be increased to some extent, the memory cell becomes stable.

[0017]

According to the present invention as described above, according to the present invention, main
Reference potential that prevents the influence of electric fields from conductive layers other than molycell
The layer and the reference potential layer of the driving transistor are the same layer.
Since the electric field inside and outside the memory cell that affects the memory cell such as the bit line of the memory cell is reduced without increasing the manufacturing cost, the memory cell can be made more stable, and conversely The data can be easily inverted and the minimum drivable power supply voltage value and the data holding voltage value can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of a static semiconductor memory device according to the present invention.

FIG. 2 is a sectional view taken along line BB of FIG.

FIG. 3 is a plan view showing a second embodiment of the static semiconductor memory device according to the present invention.

FIG. 4 is a sectional view taken along line CC of FIG. 3;

FIG. 5 is a circuit diagram showing a conventional static memory cell.

FIG. 6 is a plan view of the static memory cell of FIG.

FIG. 7 is a sectional view taken along line AA of FIG. 6;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Field oxide film 3 ... Gate oxide film 4-7 ... Insulating layers P1, P2 ... N ^{+ type} impurity regions S1, S2, S3 ... MOS gate electrode GND ... Ground potential layers TG1, TG2 ... TFT Gate electrodes TB1, TB2 ... Source, channel and drain regions of TFT BL ... Bit lines C1 to C11 ... Contact

Claims (2)

(57) [Claims] 1. A load transistor and a drive transistor.
Static type semiconductor having memory cells consisting of
In the memory device, from a conductive layer other than the memory cell
Reference potential layer for preventing influence of electric field and the driving transistor
It is characterized in that it is composed of the same layer as the reference potential layer of
Static semiconductor memory device. 2. The load potential transistor is connected to the reference potential layer.
Of the load transistor across the channel region of the star
A contract characterized by being provided on the opposite side of the gate
The static semiconductor memory device according to claim 1.