JPH04299568A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To manufacture a TFT load type SRAM of constitution wherein a TFT load is not affected by noise from other conducting parts in a memory cell, by using few mask processes. CONSTITUTION:Under a semiconductor layer in which a source region 17, a drain region 18 and a channel region 19 of a TFT load are formed, a gate electrode whose electric potential is set at a value between logic levels is formed via a gate insulating film 16. On at least the channel region 19 of the above semiconductor layer, a shield electrode 30 whose electric potential is fixed at a constant value is formed via an insulating film 29.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to TFT (thin
film transistor) load type SRAM (
static random access m
This invention relates to improvements in a semiconductor memory device called ``emory'' and its manufacturing method.

[0002] Until recently, SRAMs of the type that use high resistance as a load have been widely used. However,
As the degree of integration improves and the number of memory cells increases, current consumption increases and various problems occur, so it is necessary to avoid this and with advances in semiconductor technology, TF
An SRAM with a load of T has been realized. However, another new problem arises due to the use of the TFT as a load, and it is necessary to solve this problem.

0003

[Prior Art] Figures 17 to 26 show high resistance load type SRAs.
27 to 32 are cross-sectional side views of main parts at key points in the process to explain a conventional example of a method for manufacturing M, and FIGS. Each shows a plan view of the main parts at key points in the process.
The explanation will be given below with reference to these figures. Incidentally, the cutaway side views of the main parts in FIGS. 17 to 26 are taken along the line YY shown in FIG. 32, which is a plan view of the main parts.

Refer to FIG. 17 17-(1) For example, a silicon dioxide (SiO2) film is used as a pad film, and silicon nitride (Si3 N4) is laminated thereon.
Selective thermal oxidation (e.g. lo
cal oxidation of silic
By applying the on:LOCOS method, a layer of SiO2 with a thickness of, for example, 400 mm is formed on the silicon semiconductor substrate 1.
A field insulating film 2 having a thickness of 0 [Å] is formed. 17-(2) Si3 N4 film and Si used for selective thermal oxidation
The O2 film is removed to expose the active region in the silicon semiconductor substrate 1.

Refer to FIG. 18 18-(1) A gate insulating film 3 made of SiO2 and having a thickness of, for example, 100 [Å] is formed by applying a thermal oxidation method. 18-(2) By applying a resist process in photolithography technology and a wet etching method using hydrofluoric acid as an etchant, the gate insulating film 3 is selectively etched to form a contact hole 3A. do.

Refer to FIGS. 19 and 27 19-(1) Chemical vapor deposition
By applying the CVD method, a first polycrystalline silicon film having a thickness of, for example, 1500 Å is formed. 19-(2) By applying the vapor phase diffusion method, for example, 1×1021
[cm-3] of phosphorus (P) is introduced to form an n + -impurity region 5'. In addition, in FIG. 27, for the sake of simplicity,
The first polycrystalline silicon film is omitted.

Refer to FIG. 20 20-(1) Resist process in photolithography technology and reactive ion etching using CCl4/O2 as etching gas.
By applying the etching: RIE) method,
Gate electrode 4 is formed by patterning the first polycrystalline silicon film. Note that this gate electrode 4 is a word line,
This is the gate electrode of the driver transistor. 20-(2) By applying the ion implantation method, the dose can be reduced to 3×1.
015 [cm-2] and acceleration energy of 40 [keV], As ions are implanted to form a source region 5 and a drain region 6.

Refer to FIGS. 21 and 28 21-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 7 made of SiO2 with a thickness of 1.5 Å is formed. 21-(2) Resist process in photolithography technology and RI using CHF3/He as etching gas
A ground line contact hole 7A is formed by applying the E method. Note that although the ground line contact hole 7A is visible in FIG. 28, it cannot be represented in FIG.

Refer to FIG. 22 22-(1) By applying the CVD method, a thickness of, for example, 1500 [
A second polycrystalline silicon film is formed. 22-(2) By applying the thermal diffusion method, for example, 1×1021 [
cm-3] of P is introduced. 22-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the second polycrystalline silicon film is patterned to form the ground line 8.

Refer to FIGS. 23 and 29 23-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 9 made of SiO2 with a thickness of 1.5 Å is formed. 23-(2) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying a method, the insulating film 9 is selectively etched to form a load resistance contact hole 9A.

Refer to FIG. 24 24-(1) By applying the CVD method, a thickness of, for example, 1500 [
A third polycrystalline silicon film is formed. 24-(2) By applying the resist process and ion implantation method in photolithography technology, the dose can be reduced to 1
×1015 [cm-2], and the acceleration energy is 30 [cm-2].
keV], As ions are implanted into a portion that is to become a supply line for the positive power supply voltage VCC and a portion where a high resistance load contacts the gate electrode 4. 24-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the third polycrystalline silicon film is patterned to form a contact portion 10, a high resistance load 11, and a VCC power supply level supply line 12.

Refer to FIGS. 25 and 30 25-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film made of SiO2 with a thickness of, for example, 500 Å]
0 [Å] phospho-silicic acid glass
ate glass (PSG)) is formed. In the figure, the two layers of insulating films are shown as one, and this is referred to as an insulating film 13. 25-(2) Heat treatment is performed to reflow and planarize the insulating film 13. 25-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying a method, the insulating film 13 and the like are selectively etched to form a bit line contact hole 13A.

Refer to FIGS. 26 and 31 26-(1) By applying the sputtering method, the thickness can be reduced to, for example, 1.
An Al film of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 14. Note that symbols shown in FIGS. 17 to 31 that are not explained, such as BL, will become clear when compared with FIG. 33, which will be described later.

FIG. 32 is a plan view of the main parts of a high resistance load type SRAM completed through the steps described above, and the same symbols as those used in FIGS. 17 to 31 represent the same parts or are the same. It shall have meaning. However, for the sake of clarity, the bit lines made of Al seen in FIGS. 26 and 31 are removed from FIG. 32.

FIG. 33 shows an equivalent circuit diagram of the main part of the high resistance load type SRAM described with reference to FIGS. 17 to 32. In the figure, Q1 and Q2 are drive transistors, Q
3 and Q4 are transfer gate transistors, R
1 and R2 are high resistance loads, WL is a word line, BL and /
BL represents a bit line, S1 and S2 represent nodes, VCC represents a positive power supply voltage, and VSS represents a negative power supply voltage.

Operation of this high resistance load type SRAM,
In particular, memory retention is performed as follows. Now, the positive side power supply voltage VCC = 5 [V], the negative side power supply voltage VS
S = 0 [V], and node S1 = 5 [V].
], node S2=0 [V], transistor Q2 is on and transistor Q1 is off. At the node S1, the potential is maintained at 5 [V] if the transistor Q1 is in the off state and the resistance value in that case is sufficiently high compared to the high resistance load R1. At node S2, the potential is maintained at 0 [V] if transistor Q2 is in the on state and the resistance value in that case is sufficiently lower than that of high resistance load R2.

However, under the above conditions, the negative power supply voltage VCC is supplied from the positive power supply voltage VCC supply line through the node S2.
DC current flows on the SS supply line side, and its value is high resistance load R
It is inversely proportional to the value of 2.

As the degree of integration of such a high resistance load type SRAM increases, the number of memory cells per chip increases, so unless the current consumption per memory cell is reduced, the current consumption of the entire chip will increase. I end up. Therefore, it is necessary to reduce the above-mentioned DC current, which requires increasing the values of the high resistance loads R2 and R1. However, when this resistance value is increased, it becomes difficult to stably maintain the potential at the node on the side where the driving transistor is turned off, which is the node S1 in the above example.

Due to the background described above, a TFT load type SRAM that uses a TFT instead of a high resistance as a load has appeared.

The TFT load type SRAM will now be explained. Similar to the explanation of the high resistance load type SRAM, first, the manufacturing of the TFT load type SRAM will be explained.

FIGS. 34 to 37 show TFT-loaded SRAMs.
38 to 41 are cross-sectional side views of main parts at key points in the process to explain a conventional example of a method for manufacturing TFT.
In order to explain a conventional example of a method for manufacturing a load-type SRAM, principal part plan views at key points in the process are shown, and the following description will be made with reference to these figures. 34 to 37 are cross-sectional side views of main parts taken along the line Y-Y shown in FIG. From 17-(1) to 23-(2), which are the steps for manufacturing, that is,
The process up to forming the load resistance contact hole 9A is almost the same in the process of manufacturing this TFT load type SRAM, except that the ground line 8 made of the second polycrystalline silicon film is The opening 8A (see FIG. 38) is necessary for the gate electrode in the TFT load made of the third polycrystalline silicon film to contact with the active region and the gate electrode 4 made of the first polycrystalline silicon film. ) and the formation of a hole 9B with which the gate electrode in the TFT load is in contact with the active region, gate electrode 4, etc., so the subsequent steps will be explained. do. Of course, FIGS. 17 to 33
The same symbols used in the above shall represent the same parts or have the same meaning.

Refer to FIGS. 34 and 38 34-(1) By applying the CVD method, a thickness of, for example, 1500 [
A third polycrystalline silicon film is formed. 34-(2) By applying the ion implantation method, the dose can be reduced to 1×1.
015 [cm-2], and the acceleration energy is 20 [k].
eV], and P ions are implanted. 34-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the third polycrystalline silicon film is patterned to form the gate electrode 15 of the TFT load.

Refer to FIG. 35 35-(1) By applying the CVD method, a TFT load gate insulating film 16 made of SiO2 and having a thickness of, for example, 300 [Å] is formed. 35-(2) By applying a resist process in photolithography technology and a wet etching method using hydrofluoric acid as an etchant, the gate insulating film 16 is selectively etched to form a drain contact hole. 16
Form A.

Refer to FIGS. 36 and 39. 36-(1) By applying the CVD method, the thickness can be reduced to, for example, 500 Å.
] A fourth polycrystalline silicon film is formed. 36-(2) By applying the resist process and ion implantation method in photolithography technology, the dose can be reduced to 1.
×1014 [cm-2], and the acceleration energy is 5 [k
eV], B ions are implanted into the portions that are to become the source and drain regions of the TFT load and the portions that are to be the Vcc power supply level supply line. 36-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the fourth polycrystalline silicon film is patterned to form the source region 17, drain region 18, channel region 19, and VCC power supply level supply line 20 of the TFT load.

Refer to FIGS. 37 and 40 37-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film made of SiO2 with a thickness of, for example, 50 Å]
An insulating film made of PSG with a thickness of 0.00 Å is formed. Note that in this figure as well, like FIG. 26, two layers of insulating films are shown as one, and this is referred to as an insulating film 21. 37-(2) Heat treatment is performed to reflow and planarize the insulating film 21. 37-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying the method, the insulating film 21 and the like are selectively etched to form a bit line contact hole. 37-(4) By applying the sputtering method, the thickness can be reduced by e.g.
An Al film of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 22. Note that symbols shown in FIGS. 34 to 40 that are not explained, such as BL, will become clear when compared with FIG. 42, which will be described later.

FIG. 41 is a plan view of the main parts of the TFT-loaded SRAM completed through the steps described above, and the same symbols as those used in FIGS. 34 to 40 represent the same parts or have the same meanings. shall have. However, for the sake of clarity, the bit lines made of Al seen in FIGS. 37 and 40 are removed from FIG. 41.

FIG. 42 shows an equivalent circuit diagram of the main part of the TFT load type SRAM described with reference to FIGS. 34 to 41. Note that the same symbols as those used in FIGS. 34 to 41 and FIG. 33 represent the same parts or have the same meaning. In the figure, Q5 and Q6 respectively indicate transistors that are load TFTs.

Operation in this TFT load type SRAM,
In particular, memory retention is performed as follows.

Now, suppose that the positive power supply voltage VCC = 5 [V] and the negative power supply voltage VSS = 0 [V], and node S1 = 5 [V] and node S2 = 0 [V]. , transistor Q2 is on and transistor Q6 is on.
is off, transistor Q1 is off, and transistor Q5 is on. Node S
1, transistor Q1 is in an off state,
Further, if the resistance value in that case is sufficiently higher than that in the on state of the transistor Q5, the potential is maintained at 5 [V]. At node S2, transistor Q2 is in an on state, and the resistance value in that case is equal to transistor Q.
If it is sufficiently low compared to the off state of 6, the potential will be 0 [V
] will be maintained.

As described above, under the above conditions, the resistance value of the transistor Q5 or transistor Q6, which is the load, changes depending on the stored information, so that the high resistance load type SRA
The problem with M is resolved and stable information storage can be performed. Note that the transistors Q5 and Q6 used here
The channel of the load TFT, that is, the channel of the load TFT, is made of polycrystalline silicon, and the crystalline state is much worse than that of single crystal, so current leaks even in the off state. Since the leakage current directly becomes the consumption current of the chip, it is desirable to make it as small as possible.

By the way, as is clear from FIG. 37, in this TFT-loaded SRAM, Al is used in the top layer.
A bit line 22 made of a film is provided, and a load T is provided directly below the bit line 22 via an insulating film 21 made of PSG or the like.
FT channel exists.

Such a configuration can be regarded as a transistor in which the bit line 22 made of an Al film serves as a gate electrode, and the insulating film 21 therebelow serves as a gate insulating film, and the bit line 22, which is the gate electrode, serves as a gate electrode. The potential of the line 22 is 0 [V] (
VSS) to 5 [V] (VCC), and therefore,
The TFT, that is, the transistor Q6, which should be in an off state, becomes close to an on state, resulting in an increase in leakage current and a significant parasitic effect. Therefore, in an attempt to solve these problems, a double-gate structure TFT-loaded SRAM, which is an improved version of the TFT-loaded SRAM, was developed.

This double gate structure TFT loaded SRAM
Now, the third polycrystalline silicon film in the TFT load type SRAM explained with reference to FIGS. The fifth polycrystalline silicon film is connected between the source region 17, drain region 18, and channel region 19, and between the fourth polycrystalline silicon film that constitutes the VCC power supply level supply line 20, etc., and the bit line 22 made of Al. The above problem is solved by intervening.

FIGS. 43 to 45 show double gate structure TFTs.
In order to explain a conventional example of a method for manufacturing a load-type SRAM, cutaway side views of essential parts at key points in the process are shown, and the following description will be made with reference to these figures. It should be noted that the steps 34-(1) to 36-(3) for manufacturing the TFT load type SRAM described above, namely, the source region 17, drain region 18, channel region 19 of the TFT load, and VCC The process up to forming the power supply level supply line 20 is performed in this double gate structure TFT load type SRAM.
Since the manufacturing process is almost the same, we will explain the subsequent steps first. Of course, the same symbols as those used in FIGS. 17 to 42 represent the same parts or have the same meanings.

Refer to FIG. 43 43-(1) By applying the CVD method, an insulating film 23 made of SiO2 and having a thickness of, for example, 500 [Å] is formed. 43-(2) Resist process in photolithography technology and RIE using CHF3 +He as etching gas
By applying a method, the insulating film 23 is selectively etched to form a contact hole 23A to the fourth polycrystalline silicon film.

Refer to FIG. 44 44-(1) By applying the CVD method, a thickness of, for example, 1000 [
A fifth polycrystalline silicon film is formed. 44-(2) For example, 1×10 21 [cm −3 ] of P is diffused into the fifth polycrystalline silicon film by applying a thermal diffusion method. 44-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the fifth polycrystalline silicon film is patterned to form the second gate electrode 24 of the TFT load.
form.

Refer to FIG. 45 45-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film made of SiO2 with a thickness of, for example, 50 Å]
An insulating film made of PSG with a thickness of 0.00 Å is formed. It should be noted that in this figure, as in FIG. 37 or 26, two layers of insulating films are shown as one, and this is referred to as an insulating film 25. 45-(2) Heat treatment is performed to reflow and planarize the insulating film 25. 45-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying the method, the insulating film 25 and the like are selectively etched to form a bit line contact hole. 45-(4) By applying the sputtering method, the thickness can be reduced to 1
An Al film with a thickness of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 26.

[0038]

[Problem to be solved by the invention] As explained above,
SRAM started with high resistance load type, then TFT load type,
This has progressed to a double gate structure TFT loaded type. However, first, FIGS. 17 to 26 (particularly FIG. 26) and FIG.
45 (particularly FIG. 45), it should become clear that the double gate structure TF from high resistance load type SRAM
When transitioning to a T-load type SRAM, the number of polycrystalline silicon films increases by two layers, and the number of mask steps increases by four times.

By the way, in a TFT load type SRAM, for example, the voltage of a bit line or the like turns the TFT load, which should be off, into a state close to on, causing parasitic effects such as an increase in leakage current. As mentioned above, a double-gate structure TFT-loaded type was developed to prevent this, and it is already known that if such a countermeasure is taken, manufacturing problems such as an increase in the number of mask processes will occur. explained.

The present invention provides a T that can operate stably without being affected by noise from other conductive parts within the memory cell.
An attempt is made to obtain an FT load type SRAM and to reduce the number of manufacturing steps.

[0041]

Means for Solving the Problems A semiconductor memory device according to the present invention includes (1) a pair of driver transistors formed on a semiconductor substrate (for example, a silicon semiconductor substrate 1) and a semiconductor layer on the semiconductor substrate; (for example, a fourth polycrystalline silicon film that is a third conductive film), the TFT load is insulated under the semiconductor layer. A gate electrode (for example, gate electrode 15) whose potential takes a value between logic levels is formed via a film (for example, gate insulating film 16), and an insulating film (for example, insulating film 29) is formed on the semiconductor layer. (2) In (1) above, the TFT load is formed by forming a shield electrode (for example, the shield electrode 30) whose potential is fixed to a constant value through the semiconductor layer. A gate electrode whose potential takes a value between logic levels is formed on top of the insulating film through an insulating film.
Further, a shield electrode whose potential is fixed to a constant value is formed under the semiconductor layer via an insulating film, or (3) in the above (1),
(4) A field insulating film (e.g., silicon semiconductor substrate 1) is formed on the surface of the semiconductor substrate (e.g., silicon semiconductor substrate 1). A step of forming a field insulating film 2) and then a gate insulating film (e.g. gate insulating film 3) is followed by growing a first conductive film and patterning it to form a gate electrode of a driver transistor (e.g. gate insulating film 3). Next, impurities are introduced using the field insulating film and the gate electrode of the driver transistor, which is the first conductive film, as a mask to form impurity regions (for example, the source regions 5 and 55). After forming a first insulating film (e.g., insulating films 7, 9, etc.)
Next, a second conductive film in contact with the gate electrode or drain of the driver transistor is grown and patterned to form a gate electrode (for example, gate electrode 15) of the TFT load, and then a second conductive film is formed. gate insulating film (for example, gate insulating film 16
), and then a semiconductor layer (for example, a fourth polycrystalline silicon film) which is a third conductive film in contact with the gate electrode of the TFT load is grown, selectively doped with impurities, and patterned. A step of forming a source region (e.g., source region 17), a drain region (e.g., drain region 18), and a channel region (e.g., channel region 19) of the TFT load, and then an insulating layer covering the semiconductor layer, which is the third conductive film. A step of forming a film (for example, an insulating film 29) and a fourth conductive film (for example, a fifth polycrystalline silicon film), and then patterning the fourth conductive film to form a shield electrode (for example, a shield electrode) of a TFT load. 3
0), or (5) in the above (4), a third conductive layer forming a source region, a driver region, and a channel region of the TFT load. The method is characterized in that it includes a step of patterning a semiconductor layer, which is a film, and a fourth conductive film, which becomes a shield electrode of a TFT load, using the same mask.

[0042]

[Operation] As is clear from the above, in the present invention, since the TFT load is covered with a shield electrode, the potential at other conductive parts within the memory cell influences the TFT load.
There is no risk of unstable operation such as an increase in leakage current due to the FT load becoming close to on, and furthermore, this type of TFT load type SRAM can be manufactured easily and easily with a high yield with a small number of mask steps. can be manufactured.

[0043]

[Embodiment] FIGS. 1 and 2 are cross-sectional side views of essential parts of a TFT-loaded SRAM at key process points for explaining a first embodiment of the present invention, and FIG. TFT-loaded SR at key points in the process to explain the first embodiment
Each shows a plan view of a main part of the AM, and will be described in detail below with reference to these figures. 3 is different from the conventional example shown in FIG. 41 only in that a shield electrode 30 is added, and the cutaway side views of main parts in FIGS. 1 and 2 show the TFT load in the present invention. The cut plane is similar to the cut plane along the line Y-Y shown in FIG. 3, which is a plan view of the main part of the SRAM type SRAM, and FIGS. 34 to 37 and FIGS. Step 36-(
3), that is, T using the fourth polycrystalline silicon film.
The steps up to the formation of the source region 17, drain region 18, channel region 19 of the FT load, VCC power supply level supply line 20, etc. are the same in this embodiment, so the explanation will be omitted and will be explained from the next step.

Refer to FIGS. 1 and 3 1-(1) Here, the TFT load type SRAM includes a transfer transistor consisting of a field insulating film 2, a gate insulating film 3, and a first polycrystalline silicon film on a silicon semiconductor substrate 1. Gate electrode or gate electrode of driver transistor 4, n+ −
Impurity region 5', n+-source region 5, n+-drain region 6, insulating film 7 made of SiO2, ground line 8 made of second polycrystalline silicon film, insulating film 9 made of SiO2, third polycrystalline silicon. A TFT load gate electrode 15 made of a film, a TFT load gate insulating film 16 made of SiO2, and a TFT made of a fourth polycrystalline silicon film.
It is assumed that a source region 17, a drain region 18, a channel region 19 and a VCC power supply level supply line (not shown) of the load are formed. 1-(2) By applying the CVD method, the thickness can be reduced to, for example, 500 [Å].
An insulating film 29 made of SiO2 is formed over the entire surface. 1-(3) By applying the CVD method, the thickness can be reduced to, for example, 1000 [
A fifth polycrystalline silicon film of Å] is formed on the entire surface. 1-(4) By applying a thermal diffusion method, for example, 1×10 21 [cm −3 ] of P is diffused into the fifth polycrystalline silicon film. 1-(5) Resist process in photolithography technology and R using CCl4/O2 as etching gas
By applying the IE method, the fifth polycrystalline silicon film is patterned to form the shield electrode 30.

Refer to FIGS. 2 and 3 2-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film made of SiO2 with a thickness of, for example, 50 Å]
An insulating film made of PSG with a thickness of 0.00 Å is formed. Note that in this figure, as in FIG. 37, two layers of insulating films are shown as one, and this is referred to as an insulating film 31. 2-(2) Heat treatment is performed to reflow and planarize the insulating film 31. 2-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying the method, the insulating film 31 and the like are selectively etched to form a bit line contact hole. 2-(4) By applying the sputtering method, the thickness can be reduced, e.g.
An Al film of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 32.

In the first embodiment described above, the TFT load is configured to be shielded by the shield electrode 30, so there is no possibility of undesired operation due to voltage from other conductive parts such as the bit line 32. do not have. In addition, compared to the case of double gate structure TFT load, the mask process is reduced by one time,
The manufacturing process is simplified.

FIGS. 4 to 6 show a TFT-loaded SRAM at key points in the process for explaining the second embodiment of the present invention.
The main parts are shown in cross-sectional side views, and will be described in detail below with reference to these figures. Incidentally, the cutaway side views of the main parts in FIGS. 4 to 6 are the same cut planes as the cut plane along the line Y-Y shown in FIG. (However, only the shield electrode pattern is different from FIG. 3), and the TFT-loaded SRA described in FIGS. 34 to 37 and 38 to 41.
From the beginning to step 35-(2) in the conventional method for manufacturing M, that is, selectively etching the gate insulating film 16 to form the drain contact hole 16A.
Since the steps up to the formation of the steps are the same in this embodiment, the explanation will be omitted and will be explained from the next step.

Refer to FIG. 4 4-(1) Here, the TFT load type SRAM includes a silicon semiconductor substrate 1, a field insulating film 2, a gate insulating film 3, and a gate electrode of a driver transistor consisting of a first polycrystalline silicon film. 4, n+ - impurity region 5', n+ - source region 5, n+ - drain region 6, insulating film 7 made of SiO2, ground line 8 made of second polycrystalline silicon film, Si
An insulating film 9 made of O2, a TFT load gate electrode 15 made of a third polycrystalline silicon film, a TFT load gate insulating film 16 made of SiO2, and a drain contact hole 16A (see FIG. 37) are formed. state. 4-(2) By applying the CVD method, the thickness can be reduced to, for example, 200 [Å].
] A fourth polycrystalline silicon film is formed. 4-(3) By applying the resist process and ion implantation method in photolithography technology, the dose can be reduced to 1
×1014 [cm-2], and the acceleration energy is 5 [k
eV], B ions are implanted into the portions that are to become the source and drain regions of the TFT load and the portions that are to be the Vcc power supply level supply line. See Figure 5 5-(1) By applying the CVD method, the thickness can be reduced to, for example, 500 [Å].
An insulating film 29 made of SiO2 is formed over the entire surface. 5-(2) By applying the CVD method, the thickness can be reduced to, for example, 1000 [
A fifth polycrystalline silicon film of Å] is formed on the entire surface. 5-(3) By applying a thermal diffusion method, for example, 1×10 21 [cm −3 ] of P is diffused into the fifth polycrystalline silicon film. 5-(4) Use CCl4 /O2 (for polycrystalline silicon) and CHF3 /He (for SiO2) as resist process and etching gas in photolithography technology.
By applying the RIE method, the fifth polycrystalline silicon film, the insulating film 29, and the fourth polycrystalline silicon film are patterned, and the shield electrode 30, TFT
A source region 17, a drain region 18, a channel region 19, a VCC power supply level supply line (not shown), etc. of the load are formed.

Refer to FIG. 6 6-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film made of SiO2 with a thickness of, for example, 50 Å]
An insulating film made of PSG with a thickness of 0.00 Å is formed. Note that in this figure, as in FIG. 37, two layers of insulating films are shown as one, and this is referred to as an insulating film 31. 6-(2) Heat treatment is performed to reflow and planarize the insulating film 31. 6-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying the method, the insulating film 31 and the like are selectively etched to form a bit line contact hole. 6-(4) By applying the sputtering method, the thickness can be reduced, e.g.
An Al film of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 32.

In the second embodiment described above, the shield electrode 30 for shielding the TFT load, the source region 17, drain region 18, channel region, etc. of the TFT load can be realized in one mask process.
Even if the parasitic effect of the TFT load is introduced, it is possible to prevent the parasitic effect of the TFT load without increasing the number of processes compared to the conventional example (see, for example, FIG. 41). The mask step is reduced by two times compared to the case of some dual gate structure TFT loads (see, eg, FIG. 45).

FIG. 7 shows a plan view of a main part of a TFT load type SRAM having a split word line developed and realized by the present inventors. In the figure, 41 indicates the gate of the TFT, 42 the channel of the TFT, 43 the word line, and VCC the positive power supply level.

In this SRAM, the driver transistor, TFT, etc. have good symmetry, and therefore,
It has the advantage of easy layout, and next, this T
An embodiment in which the present invention is applied to an FT load type SRAM will be described.

FIGS. 8 to 16 are cross-sectional side views of the main parts of a TFT-loaded SRAM at key points in the process for explaining the third embodiment of the present invention, and these figures will be referred to below. This will be explained in detail. Note that FIGS. 8 to 16 are cross-sections taken along line XX shown in FIG. 7.

Refer to FIG. 8 8-(1) SiO2 covering the active region of the silicon semiconductor substrate 51
A pad film consisting of Si
By applying a selective thermal oxidation method using an oxidation-resistant mask film made of 3N4, a field insulating film 52 made of SiO2 and having a thickness of, for example, 4000 [Å] is formed. 8-(2) After removing the oxidation-resistant mask film and pad film to expose the active region, by applying a thermal oxidation method, SiO2
A gate insulating film 53 having a thickness of, for example, 100 [Å] consisting of
form. 8-(3) By applying a resist process in photolithography technology and a wet etching method using hydrofluoric acid as an etchant, the gate insulating film 53 was selectively etched and also used for impurity diffusion. contact·
Form a hole. 8-(4) By applying the CVD method, the thickness can be reduced to, for example, 1000 [
A first polycrystalline silicon film is formed. 8-(5) By applying the vapor phase diffusion method, P is introduced with an impurity concentration of, for example, 1 × 1020 [cm-3], and n+
- forming impurity regions 54; 8-(6) Resist process in photolithography technology and RI using CCl4 + O2 as etching gas
By applying the E method, the first polycrystalline silicon film is patterned to form gate electrodes 55 and 56. 8-(7) By applying the ion implantation method, As ions are implanted at a dose of, for example, 1 x 1015 [cm-2] and an acceleration energy of 30 [keV].
A + -source region 57 and an n+ -drain region 58 are formed.

Refer to FIG. 9 9-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 59 made of SiO2 with a thickness of 1.5 Å is formed. 9-(2) By applying the CVD method, a thickness of, for example, 1000 [
A second polycrystalline silicon film is formed. 9-(3) By applying a vapor phase diffusion method, P is introduced into the second polycrystalline silicon film at an impurity concentration of, for example, 1×10 20 [cm −3 ]. 9-(4) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the second polycrystalline silicon film is patterned to form the gate electrode 61 of the TFT load and the like.

Refer to FIG. 10 10-(1) By applying the CVD method, the thickness can be reduced to, for example, 200 [Å].
] A TFT gate insulating film 62 made of SiO2 is formed. 10-(2) CHF3/He(SiO2) resist process and etching gas in photolithography technology
By applying the RIE method using CCl4/O2 (for polycrystalline silicon) and CCl4/O2 (for polycrystalline silicon), the gate electrode 61 of the TFT load consisting of the insulating film 62, the second polycrystalline silicon film,
The insulating film 59 is selectively etched to form an interconnect contact hole 62A extending from the surface to the gate electrode 56 or 55 of the driving transistor, which is the first polycrystalline silicon film.

Refer to FIG. 11 11-(1) By applying the CVD method, the thickness can be reduced to, for example, 500 [Å].
] A third polycrystalline silicon film is formed. 11-(2) By applying the resist process in photolithography technology and the ion implantation method, the source region and drain region of the TFT load and the VCC power supply level supply line in the third polycrystalline silicon film are formed. B is implanted at a dose of 1×10 14 [cm −2 ] and an acceleration energy of 5 [keV] into the area where the B is to be formed.

Refer to FIG. 12 12-(1) By applying the CVD method, the thickness can be reduced to, for example, 500 [Å].
An insulating film 65 made of SiO2 is formed. 12-(2) By applying the CVD method, a thickness of, for example, 1000 [
A fourth polycrystalline silicon film is formed. 12-(3) For example, 1×10 20 [cm −3 ] of P is diffused into the fourth polycrystalline silicon film by applying a thermal diffusion method.

Refer to FIG. 13 13-(1) Apply RIE method using CCl4 /O2 (for polycrystalline silicon) and CHF3 /He (for SiO2) as resist process and etching gas in photolithography technology. Depending on the situation, the fourth polycrystalline silicon film, the insulating film 65, and the third polycrystalline silicon film are patterned to form the shield electrode 66 of the TFT load, the contact portion, the drain region, source region, and channel of each TFT load. A region, a VCC power supply level supply line, etc. are formed. In addition, in the figure, all of the above-mentioned parts, especially the TFT load composed of the third polycrystalline silicon film, cannot be represented because they extend in the direction perpendicular to the plane of the paper. TF
Contact portion 63 connected to the tip of the drain region of the T load
Only the channel region 64 of the TFT load adjacent to the TFT load is shown. Furthermore, the purpose of shielding the TFT load can be sufficiently achieved if the channel region is mainly covered with the shield electrode 66.

Refer to FIG. 14 14-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 67 made of SiO2 with a thickness of 1.5 Å is formed. 14-(2) RI using CHF3/He as the resist process and etching gas in photolithography technology
By applying the E method, the insulating film 67, etc. is selectively etched to form the VSS power supply level supply line contact and
A hole 67A is formed.

Refer to FIG. 15 15-(1) By applying the CVD method, a thickness of, for example, 1000 [
A fifth polycrystalline silicon film is formed. 15-(2) For example, 1×10 21 [cm −3 ] of P is diffused into the fifth polycrystalline silicon film by applying a thermal diffusion method. 15-(3) Resist process in photolithography technology and R using CCl4 /O2 as etching gas
By applying the IE method, the fifth polycrystalline silicon film is patterned to form the VSS power level supply line 68.

Refer to FIG. 16 16-(1) By applying the CVD method, a thickness of, for example, 5000 [
An insulating film 69 made of PSG with a thickness of 1.5 Å is formed. 16-(2) Heat treatment is performed to reflow and planarize the insulating film 69. 16-(3) By applying the resist process in photolithography technology and the RIE method using etching gas such as CCl4 /O2, the insulating film 69 and the like are selectively etched to form bit line contacts. Form a hole. Note that FIG. 16 cannot represent bit line contact holes (see, for example, FIG. 7). 16-(4) By applying the sputtering method, the thickness can be reduced, e.g.
An Al film with a thickness of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 70.

In the third embodiment described above, the TFT load is of course shielded by the counter electrode 66, so it is not affected by noise, and the TFT load shown in FIG. The advantages of the load-type SRAM are inherited as they are, and furthermore, in this embodiment, the drain region of the TFT load, the lower gate electrode, and the gate electrode or drain region of the driver transistor can be formed in a single mask process. Since the connection can be made, one mask process is required compared to the second embodiment, and three mask processes are required compared to the conventional example of the double gate structure TFT load, and the manufacturing process is simplified. Simplified.

[0064]

Effects of the Invention The semiconductor memory device and the manufacturing method thereof according to the present invention include a pair of driver transistors formed on a semiconductor substrate and a pair of TFT loads formed on a semiconductor layer on the semiconductor substrate. The TFT load has a gate electrode formed under the semiconductor layer via an insulating film, the potential of which takes a value between logic levels; A shield electrode whose potential is fixed to a constant value is formed thereon via an insulating film.

As is clear from the above, in the present invention, since the TFT load is covered with a shield electrode, the TFT load is not turned on due to the influence of the potential in other conductive parts in the memory cell. There is no risk of unstable operation such as an increase in leakage current due to a similar situation.
Moreover, this type of TFT-loaded SRAM can be manufactured easily and simply with a high yield with a small number of mask steps.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional side view of a main part of a TFT-loaded SRAM at key points in the process for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional side view of a main part of a TFT-loaded SRAM at key points in the process for explaining the first embodiment of the present invention.

FIG. 3 is a plan view of a main part of a TFT-loaded SRAM at key points in the process for explaining the first embodiment of the present invention.

FIG. 4 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining a second embodiment of the present invention.

FIG. 5 is a cross-sectional side view of a main part of a TFT-loaded SRAM at key points in the process for explaining a second embodiment of the present invention.

FIG. 6 is a cross-sectional side view of a main part of a TFT-loaded SRAM at key points in the process for explaining a second embodiment of the present invention.

FIG. 7 is a plan view of a main part of a TFT load type SRAM with split word lines developed and realized by the present inventors.

FIG. 8 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 9 is a cutaway side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 10 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 11 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 12 is a cutaway side view of a main part of a TFT load type SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 13 is a cutaway side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 14 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 15 is a cutaway side view of a main part of a TFT load type SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 16 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining a third embodiment of the present invention.

FIG. 17 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 18 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 19 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 20 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 21 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 22 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 23 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 24 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 25 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 26 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 27 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 28 is a plan view of a main part at key points in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 29 is a plan view of main parts at key points in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 30 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 31 is a plan view of a main part at key points in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 32 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 33 is an equivalent circuit diagram of a main part of a high resistance load type SRAM.

FIG. 34 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 35 is a side view with a main part cut away at key points in the process for explaining a conventional method for manufacturing a TFT-loaded SRAM.

FIG. 36 is a side view of a main part cut away at key points in the process for explaining a conventional method for manufacturing a TFT-loaded SRAM.

FIG. 37 is a side view with a main part cut away at key points in the process for explaining a conventional method for manufacturing a TFT-loaded SRAM.

FIG. 38 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 39 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 40 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 41 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 42 is an equivalent circuit diagram of a main part of a TFT load type SRAM.

FIG. 43 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a double-gate structure TFT-loaded SRAM.

FIG. 44 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a double-gate structure TFT-loaded SRAM.

FIG. 45 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a double-gate structure TFT-loaded SRAM.

[Explanation of symbols]

1 Silicon semiconductor substrate 2 Field insulation film 3 Gate insulating film 4 Gate electrode 5 Source area 5' Impurity region 6 Drain region 7 Insulating film 8 Ground wire 15 Gate electrode 16 Gate insulation film 17 Source area 18 Drain region 19 Channel area 29 Insulating film 30 Shield electrode 31 Insulating film 32 Bit line

Claims (6)

[Claims] Claim 1: A pair of drivers formed on a semiconductor substrate.
The memory cell includes a transistor and a pair of TFT loads formed in a semiconductor layer on the semiconductor substrate. A semiconductor memory device characterized in that a gate electrode that takes a value between levels is formed, and a shield electrode whose potential is fixed to a constant value is formed on the semiconductor layer via an insulating film. . 2. The semiconductor memory device according to claim 1, wherein the semiconductor layer in which the channel region of the TFT load exists and the shield electrode have the same planar pattern. 3. The TFT load according to claim 1 or 2, wherein the drain region of the TFT load is connected to the lower gate electrode at its side surface and to the gate electrode or drain region of the driver transistor at its surface. Semiconductor storage device. 4. A step of forming a field insulating film on the surface of the semiconductor substrate and then forming a gate insulating film, and then growing a first conductive film and patterning it to form a gate electrode of the driver transistor. Next, using the field insulating film and the gate electrode of the driver transistor, which is the first conductive film, as a mask, impurities are introduced to form an impurity region, and then a first insulating film is formed. Then, a second conductive film is grown and patterned to form a gate electrode of a TFT load, and then a gate insulating film, which is a second insulating film, is formed, and then a third conductive film is formed. A step of growing a certain semiconductor layer, selectively introducing impurities and patterning to form a source region, a drain region, and a channel region of a TFT load, and then an insulating film covering the semiconductor layer, which is the third conductive film. A method for manufacturing a semiconductor memory device, comprising the steps of forming a fourth conductive film, and then patterning the fourth conductive film to form a shield electrode for a TFT load. . 5. The method further comprises the step of forming a drain region of the TFT load that is in contact with the lower gate electrode of the TFT load and its side surface and with the gate electrode or drain of the driver transistor and its surface. 5. The method of manufacturing a semiconductor memory device according to claim 4. 6. Patterning a semiconductor layer, which is a third conductive film for forming the source region, driver region, and channel region of the TFT load, and a fourth conductive film, which becomes the shield electrode of the TFT load, using the same mask. 5. The method of manufacturing a semiconductor memory device according to claim 4, further comprising the step of: