JP3044403B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a TFT (thin f
ilm transformer) load type SRAM (st
atic random access memory
The present invention relates to an improvement in a semiconductor memory device called y) and a method of manufacturing the same.

[0002] Until recently, SRAMs having a high resistance load have been widely used. However,
As the degree of integration increases and the number of memory cells increases, the current consumption increases and various problems occur.
An SRAM with a load of T has been realized. However, another new problem is caused by using the TFT as a load, and it is necessary to solve it.

[0003]

2. Description of the Related Art FIGS. 31 to 40 show a high resistance load type SRA.
FIGS. 41 to 46 are sectional views for explaining a conventional example of a method of manufacturing a high-resistance load type SRAM. FIG. 41 to FIG. 46 are views for explaining a conventional example of a method of manufacturing a high resistance load type SRAM. The main part plan view at the important points of the process is shown respectively,
Hereinafter, description will be made with reference to these figures. The cutaway side views of the main part in FIGS. 31 to 40 are taken along the line YY shown in FIG. 46 which is a plan view of the main part.

See FIG. 31 31- (1) For example, a silicon dioxide (SiO ₂ ) film is used as a pad film,
Selective thermal oxidation (eg, local) using a silicon nitride (Si ₃ N ₄ ) film laminated thereon as an oxidation resistant mask film
oxidation of silicon: LOC
By applying the (OS) method, the silicon semiconductor substrate 1
A field insulating film 2 made of SiO ₂ and having a thickness of, for example, 4000 [Å] is formed thereon. 31- (2) Si ₃ N ₄ film or SiO ₂ used for performing selective thermal oxidation
The active region in the silicon semiconductor substrate 1 is exposed by removing the film.

Referring to FIG. 32, 32- (1) A gate insulating film 3 made of SiO ₂ and having a thickness of, for example, 100 [Å] is formed by applying a thermal oxidation method. 32- (2) A contact hole 3A is formed by selectively etching the gate insulating film 3 by applying a resist process in photolithography technology and a wet etching method using an etchant as hydrofluoric acid. I do.

FIG. 33 and FIG. 41 33- (1) Chemical vapor deposition (chemical vapor deposition)
A first polycrystalline silicon film having a thickness of, for example, 1500 [Å] is formed by applying the position (CVD) method. 33- (2) By applying the gas phase diffusion method, for example, 1 × 10
²¹ [cm ^-3 ] of phosphorus (P) is introduced to form an n ⁺ -impurity region 5 '. In FIG. 41, the first polycrystalline silicon film is omitted for simplicity.

Referring to FIG. 34, 34- (1) Reactive ion etching (reactive ion etc) using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
In this case, the gate electrode 4 is formed by patterning the first polycrystalline silicon film by applying the Hing (RIE) method. The gate electrode 4 is a word line and a gate electrode of a driver transistor. 34- (2) Applying the ion implantation method to reduce the dose amount to 3 × 1
0 ¹⁵ [cm ^-2 ], acceleration energy 40 [keV], A
The source region 5 and the drain region 6 are formed by implanting s ions.

See FIGS. 35 and 42. 35- (1) A thickness of, for example, 1000 by applying the CVD method.
[Å] The insulating film 7 made of SiO ₂ is formed. 35- (2) RIE using CHF ₃ / He as an etching gas and resist process in photolithography technology
Ground line contact hole 7 by applying the
Form A. The ground line contact hole 7A is not visible in FIG.

Referring to FIG. 36, 36- (1) The thickness is, for example, 1500 by applying the CVD method.
[2] A second polycrystalline silicon film is formed. 36- (2) By applying a resist process in photolithography and an RIE method using CCl ₄ / O ₂ as an etching gas, the second polysilicon film is patterned to form a ground line. 8 is formed.

See FIGS. 37 and 43. 37- (1) A thickness of, for example, 1000 by applying the CVD method.
[Å] The insulating film 9 made of SiO ₂ is formed. 37- (2) The resist process in the photolithography technology and the application of the RIE method using CHF ₃ / He as an etching gas are performed to selectively etch the insulating film 9 and to provide a load resistance contact hole. 9A is formed.

Referring to FIG. 38, 38- (1) The thickness is, for example, 1500 by applying the CVD method.
[3] A third polycrystalline silicon film is formed. 38- (2) Applying a resist process and an ion implantation method in the photolithography technology to reduce the dose to 1
× 10 ¹⁵ [cm ^-2 ] and acceleration energy of 30 [ke]
V], As ions are implanted into a portion to be a supply line of the positive power supply voltage V _CC and a portion where the high resistance load contacts the gate electrode 4. 38- (3) A third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. 10. High resistance load 1
1. _Vcc power level supply line 12 is formed.

See FIGS. 39 and 44. 39- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] an insulating film made of SiO ₂ and a thickness of, for example, 500
0 [Å] phospho-silicate glass (phospho-silicic glass)
a) (insulating glass: PS glass). In the drawing, the two layers of the insulating film are integrally shown, and this is referred to as an insulating film 13. 39- (2) A heat treatment for reflowing the insulating film 13 to make it flat is performed. 39- (3) By selectively etching the insulating film 13 and the like by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, A hole 13A is formed.

See FIGS. 40 and 45. 40- (1) A thickness of, for example, 1 by applying the sputtering method.
An [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 14. It should be noted that those not described with reference to the symbols described in FIGS. 31 to 45, for example, BL and the like will become clear when compared with FIG. 47 described later.

FIG. 46 is a plan view of a main part of a high resistance load type SRAM completed through the above-described steps. The same symbols as those used in FIGS. It has meaning. However, for simplicity, the bit line made of Al shown in FIGS. 40 and 45 is removed in FIG.

FIG. 47 is a main part equivalent circuit diagram of the high resistance load type SRAM described with reference to FIGS. In the figure, Q1 and Q2 are driving transistors,
Q3 and Q4 are transfer gate transistors,
R1 and R2 are high resistance loads, WL is a word line, BL and / BL are bit lines, S1 and S2 are nodes, V _CC is a positive power supply voltage, and V _SS is a negative power supply voltage.

The operation in the high resistance load type SRAM,
In particular, storage is performed as follows.
Now, the positive power supply voltage V _CC = 5 [V], the negative power supply voltage V _SS =
0 [V], the node S1 = 5 [V],
Assuming that the node S2 = 0 [V], the transistor Q
2 is on, and transistor Q1 is off. At the node S1, the potential is maintained at 5 [V] when the transistor Q1 is off and the resistance value in that case is sufficiently higher than the high resistance load R1. At the node S2, when the transistor Q2 is on,
If the resistance value in this case is sufficiently lower than the high resistance load R2, the potential is maintained at 0 [V].

However, under the above conditions, the negative power supply voltage V _{SS is} supplied from the positive power supply voltage V _CC supply line side through the node S2.
A direct current flows on the supply line side, and its value is inversely proportional to the value of the high resistance load R2.

As the degree of integration of such a high resistance load type SRAM increases, the number of memory cells per chip increases. Therefore, unless the current consumption per memory cell is reduced, the current consumption of the entire chip increases. Would. Therefore, the DC current has to be reduced, and this requires increasing the values of the high resistance loads R2 and R1. However, when the resistance value is increased, it becomes difficult to stably maintain the potential at the node on the side where the driving transistor is turned off, in the example described above.

With the background described above, a TFT load type SRAM using a TFT instead of a high resistance has appeared.

Here, the TFT load type SRAM will be described. As in the case of the high resistance load type SRAM, first, the case of manufacturing the TFT load type SRAM will be described.

FIGS. 48 to 51 show a TFT load type SRAM.
FIGS. 52 to 55 are cut-away side views of essential parts in important process steps for explaining a conventional example of a method of manufacturing a TFT.
Principal plan views at key process steps for explaining a conventional example of a method of manufacturing a load type SRAM are respectively shown. Hereinafter, description will be made with reference to these drawings. 48 to 51 are sectional views taken along the line YY shown in FIG. 55 which is a plan view of the principal part. The steps from 31- (1) to 37- (2), which are the steps in the case of manufacturing the above-described high resistance load type SRAM, that is, the steps up to forming the load resistance contact hole 9A are as follows.
This is almost the same in the process of manufacturing this TFT load type SRAM. Only the ground line 8 made of the second polysilicon film is applied to the TFT load made of the third polysilicon film. Hole 8A (see FIG. 52) necessary for the gate electrode to be in contact with the active region and the gate electrode 4 formed of the first polycrystalline silicon film.
Only the differences that form the
It will be described from a later stage. Needless to say, the same symbols as those used in FIGS. 31 to 47 represent the same parts or have the same meanings.

See FIGS. 48 and 52. 48- (1) By applying the CVD method, a thickness of, for example, 1500
[3] A third polycrystalline silicon film is formed. 48- (2) The dose amount is set to 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 20 [keV]
And implant P ions. 48- (3) The third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas to load a TFT. Of the gate electrode 15 is formed.

Referring to FIG. 49, 49- (1) The gate insulating film 1 of a TFT load having a thickness of, for example, 300 [Å] made of SiO ₂ by applying the CVD method.
6 is formed. 49- (2) The resist process in the photolithography technique and the wet etching method using hydrofluoric acid as an etchant are applied to selectively etch the gate insulating film 16 to form a drain contact hole. 16
Form A.

See FIGS. 50 and 53. 50- (1) A thickness of, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 50- (2) Applying a resist process and an ion implantation method in the photolithography technology to reduce the dose to 1
× 10 ¹⁴ [cm ^-2 ] and acceleration energy of 5 [keV]
Then, B ions are implanted into a portion to be a source region and a drain region of a TFT load and a portion to be a _Vcc supply line. 50- (3) By applying a resist process in photolithography and an RIE method using CCl ₄ / O ₂ as an etching gas, the fourth polycrystalline silicon film is patterned to load the TFT load. , A source region 17, a drain region 18, a channel region 19, and a _VCC power supply line 20.

See FIGS. 51 and 54. 51- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. In this figure, as in FIG. 40, two layers of insulating films are integrally shown, and this is referred to as an insulating film 21. 51- (2) A heat treatment is performed to reflow and planarize the insulating film 21. 51- (3) Selective etching of the insulating film 21 and the like is performed by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, and Form a hole. 51- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed and is patterned by applying a normal photolithography technique to form a bit line 22. Note that those not described with reference to the symbols described in FIGS. 48 to 54, for example, BL and the like will become clear when compared with FIG. 56 described later.

FIG. 55 is a plan view of a principal part of the TFT load type SRAM completed through the above-described steps. The symbols used in FIGS. 31 to 54 denote the same parts or have the same meanings. Have However, for simplicity, the bit lines made of Al shown in FIGS. 51 and 54 are removed in FIG.

FIG. 56 is a main part equivalent circuit diagram of the TFT load type SRAM described with reference to FIGS. 48 to 55 and FIG. 47 represent the same parts or have the same meaning. In the figure, Q5 and Q6 indicate transistors which are load TFTs, respectively.

The operation in this TFT load type SRAM,
In particular, storage is performed as follows.

Now, the positive power supply voltage V _CC = 5 [V] and the negative power supply voltage V _SS = 0 [V] are set, respectively, and the node S1
= 5 [V] and the node S2 = 0 [V], the transistor Q2 is on and the transistor Q6 is off, and the transistor Q1 is off and the transistor Q5 is on. At the node S1, the potential is maintained at 5 [V] when the transistor Q1 is off and the resistance value in that case is sufficiently higher than the on state of the transistor Q5. At the node S2, the transistor Q2 is in the ON state, and the resistance value in that case is the transistor Q2.
If the potential is sufficiently low compared to the off state of No. 6, the potential becomes 0
[V] is maintained.

As described above, under the above conditions, the resistance value of the transistor Q5 or the transistor Q6, which is a load, changes according to the stored information.
The problem in M is solved, and stable information storage can be performed. The transistors Q5 and Q6 used here
The channel of the load TFT, that is, the channel in the load TFT is made of polycrystalline silicon, and its crystal state is much worse than that of a single crystal. Since the leakage current is the current consumption of the chip as it is, it is desirable to make it as small as possible.

By the way, as is apparent from FIG. 51, in this TFT load type SRAM, A
A bit line 22 made of an l film is provided, and a channel of a load TFT exists immediately below the bit line 22 via an insulating film 21 made of PSG or the like.

Such a structure can be regarded as a transistor having the bit line 22 made of an Al film as a gate electrode and the insulating film 21 thereunder as a gate insulating film. The potential of the line 22 is 0 [V]
(V _ss ) to 5 [V] (V _cc ), so that the TFT which should be in the off state, ie, the transistor Q6, is close to the on state, the leakage current increases, and the parasitic effect is remarkable. Become. In order to solve such a problem, a TFT with a double gate structure, which is an improved type of the TFT with load, has been developed.

This double gate structure TFT load type SRAM
Now, the third polycrystalline silicon film in the TFT load type SRAM described with reference to FIGS. 48 to 56, specifically, the second gate electrode having the same pattern as the gate electrode 15 of the TFT load will be described. The fifth polycrystalline silicon film is formed of a source region 17, a drain region 18, a channel region 19, and a fourth polycrystalline silicon film constituting a V _CC power level supply line 20 and the like and a bit line 22 made of Al. The above problem is solved by interposing it between them.

FIGS. 57 to 59 show TFTs having a double gate structure.
FIGS. 2A and 2B are cut-away side views of essential parts at important steps in a process for explaining a conventional example of a method of manufacturing a load type SRAM, and will be described below with reference to these figures. It should be noted that the above-described steps for manufacturing the TFT load type SRAM from 48- (1) to 50- (3), that is,
The steps of forming the source region 17, the drain region 18, the channel region 19 of the load, and the _Vcc power supply level supply line 20 are performed by the double gate structure TFT load type SRAM.
Are almost the same in the process of manufacturing the same, and the following steps will be described. Of course, the same symbols as those used in FIGS. 31 to 56 represent the same parts or have the same meaning.

Referring to FIG. 57, 57- (1) An insulating film 23 made of SiO ₂ and having a thickness of, for example, 500 [Å] is formed by applying the CVD method. 57- (2) Fourth polycrystal by selectively etching insulating film 23 by applying a resist process in photolithography technology and an RIE method using CHF ₃ + He as an etching gas. A contact hole 23A for the silicon film is formed.

Referring to FIG. 58, 58- (1) The thickness is, for example, 1000 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 58- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 58- (3) The fifth polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas to load a TFT. Of the second gate electrode 24 is formed.

Referring to FIG. 59, a thickness of, for example, 1000 is obtained by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. In this figure, as in FIG. 51, the two-layer insulating film is integrally shown and is referred to as an insulating film 25. 59- (2) A heat treatment for reflowing and flattening the insulating film 25 is performed. 59- (3) By selectively etching the insulating film 25 and the like by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, Form a hole. 59- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 26.

[0038]

As described above,
SRAM starts with a high resistance load type, a TFT load type,
It has progressed to a double gate structure TFT load type. However, first, FIGS. 31 to 40 (particularly, FIG. 40) and FIG.
59 (especially FIG. 59), it should be clear that the double gate structure TF
In shifting to the T-load type SRAM, the number of polycrystalline silicon films has increased by two layers, and the number of mask steps has actually increased four times.

By the way, not only the SRAM as described above, but also "miniaturization" is the most important proposition in semiconductor memory devices. In recent years, the size of the SRAM has been remarkably reduced. Is causing problems.

It is well known that a memory capacitor is necessary even for an SRAM. Generally, the memory capacitor includes a parasitic capacitance near a node between a driver transistor and a load. We are using. Therefore, the capacity of the memory capacitor is
High resistance load type SRAM is the smallest and TFT load type SR
AM slightly increased, double gate structure TFT load type SR
AM is the largest.

However, even with the double gate structure TFT load type SRAM, as described above, as the miniaturization progresses, the capacity of the memory capacitor becomes insufficient.

Therefore, instead of relying on the parasitic capacitance as described above, it is necessary to intentionally provide a separate memory capacitor. However, as described above, the number of mask steps is increased. Therefore, it is necessary to minimize the increase in the number of steps when fabricating a memory capacitor.

According to the present invention, a TFT-loaded SRAM having high resistance to soft errors due to radiation and capable of operating stably without being affected by noise from other conductive portions in the memory cell is obtained. Thus, it is intended to reduce the number of steps for manufacturing the same.

[0044]

SUMMARY OF THE INVENTION In a semiconductor memory device according to the present invention, (1) a pair of driver transistors (for example, a pair of driver transistors formed on a semiconductor substrate (for example, a silicon semiconductor substrate 1) and constituting a flip-flop circuit); For example, the driving transistors Q1 and Q2: FIG. 47 and the like, and a pair of TFT loads (for example, the source region 17 and the drain) formed on the semiconductor layer (for example, the fourth polycrystalline silicon film shown in FIG. 1) on the semiconductor substrate. The region 18 and the channel region 19) and the memory capacitor formed above the TFT load (for example, the storage electrode 33, the dielectric film 34, and the counter electrode 35 of the memory capacitor also serving as the shield electrode of the TFT load). The TFT load is connected to a gate (eg, drain region 6) of the driver transistor. (For example, a channel region 19) formed on the gate electrode (for example, the gate electrode 15) and the gate electrode via a gate insulating film (for example, the gate insulating film 16), and a source (for example, a source region) opposed to the channel. 1
7) and a drain (for example, the drain region 18), and the memory capacitor includes a storage electrode (for example, the storage electrode 33), a dielectric film for the memory capacitor (for example, the dielectric film 34) covering the storage electrode, memory·
A counter electrode of a memory capacitor (eg, a shield of a TFT load) which is formed on a channel of the TFT load via an insulating film and faces the storage electrode via a capacitor dielectric film and also serves as a shield electrode of the TFT load. A counter electrode 35 of a memory capacitor also serving as an electrode, and at least a storage electrode of the memory capacitor (eg, storage electrode 33) and a drain of the TFT load (eg, drain region 18) in the same connection region. And a gate electrode (for example, the gate electrode 15) and a gate electrode (for example, the gate electrode 4) or a drain (for example, the drain region 6) of the driver transistor are connected to each other. In (1), the storage electrode (for example, storage The fin (fin 32) of the memory capacitor is provided between the electrode 33) and the counter electrode of the memory capacitor also serving as the shield electrode of the TFT load (for example, the counter electrode 35 of the memory capacitor also serving as the shield electrode of the TFT load). (3) In the above (1), the storage electrode (for example, the storage electrode 33) of the memory capacitor in the uppermost layer is a memory capacitor.
In an interconnect contact hole (eg, interconnect contact hole 31A) that penetrates the capacitor fin (eg, fin 32) and the TFT load drain (eg, drain region 18) and the TFT load gate electrode (eg, gate electrode 15). Wherein the contact is made with each side surface and with the surface of the gate electrode (for example, the gate electrode 4) or the drain (for example, the drain region 6) of the lowermost driver transistor, or 4) In the above (1), the counter electrode of the memory capacitor also serving as the shield electrode in the TFT load (for example, the counter electrode 35 of the memory capacitor also serving as the shield electrode in the TFT load) and the TFT load. Silicon nitride between the channel (eg, channel region 19) An insulating film (for example, insulating film 29) made of silicon is used as a counter electrode of the memory capacitor also serving as a shield electrode in the TFT load (for example, a counter electrode 35 of the memory capacitor also serving as a shield electrode in the TFT load). (5) In the above (1), (2), (3) or (4), a potential substantially equal to the source potential in the TFT load. Or (6) a field insulating film (e.g., a silicon semiconductor substrate 1) on the surface of a semiconductor substrate (e.g., a silicon semiconductor substrate 1). Forming a gate insulating film (eg, gate insulating film 3) after forming the field insulating film 2), and then forming a first conductive film (eg, first A step of forming a gate electrode (eg, gate electrode 4) of the driver transistor by patterning after growing a crystalline silicon film) and then a step of forming the driver transistor, which is the field insulating film and the first conductive film. Impurity is introduced by using the gate electrode as a mask to form impurity regions (eg, source region 5 and drain region 6).
After forming the first insulating film (for example, insulating films 7 and 9)
And a second conductive film (for example, a third polycrystalline silicon film: FIG. 1) contacting a gate electrode (for example, gate electrode 4) or a drain (for example, drain region 6) of the driver transistor. Forming a gate electrode (for example, gate electrode 15) of a TFT load, forming a gate insulating film (for example, gate insulating film 16) as a second insulating film, and then patterning the TFT. A semiconductor layer (for example, a fourth polycrystalline silicon film: FIG. 1), which is a third conductive film, in contact with a load gate electrode (for example, gate electrode 15) is grown and selectively doped with impurities and patterned to perform TFT load. Source region (for example, source region 17), drain region (for example, drain region 18) and channel region (for example, channel region 9), forming a film (eg, insulating film 29) acting as an etching stopper, and then growing a film (eg, insulating film 30) acting as a spacer, and then forming a drain region of the TFT load. A step of growing a fourth conductive film (for example, a fifth polycrystalline silicon film: FIG. 1) in contact with (for example, the drain region 18), and then patterning the fourth conductive film to store a memory capacitor Forming an electrode (for example, storage electrode 33), and then removing an insulating film (for example, insulating film 30) serving as the spacer, which is a base of the storage electrode (for example, storage electrode 33) of the memory capacitor. And then a dielectric film (for example, a dielectric film) for the memory capacitor covering the storage electrode (for example, the storage electrode 33) of the memory capacitor. Forming a body layer 34), then the counter electrode (e.g. T memory capacitor also serving as a shield electrode of the TFT load which covers the memory capacitor dielectric film (e.g., a dielectric film 34)
Forming a counter electrode 33) of a memory capacitor also serving as a shield electrode of an FT load, or (7) the drain region of the TFT load in the above (6). (For example, the drain region 18) and the gate electrode (for example, the gate electrode 15) of the TFT load, the transistor
After forming an interconnect contact hole (eg, interconnect contact hole 31A: FIG. 8) reaching the surface of the gate electrode (eg, gate electrode 4) or drain (eg, drain region 6) of the transistor, the drain region of the TFT load is formed. (Eg, drain region 18) and TFT
The gate electrode of the load (for example, the gate electrode 15) is a side surface exposed in the interconnect contact hole (for example, the interconnect contact hole 31A) and the gate electrode (for example, the gate electrode 4) or the drain (for the driver transistor) of the driver transistor. For example, the drain region 6) is an interconnect contact hole (eg, the interconnect contact hole 31).
Or (8) forming a storage electrode (eg, storage electrode 33) of a memory capacitor to be in contact with each of the surfaces exposed at the bottom of (A). Or, in (7), etching
A conductive film serving as a fin (for example, fin 32) of a memory capacitor serves as a spacer between a film (for example, an insulating film 29) serving as a stopper and a conductive film serving as a storage electrode (for example, a storage electrode 33) of a memory capacitor. (9) In the above (6), (7) or (8),
The same mask (eg, a photo-resist film) is used when patterning a conductive film to be a counter electrode of a memory capacitor also serving as a shield electrode of a TFT load (eg, a counter electrode 35 of a memory capacitor also serving as a shield electrode of a TFT load). 13 and FIG. 14), characterized by including a step of patterning a film (for example, insulating film 29) acting as an etching stopper.

[0045]

As is evident from the above description, in the present invention, a memory capacitor is separately provided above the TFT load, and since the capacity can be increased due to the configuration, the memory capacitor can be used. The resistance to soft errors is improved, and the counter electrode of the memory capacitor can also serve as an electrode for shielding the TFT load from others. It can be easily and easily manufactured with high yield by the number of manufacturing steps.

[0046]

FIG. 1 to FIG. 5 are cutaway side views of a principal part of a TFT load type SRAM at a key point of a process for explaining a first embodiment of the present invention. It will be explained while doing. 1 to 5 are cut-away views similar to those cut along the line Y-Y shown in FIG. 55, which is a plan view of a main part of a conventional TFT load type SRAM. Yes, and from the beginning of the step of manufacturing the conventional TFT load type SRAM described with reference to FIGS. 48 to 51 to step 50- (3), that is, the source region 17, the drain region 18, and the channel region in the TFT load. 19, and the same is applied to the present embodiment up to the formation of the _Vcc power supply line and the like.

FIG. 1 1- (1) Here, the TFT load type SRAM has a field insulating film 2, a gate insulating film 3, and a gate electrode of a driver transistor formed of a first polycrystalline silicon film on a silicon semiconductor substrate 1. 4, n ⁺ -impurity region 5 ', n ⁺ -source region 5,
n ⁺ - drain region 6, SiO ₂ formed of an insulating film 7, the second polycrystalline silicon film consisting of the ground line 8, consisting of SiO ₂ insulating film 9, TFT consisting of a third polycrystalline silicon film
A gate electrode 15 of a load, a gate insulating film 16 of a TFT load made of SiO _2, and a TFT made of a fourth polycrystalline silicon film.
It is assumed that the source region 17, the drain region 18, the channel region 19 of the FT load, and the _Vcc power supply level supply line (not shown) are formed. 1- (2) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 29 made of Si ₃ N ₄ is formed on the entire surface. The insulating film 29 not only plays a role of electrical insulation but also functions as an etching stopper. 1- (3) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 30 serving as a spacer made of SiO ₂ is formed on the entire surface. 1- (4) A thickness of, for example, 500 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed on the entire surface. 1- (5) The dose amount is set to 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 10 [keV]
And implant P ions. 1- (6) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 31 serving as a spacer made of SiO ₂ is formed on the entire surface. 1- (7) Photo lithography to in the resist process and an etching gas CHF ₃ / the He (for a SiO ₂ and Si ₃ N ₄₎ and CCl ₄ / O ₂ (for polycrystalline silicon)
By applying the RIE method, each of the insulating film 31 acting as a spacer, the fifth polycrystalline silicon film, the insulating film 30 acting as a spacer, and the insulating film 29 serving as an etching stopper and also for electrical insulation is formed. TFT consisting of a third polycrystalline silicon film from the surface by selective etching
Interconnect contacts to reach the drain region 18 of the load
A hole 31A is formed.

FIG. 2 2- (1) The thickness is, for example, 500 by applying the CVD method.
[6] A sixth polycrystalline silicon film is formed. 2- (2) By applying a thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 2- (3) Application of RIE method using CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for SiO ₂ ) as resist process and etching gas in photolithography technology Accordingly, the sixth polycrystalline silicon film, the insulating film 31 acting as a spacer, and the fifth polycrystalline silicon film are patterned to form the storage electrode 33 of the memory capacitor and the memory extending from the storage electrode 33.
The fin 32 of the capacitor is formed. In this case, the insulating film 30 is used as an etching stopper for the fins 32. Since the insulating film 30 is removed as described in the next step 3- (1), the insulating film 30 is used for etching the fins 32. It is not necessary to worry about the damage of the insulating film 30, and the residue can be completely removed by performing sufficient over-etching. This is because the location is below the lowermost fin and the TFT
This is possible because the counter electrode also serving as a shield electrode wraps around the load channel region.

FIG. 3 3- (1) An insulating film 31 made of SiO ₂ immersed in an aqueous HF solution,
Remove 30.

Referring to FIG. 4, 4- (1) a thickness of, for example, 200 made of Si ₃ N _{4 on the} surface of the storage electrode 33 of the memory capacitor and the fin 32 of the memory capacitor by applying the CVD method.
[Å] The memory capacitor dielectric film 34 is formed. 4- (2) The thickness is, for example, 1000 by applying the CVD method.
[7] A seventh polycrystalline silicon film is formed. 4- (3) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the seventh polycrystalline silicon film. 4- (4) RIE using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
By applying the method, the seventh polycrystalline silicon film is patterned to form the counter electrode 35 of the memory capacitor also serving as the shield electrode. Usually, the counter electrode 35 of the memory capacitor also serving as the shield electrode is
If the TFT load is a p-channel type, a V _CC power level, ie, 5 [V], is applied. If an n-channel type, the V _SS power level, ie, 0 [V], is applied. -Shields noise from entering the TFT load from other conductive layers in the cell. By the way, Step 2-
As described in (3), when the fins are formed and are manufactured stably by performing sufficient over-etching, the counter electrode goes around between the lowermost fins and the channel region of the TFT load. Configuration. The present invention is greatly characterized in that by using this counter electrode also as a shield electrode for a TFT load, both the stable formation of fins and the prevention of the parasitic effect of the TFT load are compatible.

Referring to FIG. 5, 5- (1) the thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. Note that, also in this figure, as in FIG. 59, the two-layered insulating film is integrally shown and is referred to as an insulating film 36. 5- (2) A heat treatment is performed to reflow and planarize the insulating film 36. 5- (3) Selective etching of the insulating film 36 and the like is performed by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, and Form a hole. 5- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 37.

In the first embodiment described above, the capacity of the memory capacitor is sufficiently large, and the TFT load is shielded by the counter electrode 35, so that it is not affected by noise. In addition, when etching the memory capacitor, it is possible to perform sufficient over-etching, so that stable production is possible. However, when compared with the conventional technology related to the double gate structure,
The mask layer is increased only once.

FIGS. 6 to 12 are cutaway side views of a principal part of a TFT load type SRAM at a key point of a process for explaining a second embodiment of the present invention. I will explain it. 1 to 5 are plan views of main parts of a conventional TFT load type SRAM.
A cutting plane similar to the cutting plane along the line Y-Y shown in FIG. 31 is taken, and from the beginning of the step of manufacturing the conventional high resistance load type SRAM described with reference to FIGS. The process up to (1), that is, the process up to the formation of the ground line 8 made of the second polycrystalline silicon film is the same in the present embodiment.

FIG. 6 6- (1) Here, in the TFT load type SRAM, a gate electrode of a driver transistor comprising a field insulating film 2, a gate insulating film 3, and a first polycrystalline silicon film on a silicon semiconductor substrate 1. 4, n ⁺ -impurity region 5 ', n ⁺ -source region 5,
It is assumed that an n ⁺ -drain region 6, an insulating film 7 made of SiO ₂ and a ground line 8 made of a second polycrystalline silicon film are formed. 6- (2) By applying the CVD method, the thickness is, for example, 1000
[Å] The insulating film 9 made of SiO ₂ is formed. 6- (3) A thickness of, for example, 500 by applying the CVD method.
[3] A third polycrystalline silicon film is formed. 6- (4) The dose amount is 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 10 [keV]
And implant P ions. 6- (5) The third polycrystalline silicon film is patterned by applying a resist process in the photolithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas to load the TFT. Of the gate electrode 15 is formed.

FIG. 7 7- (1) The gate insulating film 1 of a TFT load having a thickness of, for example, 200 [Å] made of SiO ₂ by applying the CVD method.
6 is formed. 7- (2) The thickness is, for example, 200 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 7- (3) By applying a resist process and an ion implantation method in the photolithography technology, the dose amount is reduced to 1
× 10 ¹⁴ [cm ^-2 ] and acceleration energy of 5 [keV]
Then, B ions are implanted into portions to be the source and drain regions of the TFT load. 7- (4) RIE using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
By applying the method, the fourth polycrystalline silicon film is patterned to form a source region 17, a drain region 18, a channel region 19 of a TFT load, a _VCC power level supply line (not shown in the drawing), and the like. To form

8- (1) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 29 made of Si ₃ N ₄ is formed on the entire surface. 8- (3) The thickness is, for example, 500 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 8- (4) The dose amount is set to 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 10 [keV]
And implant P ions. 8- (5) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 31 serving as a spacer made of SiO ₂ is formed on the entire surface. 8- (6) RIE using CHF ₃ / He (for SiO ₂ and Si ₃ N ₄ ) and CCl ₄ / O ₂ (for polycrystalline silicon) as the resist process and etching gas in the photolithography technology By applying the method, the insulating film 31 acting as a spacer, the fifth polycrystalline silicon film, the insulating film 29, the drain region 18 of the TFT load which is the fourth polycrystalline silicon film, the gate insulating film 16, The gate electrode 15, the insulating film 9, and the insulating film 7, which are the three polycrystalline silicon films, are selectively etched to reach the gate electrode 4 of the driving transistor made of the first polycrystalline silicon film from the surface. A hole 31A is formed. This step is very characteristic in the second embodiment. That is, the number of mask steps for the interconnect contact holes has been reduced twice as compared with the first embodiment.

9- (1) The thickness is, for example, 500 by applying the CVD method.
[6] A sixth polycrystalline silicon film is formed. 9- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film. 9- (3) Applying the RIE method using CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for SiO ₂ ) as a resist process and an etching gas in photolithography technology Accordingly, the sixth polycrystalline silicon film, the insulating film 31 acting as a spacer, and the fifth polycrystalline silicon film are patterned to form the storage electrode 33 of the memory capacitor and the fin 32 of the memory capacitor. In this case, as in the first embodiment, sufficient over-etching is possible, and the fins 32 can be formed stably.

Referring to FIG. 10, 10- (1) The insulating films 31 and 30 functioning as spacers made of SiO ₂ are immersed in an aqueous HF solution to be removed.

11- (1) By applying the CVD method, the surface of the storage electrode 33 of the memory capacitor and the surface of the fin 32 of the memory capacitor have a thickness of, for example, 200 [Å] made of Si ₃ N _4. Is formed. 11- (2) A thickness of, for example, 1000 by applying the CVD method.
[7] A seventh polycrystalline silicon film is formed. 11- (3) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the seventh polycrystalline silicon film. 11- (4) RIE using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
By applying the method, the seventh polycrystalline silicon film is patterned to form the counter electrode 35 of the memory capacitor also serving as the shield electrode.

FIG. 12 12- (1) The thickness is, for example, 500 by applying the CVD method.
[Å] an insulating film made of SiO ₂ and a thickness of, for example, 500
An insulating film made of 0 [Å] PSG is formed. Note that, also in this figure, as in FIG. 5, the two-layer insulating film is integrally shown and is referred to as an insulating film 36. 12- (2) A heat treatment is performed to reflow and planarize the insulating film 36. 12- (3) Selective etching of the insulating film 36 and the like is performed by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, and Form a hole. 12- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 37.

As can be seen from the above description, FIG.
The second embodiment described with reference to FIGS. 12 to 12 is different from the first embodiment described with reference to FIGS. 1 to 5 in that the storage electrode 33 of the memory capacitor can be directly contacted with the gate electrode 4 of the driver transistor. The difference is that a connection contact hole 31A is formed.

As a result, the interconnect contact holes 31A can be formed in a single mask step, two times in comparison with the first embodiment, and in comparison with the conventional double gate structure. For one batch, the number of mask steps is reduced, and the manufacturing process is simplified. Moreover, a sufficiently large memory capacitor can be stably manufactured while preventing the parasitic effect of the TFT load.

FIG. 13 to FIG. 15 are cutaway side views of a principal part of a TFT load type SRAM at a key point of a process for explaining a third embodiment of the present invention. I will explain it. 13 to 15 are sectional views taken along the line YY shown in FIG. 55 which is a plan view of a principal part of a conventional TFT load type SRAM. In addition, from the beginning of the process in the second embodiment described with reference to FIGS.
The process up to (3), that is, until P is diffused into the seventh polycrystalline silicon film to make it conductive, is the same in the present embodiment.

13- (1) Here, the TFT load type SRAM has a gate electrode of a driver transistor comprising a field insulating film 2, a gate insulating film 3, and a first polycrystalline silicon film on a silicon semiconductor substrate 1. 4, n ⁺ -impurity region 5 ', n ⁺ -source region 5,
n ⁺ - drain region 6, made of SiO ₂ insulating film 7, the second polycrystalline silicon film consisting of the ground line 8, consisting of SiO ₂ insulating film 9, a gate electrode 15 of the TFT load, TFT load of the gate insulating film 16 , The source region 17 of the TFT load,
Drain region 18 of the TFT load, channel region 19 of the TFT load, insulating film 29 made of Si ₃ N ₄ , fin of the memory capacitor, storage electrode 3 of the memory capacitor
3. It is assumed that the memory capacitor dielectric film 34 is formed and a polycrystalline silicon film is deposited on the entire surface. 13- (2) By applying a resist process in photolithography technology, memory
A photoresist film 38 having a pattern for forming a counter electrode of a capacitor is formed.

Referring to FIG. 14, 14- (1) The seventh polycrystalline silicon film is patterned by using the photoresist film 38 as a mask by applying the RIE method using CCl ₄ / O ₂ as an etching gas. , Counter electrode 35 of memory capacitor also serving as shield electrode
To form 14- (2) The insulating film 29 made of Si ₃ N ₄ is patterned by applying the RIE method in which the etching gas is CCl ₄ / O ₂ with the photo resist film 38 left. Through this step, at least the insulating film 29 made of Si ₃ N ₄ covering the portion where the bit line contact hole is to be formed is removed.

FIG. 15 15- (1) A thickness of, for example, 500 by applying the CVD method.
[Å] an insulating film made of SiO ₂ and a thickness of, for example, 500
An insulating film made of 0 [Å] PSG is formed. Note that, also in this figure, as in FIGS. 5 and 12, two layers of the insulating film are integrally shown, and this is referred to as an insulating film 36. 15- (2) A heat treatment for reflowing and flattening the insulating film 36 is performed. 15- (3) Selective etching of the insulating film 36 and the like is performed by applying a resist process in photolithography technology and an RIE method using CHF ₃ / He as an etching gas to perform bit line contact. Form a hole. 15- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 37.

In the embodiment described with reference to FIGS. 13 to 15, patterning the insulating film 29 made of Si ₃ N ₄ by using a mask in which the counter electrode 35 of the memory capacitor is patterned, It offers significant advantages in forming, and will now be described.

FIGS. 16 to 19 are cutaway side views of main parts of a semiconductor device at important steps in the process for explaining the reason for the embodiment described with reference to FIGS. 13 to 15. This will be described with reference to FIG.

16- (1) Here, an insulating film 102 made of SiO ₂ , an insulating film 103 made of Si ₃ N ₄ on a silicon semiconductor substrate 101,
It is assumed that insulating films 104 made of PSG are sequentially stacked. 16- (2) Insulating film 104 using photo resist film 105 having opening 105A as a mask by applying a resist process in photolithography technology and an RIE method using CHF ₃ / He as an etching gas. Is selectively etched to form a contact hole 10 reaching the surface of the silicon semiconductor substrate 101 from the surface of the insulating film 104.
4A is formed.

Referring to FIG. 17 17- (1) The photoresist film 105 is ashed and removed in oxygen plasma by applying the plasma ashing method. At this time, a thin oxide film 106 is formed on the surface of the silicon semiconductor substrate 101 exposed at the bottom of the contact hole 104A.

See FIG. 18. 18- (1) The thin oxide film 106 is removed by immersion in an HF aqueous solution.
At this time, the insulating film 104 made of PSG and the insulating film 102 made of SiO ₂ are etched, and the wall surface in the contact hole 104A recedes. However, Si ₃ N
_Since only the insulating film 103 made of ₄ is not etched, the insulating film 103 protrudes into the contact hole 104A.

19- (1) An electrode / wiring film 107 made of Al is formed by applying a sputtering method. At this time, the electrode / wiring film 107 is projected to the S
There is a possibility that the film is divided by the action of the insulating film 103 made of i ₃ N ₄ .

As described above, the phenomena described with reference to FIGS. 16 to 19 are completely applied to the case where the bit line contact hole of the TFT load type SRAM according to the present invention is formed. In the embodiment described with reference to No. 15, there is no problem because the insulating film 29 made of Si ₃ N ₄ does not exist in the portion where the bit line contact hole is to be formed. The number of steps does not increase because the mask step also serves as a mask step.

FIG. 20 is a plan view of a principal part of a TFT load type SRAM having a split word line realized by the present inventors. In the figure, 41 is the gate of the TFT, 4
2 indicates a channel of the TFT, 43 indicates a word line, and V _CC indicates a positive power supply level.

In this SRAM, the symmetry of the driver transistor, TFT and the like is good, and the interconnection area is two places for one memory cell. Therefore, there is an advantage that the layout is easy. Next, an embodiment in which the present invention is applied to the TFT load type SRAM will be described.

FIGS. 21 to 30 are cut-away side views of a main part of a TFT load type SRAM at a process point for explaining a fourth embodiment of the present invention. This will be described in detail. 21 to 30 correspond to FIG.
A section taken along a line XX indicated by 0 is taken.

21- (1) A pad film made of SiO ₂ covering the active region of the silicon semiconductor substrate 51 and Si ₃ laminated on the pad film
By applying a selective thermal oxidation method using an oxidation-resistant mask film made of N _4, a field insulating film 52 made of SiO ₂ and having a thickness of, for example, 4000 [Å] is formed. 21- (2) By removing the oxidation-resistant mask film and the pad film to expose the active region, and then applying the thermal oxidation method, SiO ₂
The gate insulating film 53 having a thickness of, for example, 100 [Å] is formed. 21- (3) Selective etching of the gate insulating film 53 is also performed for impurity diffusion by applying a resist process in photolithography technology and a wet etching method using an etchant as hydrofluoric acid. contact·
Form a hole. 21- (4) Thickness, for example, 1000 by applying the CVD method
[Å] First polycrystalline silicon film is formed. 21- (5) An n ⁺ -impurity region 54 is formed by introducing P by setting the impurity concentration to, for example, 1 × 10 ²⁰ [cm ⁻³ ] by applying the vapor phase diffusion method. 21- (6) The first polycrystalline silicon film is patterned by applying a resist process in the photolithography technique and an RIE method using an etching gas of CCl ₄ + O ₂ to form a gate electrode 55. And 56 are formed. 21- (7) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ], and the acceleration energy is set to 30.
[KeV] is implanted with As ions to obtain n ⁺ −
A source region 57 and an n ⁺ -drain region 58 are formed.

See FIG. 22 22- (1) By applying the CVD method, a thickness of, for example, 1000
[Å] An insulating film 59 made of SiO ₂ is formed. 22- (2) Thickness, for example, 1000 by applying the CVD method
[Å] A second polycrystalline silicon film is formed. 22- (3) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ] and the second polycrystalline silicon film
Introduce. 22- (4) Patterning of the second polycrystalline silicon film by applying a resist process in photolithography and an RIE method using CCl ₄ / O ₂ as an etching gas to load a TFT Is formed.

Referring to FIG. 23, 23- (1) The thickness is, for example, 200 by applying the CVD method.
[Å] An insulating film 62 made of SiO ₂ is formed. 23- (2) A thickness of, for example, 200
[3] A third polycrystalline silicon film is formed. 23- (3) Applying a resist process and an ion implantation method in photolithography technology to supply a source region and a drain region of a TFT load in the third polycrystalline silicon film, and supply a V _CC power level. A dose amount of 1 × 10 ¹⁴ [cm ⁻² ] and acceleration energy of 5
B is implanted as [keV]. 23- (4) A third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. Then, a drain region, a source region, a channel region, a _VCC power supply level supply line, and the like of each TFT load are formed. In the figure, not all of the above parts can be shown, and a contact portion 64 connected to the tip of a drain region of a certain TFT load and a channel region 67 of the TFT load adjacent to the TFT load are shown.

Referring to FIG. 24, 24- (1) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 79 serving as an etching stopper made of Si ₃ N ₄ is formed.

See FIG. 25. 25- (1) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 81 made of SiO ₂ is formed. 25- (4) RIE using CHF ₃ / He (for SiO _{2 and} for Si ₃ N ₄ ) and CCl ₄ / O ₂ (for polycrystalline silicon) as resist process and etching gas in photolithography technology By applying the method, the insulating film 8
1, the insulating film 79, the contact portion 64 made of the third polycrystalline silicon film, the insulating film 62, the gate electrode 61 of the TFT load made of the second polycrystalline silicon film, and the insulating film 59 are selectively etched to form a surface. From the gate electrode 56 or 5 of the driving transistor which is the first polycrystalline silicon film.
5, forming an interconnect contact hole 81A.

26- (1) A thickness of, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 26- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fourth polycrystalline silicon film.

26- (3) Resist process in photolithography technology and RIE using CCl ₄ / O ₂ as an etching gas
The fourth polycrystalline silicon film is patterned by applying the storage electrode 82 of the memory capacitor.
To form

See FIG. 27 27- (1) The insulating film 81 made of SiO ₂ is removed by immersion in an aqueous HF solution.

See FIG. 28. 28- (1) By applying the CVD method, a dielectric material for a memory capacitor having a thickness of, for example, 200 [Å] made of Si ₃ N ₄ covering the surface of the storage electrode 82 of the memory capacitor. A body film 83 is formed. 28- (2) Thickness, for example, 1000 by applying the CVD method
[5] A fifth polycrystalline silicon film is formed. 28- (3) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 28- (4) RIE Using CCl ₄ / O ₂ as a Resist Process and Etching Gas in Photolithography Technology
By applying the method, the fifth polycrystalline silicon film is patterned to form the counter electrode 84 of the memory capacitor also serving as the shield electrode.

See FIG. 29. 29- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. Also in this figure, as in FIGS. 5, 12, and 15, two insulating films are integrally shown, and this is referred to as an insulating film 85. 29- (2) Heat treatment is performed to reflow and planarize the insulating film 85. 29- (3) The resist process in the photolithography technique and the RIE method using CHF ₃ / He as an etching gas are applied to selectively etch the insulating film 85 and the like to perform ground line contact / etching. Form a hole. 29- (4) Thickness, for example, 1000 by applying the CVD method
[6] A sixth polycrystalline silicon film is formed. 29- (5) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film. 29- (6) RIE using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
Depending on applying the law, to form a V _SS power level supply line 86 by patterning the sixth polycrystalline silicon film.

Referring to FIG. 30 30- (1) The thickness is, for example, 5000 by applying the CVD method.
[Å] An insulating film 87 made of PSG is formed. 30- (2) Heat treatment is performed to reflow the insulating film 87 to make it flat. 30- (3) RI in which the resist process and the etching gas in the photolithography technology are CCl ₄ / O ₂ or the like
By applying the E method, a bit line contact hole (not visible in FIG. 30, but see FIG. 20) is formed by selectively etching the insulating film 87 and the like. 30- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 88.

In the fourth embodiment described above, the TFT load is of course shielded by the counter electrode 84, so that it is not affected by noise. As in the case of the conventional double gate structure TFT load, the number of times of the masking process is reduced by one, and
Large memory capacitors can be added. Furthermore, the symmetry of the memory cell is better than that of the second embodiment, and there are only two interconnecting regions, which can be easily formed.

[0089]

According to the semiconductor memory device and the method of manufacturing the same according to the present invention, a pair of driver transistors formed on a semiconductor substrate and a pair of TFs formed on a semiconductor layer are provided.
A T-load and a memory capacitor formed above the TFT load, wherein the TFT load has a gate electrode connected to the drain of the driver transistor, a channel formed on the gate electrode via a gate insulating film, and The storage capacitor includes a source and a drain opposed to each other with the channel interposed therebetween, and the memory capacitor is opposed to the storage electrode via the storage electrode, a dielectric film covering the storage electrode, and the dielectric film, and is provided on the channel of the TFT load via an insulating film. A counter electrode of a memory capacitor formed and also serving as a shield electrode of a TFT load is provided. In the same connection region, at least a storage electrode of the memory capacitor, a drain and a gate electrode of the TFT load, and a gate electrode or a drain of a driver transistor. Are connected respectively.

As is apparent from the above description, according to the present invention, a memory capacitor is separately provided above the TFT load, and since the capacity can be increased due to the configuration, the memory capacitor can be used. The resistance to soft errors is improved, and the counter electrode of the memory capacitor can also serve as an electrode for shielding the TFT load from others.
It is possible to easily and easily manufacture a load type SRAM with a small number of manufacturing steps with a high yield.

[Brief description of the drawings]

FIG. 1 is a cutaway side view of an essential part of a TFT load type SRAM at a key point in a process for explaining a first embodiment of the present invention.

FIG. 2 is a cutaway side view of a main part of the TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 3 is a cutaway side view of a main part of the TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 4 is a cutaway side view of an essential part of the TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 5 is a cutaway side view of a principal part of the TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 6 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 7 is a cutaway side view of a main part of a TFT load type SRAM at a process key point for explaining a second embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 9 is a side cutaway view of a main part of a TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 10 is a cutaway side view of a main part of a TFT load type SRAM at a process key point for explaining a second embodiment of the present invention.

FIG. 11 is a cutaway side view of an essential part of a TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 12 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 13 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 14 is a cutaway side view of an essential part of a TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 15 is a cutaway side view of an essential part of a TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 16 is a fragmentary side view of the semiconductor device at a key step in the process for explaining the reason for the embodiment described with reference to FIGS. 13 to 15;

FIG. 17 is a fragmentary side view of the semiconductor device at a key step in the process for explaining the reason for the embodiment described with reference to FIGS. 13 to 15;

FIG. 18 is a fragmentary side view of the semiconductor device at a key step in the process for explaining the reason for the embodiment described with reference to FIGS. 13 to 15;

FIG. 19 is a fragmentary side view of the semiconductor device at a key step in the process for explaining the reason for the embodiment described with reference to FIGS. 13 to 15;

FIG. 20 is a plan view of a principal part of a TFT load type SRAM having a split word line realized by the present inventors.

FIG. 21 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 22 is a side cutaway view of a main part of a TFT load type SRAM at a process key point for explaining a fourth embodiment of the present invention.

FIG. 23 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 24 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 25 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 26 is a side cutaway view of a main part of a TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 27 is a cutaway side view of a main part of a TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 28 is a side cutaway view of a main part of a TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 29 is a cutaway side view of a main part of a TFT load type SRAM at a process key point for explaining a fourth embodiment of the present invention;

FIG. 30 is a side cutaway view of a main part of a TFT load type SRAM at a process key point for explaining a fourth embodiment of the present invention.

FIG. 31 is a cutaway side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 32 is a fragmentary side elevational view at a key step in the process for explaining a conventional example of a method of manufacturing a high resistance load type SRAM;

FIG. 33 is a side sectional view of a relevant part in a process key for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 34 is a cross-sectional side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 35 is a cutaway side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 36 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 37 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 38 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM;

FIG. 39 is a fragmentary sectional side view at a key step of the process for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 40 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 41 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a key point in a process.

FIG. 42 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high-resistance load type SRAM in a process essential point;

FIG. 43 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high-resistance load type SRAM in a process essential point;

FIG. 44 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a key point in a process;

FIG. 45 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a key point in a process.

FIG. 46 is a fragmentary plan view for explaining a conventional example of a method for manufacturing a high resistance load type SRAM at a key point in a process.

FIG. 47 is a main part equivalent circuit diagram of a high resistance load type SRAM.

FIG. 48 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 49 is a fragmentary sectional side view at a key step of the process for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 50 is a cross-sectional side view of a relevant part at a key point in a process for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 51 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 52 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM in a relevant part of a process;

FIG. 53 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM in a relevant part of a process;

FIG. 54 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM in a process essential point;

FIG. 55 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM at a key point in a process.

FIG. 56 is a main part equivalent circuit diagram of a TFT load type SRAM.

FIG. 57 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a double gate structure TFT load type SRAM.

FIG. 58 is a fragmentary side elevation view at a key step for explaining a conventional example of a method for manufacturing a double gate structure TFT load type SRAM.

FIG. 59 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a double gate structure TFT load type SRAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Field insulating film 3 Gate insulating film 4 Gate electrode 5 Source region 5 'Impurity region 6 Drain region 7 Insulating film 8 Ground line 15 Gate electrode 16 Gate insulating film 17 Source region 18 Drain region 19 Channel region 29 Etching Insulating film acting as a stopper 30 Insulating film acting as a spacer 31 Insulating film acting as a spacer 32 Fin of a memory capacitor 33 Storage electrode of a memory capacitor 34 Dielectric film for a memory capacitor 35 Also used as a shield electrode of a TFT load Counter electrode of memory capacitor

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-166554 (JP, A) JP-A-2-312271 (JP, A) JP-A-2-295164 (JP, A) JP-A-4- 115564 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8244 H01L 27/11 H01L 29/786

Claims (9)

(57) [Claims] 1. A pair of driver transistors formed on a semiconductor substrate to form a flip-flop circuit, a pair of TFT loads formed on a semiconductor layer on the semiconductor substrate, and a portion formed above the TFT load. A memory capacitor, wherein the TFT load includes a gate electrode connected to a drain of the driver transistor, a channel formed on the gate electrode via a gate insulating film, and a source facing the channel. And a drain, respectively, wherein the memory capacitor is opposed to the storage electrode via a storage electrode, a memory capacitor dielectric film covering the storage electrode, and the memory capacitor dielectric film, and is connected to the TFT load. A memory formed on a channel via an insulating film and also serving as a shield electrode for the TFT load. And at least the storage electrode of the memory capacitor, the drain of the TFT load and the gate electrode, and the gate electrode or the drain of the driver transistor are connected to each other in the same connection region. A semiconductor memory device characterized by the above-mentioned. 2. The memory capacitor according to claim 1, wherein a fin of the memory capacitor is interposed between a storage electrode of the memory capacitor in the uppermost layer and a counter electrode of the memory capacitor also serving as a shield electrode of the TFT load. The semiconductor memory device according to claim 1. 3. The storage electrode of the topmost memory capacitor has respective side surfaces within interconnect contact holes passing through the fins of the memory capacitor and the drain electrode of the TFT load and the gate electrode of the TFT load. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is in contact with the surface of the gate electrode or the drain of the lowermost driver transistor. 4. An insulating film made of silicon nitride between a counter electrode of a memory capacitor also serving as a shield electrode in the TFT load and a channel in the TFT load serves as a shield electrode in the TFT load. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a substantially same plane pattern as a counter electrode of the memory capacitor also serving as the counter electrode. 5. The semiconductor device according to claim 1, further comprising a counter electrode of a memory capacitor which also serves as a shield electrode of the TFT load to which a potential substantially equal to a source potential of the TFT load is applied. 5. The semiconductor memory device according to 4. 6. A step of forming a field insulating film on a surface of a semiconductor substrate and then forming a gate insulating film, and then patterning after growing a first conductive film to form a gate electrode of the driver transistor. Forming and then forming an impurity region by introducing impurities using the field insulating film and the gate electrode of the driver transistor as the first conductive film as a mask, and then forming a first insulating film. Then, a second conductive film that contacts the gate electrode or the drain of the driver transistor is grown and patterned to form a gate electrode of a TFT load, and then a gate insulating film as a second insulating film is formed. And then growing and selecting a semiconductor layer that is a third conductive film that is in contact with the gate electrode of the TFT load. Forming the source and drain regions and the channel region of the TFT load by performing appropriate impurity introduction and patterning, and then forming a film acting as an etching stopper, and then growing the film acting as a spacer, Growing a fourth conductive film that is in contact with the drain region of the TFT load, and then patterning the fourth conductive film to form a storage electrode of the memory capacitor; Removing the insulating film serving as the spacer, which is the base of the storage electrode; and
Forming a dielectric film for the memory capacitor covering the storage electrode of the memory capacitor, and then forming a counter electrode of the memory capacitor also serving as a shield electrode of a TFT load covering the dielectric film for the memory capacitor. And a method for manufacturing a semiconductor memory device. 7. An interconnect contact hole penetrating through the drain region of the TFT load and the gate electrode of the TFT load and reaching the surface of the gate electrode or drain of the transistor, and then forming the drain region of the TFT load and the TFT. The gate electrode of the load is the side exposed in the interconnect contact hole and the gate electrode or drain of the driver transistor is the surface of the memory capacitor contacting the exposed surface at the bottom of the interconnect contact hole, respectively. 7. The method according to claim 6, further comprising a step of forming a storage electrode. 8. A step of interposing a conductive film serving as a fin of a memory capacitor through a film serving as a spacer between a film serving as an etching stopper and a conductive film serving as a storage electrode of a memory capacitor. The method for manufacturing a semiconductor memory device according to claim 6, wherein the semiconductor memory device is included. 9. A method for patterning a film acting as an etching stopper with the same mask when patterning a conductive film to be a counter electrode of a memory capacitor also serving as a shield electrode of a TFT load. 9. The method for manufacturing a semiconductor memory device according to claim 6, wherein: