JP2923699B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a TFT (thin f
ilm transformer) load type SRAM (st
atic random access memory
The present invention relates to an improvement in a semiconductor memory device called y) and a method of manufacturing the same.

[0002] Until recently, SRAMs having a high resistance load have been widely used. However,
As the degree of integration increases and the number of memory cells increases, the current consumption increases and various problems occur.
An SRAM with a load of T has been realized. However, another new problem is caused by using the TFT as a load, and it is necessary to solve it.

[0003]

2. Description of the Related Art FIGS. 39 to 48 show a high resistance load type SRA.
FIG. 49 is a sectional view of a main part in a process step for explaining a conventional example of a method of manufacturing M. FIGS. 49 to 54 are views for explaining a conventional example of a method of manufacturing a high resistance load type SRAM. The main part plan view at the important points of the process is shown respectively,
Hereinafter, description will be made with reference to these figures. 39 to 48 are sectional views taken along the line Y-Y shown in FIG. 54 which is a plan view of the principal part.

FIG. 39 39- (1) For example, a silicon dioxide (SiO ₂ ) film is used as a pad film,
Selective thermal oxidation (eg, local) using a silicon nitride (Si ₃ N ₄ ) film laminated thereon as an oxidation resistant mask film
oxidation of silicon: LOC
By applying the (OS) method, the silicon semiconductor substrate 1
A field insulating film 2 made of SiO ₂ and having a thickness of, for example, 4000 [Å] is formed thereon. 39- (2) Si ₃ N ₄ film or SiO ₂ used for performing selective thermal oxidation
The active region in the silicon semiconductor substrate 1 is exposed by removing the film.

See FIGS. 40 and 49. 40- (1) A gate insulating film 3 made of SiO ₂ and having a thickness of, for example, 100 [Å] is formed by applying a thermal oxidation method. 40- (2) Contact hole 3A is formed by selectively etching gate insulating film 3 by applying a resist process in photolithography technology and a wet etching method using an etchant as hydrofluoric acid. I do.

Referring to FIGS. 41 and 49, 41- (1) chemical vapor deposition (chemical vapor deposition)
A first polycrystalline silicon film having a thickness of, for example, 1500 [Å] is formed by applying the position (CVD) method. 41- (2) By applying the gas phase diffusion method, for example, 1 × 10
²¹ [cm ^-3 ] of phosphorus (P) is introduced to form an n ⁺ -impurity region 5 '. In FIG. 49, the first polycrystalline silicon film is omitted for simplicity.

See FIGS. 42 and 50 42- (1) Reactive ion etching (reactive ion etc) using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
In this case, the gate electrode 4 is formed by patterning the first polycrystalline silicon film by applying the Hing (RIE) method. The gate electrode 4 is a word line and a gate electrode of a driver transistor. 42- (2) A dose amount of 3 × 1 is obtained by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ], acceleration energy 40 [keV], A
The source region 5 and the drain region 6 are formed by implanting s ions.

See FIGS. 43 and 50. 43- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] The insulating film 7 made of SiO ₂ is formed. 43- (2) Resist process in photolithography technology and RIE using CHF ₃ / He as an etching gas
Ground line contact hole 7 by applying the
Form A. The ground line contact hole 7A is not visible in FIG.

FIG. 44 and FIG. 51 44- (1) The thickness is, for example, 1500 by applying the CVD method.
[2] A second polycrystalline silicon film is formed. 44- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the second polycrystalline silicon film. 44- (3) The second polycrystalline silicon film is patterned by applying a resist process in the photolithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas to form a ground line. 8 is formed.

See FIGS. 45 and 51. 45- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] The insulating film 9 made of SiO ₂ is formed. 45- (2) The resist process in the photolithography technique and the RIE method using CHF ₃ / He as an etching gas are applied to selectively etch the insulating film 9 to provide a load resistance contact hole. 9A is formed.

See FIGS. 46 and 52. 46- (1) A thickness of, for example, 1500 by applying the CVD method.
[3] A third polycrystalline silicon film is formed. 46- (2) Applying a resist process and an ion implantation method in the photolithography technology to reduce the dose to 1
× 10 ¹⁵ [cm ^-2 ] and acceleration energy of 30 [ke]
V], As ions are implanted into a portion to be a supply line of the positive power supply voltage V _CC and a portion where the high resistance load contacts the gate electrode 4. 46- (3) A third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method in which an etching gas is CCl ₄ / O _2, and a contact portion is formed. 10. High resistance load 1
1. _Vcc supply line 12 is formed.

See FIGS. 47 and 52. 47- (1) By applying the CVD method, a thickness of, for example, 1000
[Å] an insulating film made of SiO ₂ and a thickness of, for example, 500
0 [Å] phospho-silicate glass (phospho-silicic glass)
a) (insulating glass: PS glass). In the drawing, the two layers of the insulating film are integrally shown, and this is referred to as an insulating film 13. 47- (2) A heat treatment for reflowing and planarizing the insulating film 13 is performed. 47- (3) Selective etching of the insulating film 13 and the like is performed by applying a resist process in photolithography technology and an RIE method using CHF ₃ / He as an etching gas to perform bit line contact. A hole 13A is formed.

See FIGS. 48 and 53. 48- (1) By applying the sputtering method, a thickness of, for example, 1
An [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 14. It should be noted that those not described with reference to the symbols shown in FIGS. 39 to 53, for example, BL and the like will become clear when compared with FIG. 55 described later.

FIG. 54 is a plan view of a principal part of a high resistance load type SRAM completed through the above-described steps. The same symbols as those used in FIGS. 39 to 53 represent the same parts or are the same. It has meaning. However, for the sake of simplicity, the bit lines made of Al shown in FIGS. 48 and 53 are removed in FIG.

FIG. 55 is a main part equivalent circuit diagram of the high resistance load type SRAM described with reference to FIGS. In the figure, Q1 and Q2 are driving transistors,
Q3 and Q4 are transfer gate transistors,
R1 and R2 are high resistance loads, WL is a word line, BL and / BL are bit lines, S1 and S2 are nodes, V _CC is a positive power supply voltage, and V _SS is a negative power supply voltage.

The operation in the high resistance load type SRAM,
In particular, storage is performed as follows.
Now, the positive power supply voltage V _CC = 5 [V], the negative power supply voltage V _SS =
0 [V], the node S1 = 5 [V],
Assuming that the node S2 = 0 [V], the transistor Q
2 is on, and transistor Q1 is off. At the node S1, the potential is maintained at 5 [V] when the transistor Q1 is off and the resistance value in that case is sufficiently higher than the high resistance load R1. At the node S2, when the transistor Q2 is on,
If the resistance value in this case is sufficiently lower than the high resistance load R2, the potential is maintained at 0 [V].

However, under the above conditions, the negative power supply voltage V _{SS is} supplied from the positive power supply voltage V _CC supply line side through the node S2.
A direct current flows on the supply line side, and its value is inversely proportional to the value of the high resistance load R2.

As the degree of integration of such a high resistance load type SRAM increases, the number of memory cells per chip increases. Therefore, unless the current consumption per memory cell is reduced, the current consumption of the entire chip increases. Would. Therefore, the DC current has to be reduced, and this requires increasing the values of the high resistance loads R2 and R1. However, when this resistance value is increased, it becomes difficult to stably maintain the potential at the node where the driving transistor is off, in the example described above, the node S1.

With the background described above, a TFT load type SRAM using a TFT instead of a high resistance has appeared.

Here, the TFT load type SRAM will be described. As in the case of the high resistance load type SRAM, first, the case of manufacturing the TFT load type SRAM will be described.

FIGS. 56 to 59 show a TFT load type SRAM.
FIGS. 60 to 63 are cutaway side views of main parts in key process steps for explaining a conventional example of a method of manufacturing a TFT.
Principal plan views at key process steps for explaining a conventional example of a method of manufacturing a load type SRAM are respectively shown. Hereinafter, description will be made with reference to these drawings. 56 to 59 are sectional views taken along a line Y-Y shown in FIG. 63 which is a plan view of a main part. The steps from 39- (1) to 45- (2), which are the steps for manufacturing the above-described high resistance load type SRAM, that is, the steps up to forming the load resistance contact hole 9A are as follows.
This is almost the same in the process of manufacturing this TFT load type SRAM. Only the ground line 8 made of the second polycrystalline silicon film is connected to the TFT made of the third polycrystalline silicon film. The only difference is that the gate electrode is formed with a contact hole 8A (see FIG. 60) necessary for making contact with the active region and the gate electrode 4 formed of the first polycrystalline silicon film. Therefore, it will be described from a subsequent stage. Needless to say, the same symbols as those used in FIGS. 39 to 55 represent the same parts or have the same meanings.

See FIGS. 56 and 60. 56- (1) The thickness is, for example, 1500 by applying the CVD method.
[3] A third polycrystalline silicon film is formed. 56- (2) A dose amount of 1 × 1 is obtained by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 20 [keV]
And implant P ions. 56- (3) A third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. The gate electrode 15 is formed.

Referring to FIG. 57, 57- (1) A gate insulating film 16 of TFT having a thickness of, for example, 300 [Å] made of SiO ₂ is formed by applying the CVD method. 57- (2) The gate insulating film 16 is selectively etched by applying a resist process in the photolithography technique and a wet etching method using an etchant as hydrofluoric acid to form a drain contact hole. 16
Form A.

See FIGS. 58 and 61. 58- (1) The thickness is, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 58- (2) Applying a resist process and an ion implantation method in the photolithography technology to reduce the dose to 1
× 10 ¹⁴ [cm ^-2 ] and acceleration energy of 5 [keV]
Then, B ions are implanted into a portion to be a source region and a drain region of the TFT and a portion to be a _Vcc supply line. 58- (3) The fourth polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. Source region 17, drain region 18, channel region 19, V _CC power level supply line 20
To form

See FIGS. 59 and 62. 59- (1) By applying the CVD method, a thickness of, for example, 1000
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. Also in this figure, as in FIGS. 47 and 48, two insulating films are integrally shown, and this is referred to as an insulating film 21. 59- (2) A heat treatment for reflowing and planarizing the insulating film 21 is performed. 59- (3) By selectively etching the insulating film 21 and the like by applying the resist process in the photolithography technology and the RIE method using CHF ₃ / He as an etching gas, Form a hole. 59- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed and is patterned by applying a normal photolithography technique to form a bit line 22. Note that those not described with reference to the symbols shown in FIGS. 56 to 62, such as BL, will be apparent from comparison with FIG. 64 described later.

FIG. 63 is a plan view of a principal part of the TFT load type SRAM completed through the above-described steps. The symbols used in FIGS. 39 to 62 represent the same parts or have the same meanings. Have However, for simplicity, the bit lines made of Al shown in FIGS. 59 and 62 are removed in FIG.

FIG. 64 is a main part equivalent circuit diagram of the TFT load type SRAM described with reference to FIGS. 56 to 63. 55 to 63 and FIG. 55 represent the same part or have the same meaning. In the figure, Q5 and Q6 indicate transistors which are load TFTs, respectively.

The operation in this TFT load type SRAM,
In particular, storage is performed as follows.

Now, the positive power supply voltage V _CC = 5 [V] and the negative power supply voltage V _SS = 0 [V] are set, respectively, and the node S1
= 5 [V] and the node S2 = 0 [V], the transistor Q2 is on and the transistor Q6 is off, and the transistor Q1 is off and the transistor Q5 is on. At the node S1, the potential is maintained at 5 [V] when the transistor Q1 is off and the resistance value in that case is sufficiently higher than the on state of the transistor Q5. At the node S2, the transistor Q2 is in the ON state, and the resistance value in that case is the transistor Q2.
If the potential is sufficiently low compared to the off state of No. 6, the potential becomes 0
[V] is maintained.

As described above, under the above conditions, the resistance value of the transistor Q5 or the transistor Q6, which is a load, changes according to the stored information.
The problem in M is solved, and stable information storage can be performed. The transistors Q5 and Q6 used here
The channel of the load TFT, that is, the channel in the load TFT is made of polycrystalline silicon, and its crystal state is much worse than that of a single crystal. Since the leakage current is the current consumption of the chip as it is, it is desirable to make it as small as possible.

By the way, as is apparent from FIG. 59, in this TFT load type SRAM, the uppermost layer has A
A bit line 22 made of an l film is provided, and a channel of a load TFT exists immediately below the bit line 22 via an insulating film 21 made of PSG or the like.

Such a structure can be regarded as a transistor having the bit line 22 made of an Al film as a gate electrode and the insulating film 21 thereunder as a gate insulating film. The potential of the line 22 is 0 [V]
(V _ss ) to 5 [V] (V _cc ), so that the TFT which should be in the off state, ie, the transistor Q6, is close to the on state, the leakage current increases, and the parasitic effect is remarkable. Become. In order to solve such a problem, a TFT with a double gate structure, which is an improved type of the TFT with load, has been developed.

This double gate structure TFT load type SRAM
Now, the fifth polycrystalline silicon film in the TFT load type SRAM described with reference to FIGS. 56 to 64, specifically, the fifth gate electrode having the same pattern as the gate electrode 15 of the TFT will be described. Of the polycrystalline silicon film of source region 17, drain region 18, channel region 19,
The above problem is solved by interposing between the fourth polycrystalline silicon film constituting the V _CC supply line 20 and the like and the bit line 22 made of Al.

FIGS. 65 to 67 show a double gate structure TFT.
FIGS. 2A and 2B are cut-away side views of essential parts at important steps in a process for explaining a conventional example of a method of manufacturing a load type SRAM, and will be described below with reference to these figures. The steps from 56- (1) to 58- (3), which are the steps for manufacturing the above-described TFT load type SRAM,
Source region 17, drain region 18, channel region 1
9. Since the steps up to the formation of the V _CC supply line 20 are almost the same in the steps of manufacturing this double gate structure TFT load type SRAM, they will be described from the subsequent steps. Needless to say, the same symbols as those used in FIGS. 39 to 64 represent the same parts or have the same meanings.

65- (1) An insulating film 23 made of SiO ₂ and having a thickness of, for example, 500 [Å] is formed by applying the CVD method. 65- (2) Fourth polycrystal by selectively etching insulating film 23 by applying a resist process in photolithography technology and an RIE method using CHF ₃ + He as an etching gas. A contact hole 23A for the silicon film is formed.

Referring to FIG. 66, 66- (1) The thickness is, for example, 1000 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 66- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 66- (3) The fifth polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. The second gate electrode 24 is formed.

Referring to FIG. 67, 67- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. Note that, also in this figure, as in FIG. 59, the two-layer insulating film is integrally shown, and this is referred to as an insulating film 25. 67- (2) A heat treatment for reflowing and flattening the insulating film 25 is performed. 67- (3) Selective etching of the insulating film 25 and the like is performed by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, and Form a hole. 67- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 26.

[0038]

As described above,
SRAM starts with a high resistance load type, a TFT load type,
It has progressed to a double gate structure TFT load type. However, first, FIGS. 39 to 48 (particularly, FIG. 48) and FIG.
67 (especially, FIG. 67), it should be clear that the double gate structure TF
In shifting to the T-load type SRAM, the number of polycrystalline silicon films has increased by two layers, and the number of mask steps has actually increased four times.

By the way, not only the SRAM as described above, but also "miniaturization" is the most important proposition in semiconductor memory devices. In recent years, the size of the SRAM has been remarkably reduced. Is causing problems.

In general, it is well known that a memory capacitor is required even for an SRAM. Usually, the memory capacitor includes a connection point between a driver transistor and a load, that is, a node and its connection. Utilizes nearby parasitic capacitance. Therefore, the capacity of the memory capacitor is the smallest in the high resistance load type SRAM, slightly increased in the TFT load type SRAM, and the largest in the double gate structure TFT load type SRAM.

However, even with the double gate structure TFT load type SRAM, as described above, as the miniaturization progresses, the capacity of the memory capacitor becomes insufficient. Therefore, instead of relying on the parasitic capacitance as described above, it is necessary to intentionally provide a separate memory capacitor. However, as described above, the number of mask steps is increasing. Therefore, it is necessary to minimize an increase in the number of steps in manufacturing a memory capacitor.

The present invention provides a structure in which the interconnection of a double gate structure TFT load and a driver transistor can be performed by the same contact hole, and a double gate structure T
The upper gate electrode of the FT load is used to form a memory capacitor, so that not only the parasitic capacitance but also the number of manufacturing steps in a double gate structure TFT load type SRAM having a separately provided memory capacitor is increased. Try to suppress.

In the semiconductor memory device according to the present invention, (1) a pair of transfer transistors, a pair of driver transistors, and a pair of double gate structure TFT loads, and a double gate structure TFT The storage electrode (for example, storage electrode 24) and the drain (for example, drain region 1) of the memory capacitor also serving as the upper gate electrode of the load
8) and lower gate electrode (for example, lower gate electrode 15)
And a gate electrode (e.g., gate electrode 4) or drain (e.g., n ⁺ -drain region 6) of the driver transistor having a connection region interconnected by a single contact hole. A memory cell having a counter electrode (for example, a counter electrode 28) laminated via a memory capacitor dielectric film (memory capacitor dielectric film 27) covering a storage electrode of a memory capacitor also serving as an upper gate electrode. Or

(2) In the above (1), in the connection region, at least the lower gate electrode, the drain and the upper gate electrode of the double gate structure TFT load are provided above the gate electrode or the drain of the driver transistor. The storage electrodes of the memory capacitors are respectively stacked via insulating films (for example, insulating films 7, 9, 16 and the like), and the storage electrodes of the memory capacitors in the upper layers are connected to the intermediate electrodes at the side surfaces thereof. Characterized by being connected to the lowermost layer and its surface, or

(3) In the above (1), the storage electrode of the memory capacitor has at least one fin (for example, the fin 30), and the lowermost fin serves as the upper gate electrode of the double gate structure TFT load. (4) In the above (1), there is provided a counter electrode to which a substantially intermediate potential between two voltage values corresponding to the storage state of the memory cell is applied. (5) In the above (3), the pattern seen in the plane of the fin which also serves as the storage electrode of the memory capacitor and the upper gate electrode of the double gate structure TFT load is substantially the same. (6) In the above (3) or (5), the fin serving also as the upper gate electrode of the double gate structure TFT load and the storage electrode of the memory capacitor are used. Between An insulating film (for example, an insulating film 79 acting as an etching stopper: see FIG. 37) which extends to the outside of the pattern of the electrodes and whose pattern when viewed in plan is substantially the same as the counter electrode is interposed. Characterized in that, or

(7) A step of forming a field insulating film (for example, field insulating film 2) on the surface of a semiconductor substrate (for example, silicon semiconductor substrate 1) and then forming a gate insulating film (for example, gate insulating film 3), Growing a first conductive film (eg, a first polycrystalline silicon film) and then patterning to form a gate electrode (eg, gate electrode 4) of the driver transistor;
Field insulating film and driver, which is the first conductive film
Impurity is introduced by using the gate electrode of the transistor as a mask and impurity regions (for example, n ⁺ -source region 5 and n ⁺
-Forming a first insulating film (for example, insulating film 7) after forming a drain region 6) and then growing and patterning a second conductive film (for example, third polycrystalline silicon film). To form a lower gate electrode (for example, lower gate electrode 15) of a double gate structure TFT load, and then a lower gate insulating film (for example, lower gate insulating film 6) as a second insulating film is formed. Process, and then growing a third conductive film (for example, a fourth polycrystalline silicon film) and selectively introducing impurities and patterning to form a double gate structure TF.
After forming a source region (for example, the source region 17), a drain region (for example, the drain region 18) and a channel region (for example, the channel region 19) of a T load, an upper gate insulating film (for example, the insulating film 23) which is a third insulating film. ), And then, from the upper gate insulating film and the drain region formed of the third conductive film as the third insulating film and the lower gate insulating film and the second conductive film as the second insulating film. The lower gate electrode and the first insulating film are selectively removed to remove the side surface of the drain region made of the third conductive film, the side surface of the lower gate electrode made of the second conductive film, and the first conductive film. Forming an interconnect contact hole exposing the surface of the gate electrode of the driver transistor (eg, interconnect contact hole 23A), and then forming a third conductive film. A fourth conductive film (for example, a fifth polycrystal) that contacts the side surface of the driver region, the side surface of the lower gate electrode made of the second conductive film, and the surface of the gate electrode of the driver transistor made of the first conductive film. Forming a silicon film) and patterning it to form a storage electrode (for example, storage electrode 24) of the memory capacitor; and then a dielectric film for the memory capacitor (for example, for the memory capacitor) covering the storage electrode of the memory capacitor the dielectric film 27) and SRAM and a process of forming a fifth conductive film (e.g., sixth polycrystalline silicon film) memory capacitor counter electrode consisting of a (e.g. the counter electrode 28) in this order
Is characterized by creating , or

(8) In the above (7), an insulating film (for example, an insulating film 29 made of Si ₃ N ₄₎ acting as an etching stopper instead of the upper gate insulating film as the _third insulating film. 7) and then the double gate structure T
A conductive film serving as a fin (for example, fin 30) and an insulating film (for example, SiO ₂ ) serving as a fin (for example, fin 30) in the upper gate electrode of the FT load and the storage electrode of the memory capacitor
Interconnect layers (eg, interconnect contact holes 31: see FIG. 7) after the insulating film 31 acting as a spacer made of GaAs is formed in order.
Then, the side surface of the conductive film serving as the fin, the side surface of the drain region (for example, the drain region 18) made of the third conductive film (for example, the fourth polycrystalline silicon film), and the second conductive film ( For example, a side surface of a lower gate electrode (for example, lower gate electrode 15) made of a third polycrystalline silicon film and a gate electrode (for a driver transistor) made of a first conductive film (for example, first polycrystalline silicon film). For example, a step of forming a fourth conductive film (for example, a sixth polycrystalline silicon film: see FIG. 8) in contact with the surface of the gate electrode 4), and then patterning the fourth conductive film to store a memory capacitor Patterning an insulating film serving as an electrode and a conductive film serving as a fin and a fin, and then etching the insulating film serving as a spacer with an etching stopper A dielectric film for a memory capacitor (e.g., a dielectric film for a memory capacitor) covering the surfaces of a storage electrode of a memory capacitor and a conductive film serving as a fin after the insulating film acting as a stopper is isotropically removed. 2
7), and then a counter electrode (for example, the counter electrode 2) of the memory capacitor facing the storage electrode of the memory capacitor via the memory capacitor dielectric film.
8) the step of forming; or

(9) In the above (8), the fins of the memory capacitor (for example, fins 80 and 89: FIG. 32)
(For example, a fifth polycrystalline silicon film and a fourth polycrystalline silicon film: see FIG. 30).
And an insulating film acting as a spacer (for example, insulating films 81 and 90: see FIG. 30) is interposed therebetween.
A later step of patterning them simultaneously with the formation of the storage electrodes of the memory capacitors (eg storage electrode 91: see FIG. 32), or

(10) In the above (8) or (9), a step of patterning the insulating film serving as an etching stopper at the same time as forming the counter electrode of the memory capacitor is included, or ,

(11) In the above (8), (9) or (10), the double gate structure TFT load is formed on the upper gate insulating film (for example, the insulating film 92: see FIGS. 35 and 36). The fin of the memory capacitor also serving as the upper gate electrode of the gate structure TFT load (for example,
3: See FIGS. 35 and 36), and then an insulating film (eg, insulating film 9) acting as an etching stopper
4: See FIGS. 35 and 36) and an insulating film acting as a spacer (for example, an insulating film 95 acting as a spacer):
35 and 36) are formed in order, and then an interconnect contact hole is formed. Thereafter, a side surface and a side surface of the fin of the memory capacitor also serving as the upper gate electrode of the double gate structure TFT load are formed. A storage electrode of a memory capacitor (for example, storage electrode 96: FIG. 35) that contacts the side surface of the drain region of the double gate structure TFT load, the side surface of the lower gate electrode of the double gate structure TFT load, and the surface of the gate electrode of the driver transistor. And FIG. 36)
Is formed.

[0051]

As is apparent from the above description, according to the present invention, the same contact hole is formed at the same place by interconnecting the gate electrode of the driver transistor, the gate electrode of the double gate structure TFT load, and the drain. Because of the configuration that can be connected by utilizing, a contact hole for interconnection between the driver transistor and the double gate structure TFT load can be formed only once. Because the memory capacitor is built using the upper gate electrode of the above, a radiation-resistant double gate TFT having a memory capacitor intentionally provided in addition to the parasitic capacitance is large.
A load type SRAM can be manufactured easily and easily with a small number of manufacturing steps with a high yield.

[0052]

1 to 6 illustrate a first embodiment of the present invention.
The main part cut-away side views of the RAM are shown, respectively, and will be described in detail below with reference to these figures. 39 to FIG.
8 is the same in the present embodiment from the beginning of the process of manufacturing the conventional high resistance load type SRAM described in FIG. 8 to the process 44- (2), that is, until the formation of the ground line 8 made of the second polycrystalline silicon film. Therefore, the description will be omitted, and description will be made from the next stage.

Referring to FIG. 1, 1- (1) Here, a double gate structure TFT load type SRAM is composed of a silicon semiconductor substrate 1 having a field insulating film 2, a gate insulating film 3, and a first polycrystalline silicon film. Transistor gate electrode 4, n ⁺ -impurity region 5 ', n ⁺ -
It is assumed that a source line 5, an n ⁺ -drain region 6, an insulating film 7, and a ground line 8 made of a second polycrystalline silicon film are formed. 1- (2) Thickness, for example, 1000 by applying the CVD method
[Å] An insulating film 9 made of SiO ₂ is formed on the entire surface. 1- (3) The thickness is, for example, 500 by applying the CVD method.
[3] A third polycrystalline silicon film is formed. 1- (4) The dose amount is 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 10 [keV]
And implant P ions. 1- (5) The third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. The lower gate electrode 15 is formed.

FIG. 2 2- (1) Lower gate insulating film 1 of TFT having a thickness of, for example, 200 [例 え ば] made of SiO ₂ by applying the CVD method.
6 is formed. 2- (2) The thickness is, for example, 200 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 2- (3) By applying a resist process and an ion implantation method in photolithography technology, the dose amount is reduced to 1
× 10 ¹⁴ [cm ^-2 ] and acceleration energy of 5 [keV]
Then, B ions are implanted into portions to be the source and drain regions of the TFT. 2- (4) The fourth polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. A source region 17, a drain region 18, a channel region 19, and a V _CC power level supply line (not shown in the drawing) are formed.

Referring to FIG. 3, 3- (1) the thickness is, for example, 500 by applying the CVD method.
[Å] The insulating film 23 made of SiO ₂ is formed. 3- (2) to the photolithography technique in the resist process and an etching gas CHF ₃ / the He (for SiO ₂₎
By applying the RIE method with CCl ₄ / O ₂ (for polycrystalline silicon), the insulating film 23, the drain region 18 of the TFT load which is the fourth polycrystalline silicon film, the gate insulating film 16, the third Gate electrode 1 which is a polycrystalline silicon film
5, the insulating film 9 and the insulating film 7 are selectively etched to form an interconnect contact hole 23A reaching from the surface to the gate electrode 4 of the driving transistor made of the first polycrystalline silicon film. This step is one of the major features of the present invention.

FIG. 4 4- (1) The thickness is, for example, 2000 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 4- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 4- (3) The fifth polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method in which an etching gas is CCl ₄ / O ₂ , thereby performing TFT loading. Is formed as the upper gate electrode and storage electrode 24 of the memory capacitor.

FIG. 5 5- (1) By applying the CVD method, the surface of the storage electrode 24 of the upper gate electrode of the TFT load and the memory capacitor is formed by applying the CVD method.
A dielectric film 27 for memory capacitor having a thickness of, for example, 100 [Å] made of i ₃ N ₄ is formed. 5- (2) The thickness is, for example, 1000 by applying the CVD method.
[6] A sixth polycrystalline silicon film is formed. 5- (3) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film. 5- (4) RIE using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
The patterning of the sixth polycrystalline silicon film is performed by applying the method to form the counter electrode 28 of the memory capacitor.
To form The provision of the counter electrode 28 is also a major feature of the present invention.

FIG. 6 6- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. In this figure, as in FIGS. 48, 59, and 67, two layers of the insulating film are integrally shown, and this is referred to as an insulating film 25. 6- (2) A heat treatment is performed to reflow and planarize the insulating film 25. 6- (3) Selective etching of the insulating film 25 and the like is performed by applying a resist process in photolithography technology and an RIE method using CHF ₃ / He as an etching gas to perform bit line contact. Form a hole. 6- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 26.

As can be seen from the above description, FIG.
In the embodiment described with reference to FIGS. 6 to 6, the mask step is increased once to form the counter electrode 28. However, as described in the step 3- (2), the TFT and the driver
Contact hole 23A for connecting transistors etc.
Are formed in a single mask process, so that the number of mask processes is reduced by twice as compared with the conventional example described with reference to FIGS. 65 to 67. Compared to the example, the number of mask steps is reduced by one.

FIGS. 7 to 11 are cutaway side views of a main part of a double gate structure TFT load type SRAM at a process point for explaining a second embodiment of the present invention. This will be described in detail with reference to the drawings. Note that, from the beginning of the process in the first embodiment described with reference to FIGS. 1 to 6 to the process 2- (4), that is, the source region 17 and the drain region 18 of the TFT made of the fourth polycrystalline silicon film. This is the same in the present embodiment until the channel region 19 is formed. Therefore, the description will be omitted and the following steps will be described.

7- (1) Here, a double gate structure TFT load type SRAM is composed of a silicon semiconductor substrate 1, a field insulating film 2, a gate insulating film 3, and a driver comprising a first polycrystalline silicon film. Transistor gate electrode 4, n ⁺ -impurity region 5 ', n ⁺ -
A source region 5, an n ⁺ -drain region 6, an insulating film 7, a ground line 8 made of a second polycrystalline silicon film, a gate electrode 15 of a TFT made of a third polycrystalline silicon film, a gate insulating film 16 of the TFT, TF made of fourth polycrystalline silicon film
It is assumed that a source region 17, a drain region 18, and a channel region 19 of T are formed. 7- (2) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 29 made of Si ₃ N ₄ is formed on the entire surface. 7- (3) The thickness is, for example, 500 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 7- (4) The dose amount is set to 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 10 [keV]
And implant P ions. 7- (5) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 31 serving as a spacer made of SiO ₂ is formed on the entire surface. 7- (6) CHF ₃ / He (for SiO ₂ ) using resist process and etching gas in photolithography technology
, A fifth polycrystalline silicon film, an insulating film 29, and a fourth polycrystalline silicon film that act as spacers by applying the RIE method with CCl ₄ / O ₂ (for polycrystalline silicon). The drain region 18 of the TFT load,
The gate insulating film 16, the gate electrode 15, which is a third polycrystalline silicon film, the insulating film 9, and the insulating film 7, are selectively etched to form a gate electrode 4 of a driving transistor composed of the first polycrystalline silicon film from the surface. Is formed to reach the interconnect contact hole 31A.

FIG. 8 8- (1) The thickness is, for example, 500 by applying the CVD method.
[6] A sixth polycrystalline silicon film is formed. 8- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film. 8- (3) Applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for SiO ₂ ) as an etching gas. Accordingly, the sixth polycrystalline silicon film, the insulating film 31, and the fifth polycrystalline silicon film are patterned to form the storage electrode 24 of the memory capacitor and the memory capacitor also serving as the upper gate electrode of the double gate structure TFT load. Fins 30 are formed.

9- (1) The insulating film 31 made of SiO ₂ is removed by dipping in an aqueous HF solution.

10- (1) By applying the CVD method, the surface of the storage electrode 24 of the memory capacitor and the surface of the fin 30 of the memory capacitor have a thickness of, for example, 100 [Å] made of Si ₃ N _4. Is formed. 10- (2) The thickness is, for example, 500 by applying the CVD method.
[7] A seventh polycrystalline silicon film is formed. 10- (3) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the seventh polycrystalline silicon film. 10- (4) RIE using CCl ₄ / O ₂ as a resist process and etching gas in photolithography technology
By applying the method, the seventh polycrystalline silicon film is patterned to form the counter electrode 28 of the memory capacitor.
To form

Referring to FIG. 11, 11- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. Note that, also in this figure, as in FIG. 6, two layers of the insulating film are integrally shown, and this is referred to as an insulating film 25. 11- (2) A heat treatment for reflowing and flattening the insulating film 25 is performed. 11- (3) Selective etching of the insulating film 25 and the like is performed by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, and Form a hole. 11- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 26.

As can be seen from the above description, FIG.
In the embodiment described with reference to FIGS.
Compared with the embodiment described above, since the storage electrode 24 of the memory capacitor is provided with the fin 30 also serving as the upper gate electrode in addition to the double gate structure TFT load, the total number of fins becomes two, and The capacitance of the capacitor increases. No matter how many fins are added, the mask process is the same as that of the embodiment described with reference to FIGS. Further, the voltage applied to at the counter electrode 28 in the memory capacitor may be any anything (V) within the positive supply level V _CC, the voltage applied to the dielectric film when the 1 / 2V _CC is small Therefore, the thickness of the dielectric film can be reduced, and the capacitance can be increased.

FIG. 12 is a plan view of a principal part of a TFT load type SRAM realized by the present inventors. In the figure,
41 is a TFT gate, 42 is a TFT channel, 43
Indicates a word line, and V _CC indicates a positive power supply level. This SRAM has an advantage that the symmetry of driver transistors and TFTs is good, and therefore the layout is easy. Next, an embodiment in which the present invention is applied to the TFT load type SRAM will be described. Will be described.

FIGS. 13 to 22 are cutaway side views of a principal part of a double gate structure TFT load type SRAM at a process point for explaining a third embodiment of the present invention, and FIGS. The main part plan views of the double gate structure TFT load type SRAM at the key points of the process for explaining the same embodiment are respectively shown, and the details will be described below with reference to these figures. FIGS. 13 to 22 correspond to the line X shown in FIG.
FIG. 23 is a sectional side view taken along a line −X, and FIGS. 23 to 29 are exploded views of the TFT load type SRAM shown in FIG. 12 for each process step. These figures will be referred to at any time during the process described with reference to FIGS.

13, 23 and 24 13- (1) Pad film made of SiO ₂ covering the active region of silicon semiconductor substrate 51 and Si ₃ N laminated on the pad film
By utilizing the oxidation-resistant mask film consisting of ₄ depending on applying a selective thermal oxidation method, thickness of, for example, 4 made of SiO ₂
A field insulating film 52 of 000 [Å] is formed. 13- (2) After removing the oxidation-resistant mask film and the pad film to expose the active region, and applying the thermal oxidation method, SiO ₂
The gate insulating film 53 having a thickness of, for example, 100 [Å] is formed. 13- (3) Selective etching of the gate insulating film 53 is also performed for impurity diffusion by applying a resist process in photolithography technology and a wet etching method using an etchant as hydrofluoric acid. contact·
A hole 53A is formed. 13- (4) Thickness, for example, 1000 by applying the CVD method
[Å] First polycrystalline silicon film is formed. 13- (5) The n ⁺ -impurity region 54 is formed by introducing P at an impurity concentration of, for example, 1 × 10 ²⁰ [cm ⁻³ ] by applying the vapor phase diffusion method. 13- (6) The first polycrystalline silicon film is patterned by applying a resist process in photolithography and an RIE method using CCl ₄ + O ₂ as an etching gas to form a gate electrode 55. And 56 are formed. 13- (7) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ], and the acceleration energy is set to 30.
[KeV] is implanted with As ions to obtain n ⁺ −
A source region 57 and an n ⁺ -drain region 58 are formed.

See FIGS. 14 and 25. 14- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] An insulating film 59 made of SiO ₂ is formed.

14- (2) The thickness is, for example, 1000 by applying the CVD method.
[Å] A second polycrystalline silicon film is formed. 14- (3) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ] and the second polycrystalline silicon film
Introduce. 14- (3) By applying a resist process in photolithography technology and an RIE method in which an etching gas is CCl ₄ / O ₂ , a second polycrystalline silicon film is patterned to form a TFT. The lower gate electrode 61 and the like are formed.

See FIGS. 15 and 26. 15- (1) The thickness is, for example, 200 by applying the CVD method.
[Å] An insulating film 62 made of SiO ₂ is formed. 15- (2) A thickness of, for example, 200
[3] A third polycrystalline silicon film is formed. 15- (3) depending on the applying in resist process and an ion implantation method in the photo-lithography technique, a source region and a drain region of the in TFT in the third polycrystalline silicon film, a V _CC supply line 1 × 10 ¹⁴ dose for power
[Cm ⁻² ], and B is implanted with an acceleration energy of 5 [keV]. 15- (4) A third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. Then, a drain region, a source region, a channel region, and a _Vcc supply line of each TFT are formed. In the figure, the contact portion 64 and the channel region 6 are shown.
7 appears.

See FIGS. 16 and 26. 16- (1) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 79 made of Si ₃ N ₄ is formed.

17 and 26. 17- (1) The thickness is, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 17- (2) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ], and the fourth polysilicon film is
Introduce. 17- (3) A thickness of, for example, 500
[Å] An insulating film 81 made of SiO ₂ is formed. 17- (4) RIE using CHF ₃ / He (for SiO ₂ and Si ₃ N ₄ ) and CCl ₄ / O ₂ (for polycrystalline silicon) as resist process and etching gas in photolithography technology By applying the method, the insulating film 8
1, a fourth polycrystalline silicon film, an insulating film 79, a third polycrystalline silicon film, an insulating film 62, a second polycrystalline silicon film,
The insulating film 59 is selectively etched to form an interconnect contact hole 81A reaching from the surface to the gate electrode of the driving transistor which is the first polycrystalline silicon film.

See FIG. 18. 18- (1) The thickness is, for example, 500 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 8- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film.

19- (1) A resist process and an etching gas in the photolithography technique are CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for SiO ₂ ). By applying the RIE method, the fifth polycrystalline silicon film, the insulating film 81, and the fourth polycrystalline silicon film are patterned to form the upper gate electrode of the TFT and the storage electrode 82 of the memory capacitor, Form the fins 80 of the memory capacitors.

20- (1) The insulating film 81 made of SiO ₂ is removed by immersion in an aqueous HF solution.

See FIGS. 21 and 28. 21- (1) By applying the CVD method, the fin 80 of the memory capacitor serving also as the storage electrode 82 of the memory capacitor and the upper gate electrode of the double gate structure TFT load. A dielectric film 83 for a memory capacitor having a thickness of, for example, 100 [Å] made of Si ₃ N ₄ is formed on the surface of the substrate. 21- (2) Thickness of, for example, 1000 by applying the CVD method
[6] A sixth polycrystalline silicon film is formed. 21- (3) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film. 21- (4) RIE using CCl ₄ / O ₂ as a resist process and etching gas in photolithography technology
By applying the method, the sixth polycrystalline silicon film is patterned to form the counter electrode 84 of the memory capacitor.
To form

See FIGS. 22, 28 and 29. 22- (1) By applying the CVD method, a thickness of, for example, 1000
[Å] An insulating film 85 made of SiO ₂ is formed. 22- (2) The resist process in the photolithography technology and the RIE method in which the etching gas is CHF ₃ / He are applied to selectively etch the insulating film 85 and the like to form the ground line contact. A hole 85A is formed. 22- (3) Thickness, for example, 1000 by applying the CVD method
[7] A seventh polycrystalline silicon film is formed. 22- (4) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the seventh polycrystalline silicon film. 22- (5) RIE Using CCl ₄ / O ₂ as a Resist Process and Etching Gas in Photolithography Technology
Depending on applying the law, to form a V _SS power level supply line 86 by patterning of the seventh polycrystalline silicon film. 22- (6) Thickness, for example, 1000 by applying the CVD method
[Å] SiO _{2 and} 5000 [例 え ば] P
An insulating film 87 made of SG is formed. 22- (7) A heat treatment for reflowing and flattening the insulating film 87 is performed. 22- (8) RI using resist process and etching gas such as CCl ₄ / O _{2 in} photolithography technology
By applying the E method, a bit line contact hole (not visible in the figure) is formed by selectively etching the insulating film 87 and the like. 22- (9) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 88.

FIGS. 30 to 32 are cutaway side views of a main part of a double gate structure TFT load type SRAM at a process point for explaining a fourth embodiment of the present invention.
The details will be described with reference to these figures. Note that the same applies to the present embodiment from the beginning of the process in the third embodiment described with reference to FIGS. 13 to 22 to the process 16- (1), that is, until the formation of the insulating film 79 made of Si ₃ N _4. Therefore, the description will be omitted, and description will be made from the next stage.

Referring to FIG. 30 30- (1) Here, a double gate structure TFT load type SRAM has a field insulating film 52, a gate insulating film 53, an n ⁺ -impurity region 54, Gate electrode 5 of driver transistor made of crystalline silicon film
5, n ⁺ -source region 57, n ⁺ -drain region 58,
An insulating film 59, a gate electrode 61 of the TFT made of the second polycrystalline silicon film, a gate insulating film 62 of the TFT, a source region (not shown) of the TFT made of the third polycrystalline silicon film, and a contact region of the drain It is assumed that the insulating film 79 made of Si ₃ N ₄ and the like are formed. 30- (2) The thickness is, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 30- (3) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ], and the fourth polysilicon film is
Introduce. 30- (4) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 81 made of SiO ₂ is formed. 30- (5) The thickness is, for example, 500 by applying the CVD method.
The fifth polycrystalline silicon film of [Å] is formed. 30- (3) By applying the gas phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ], and the fifth polycrystalline silicon film is doped with P.
Introduce. 30- (4) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 90 made of SiO ₂ is formed. 30- (5) RIE using CHF ₃ / He (for SiO ₂ and Si ₃ N ₄ ) and CCl ₄ / O ₂ (for polycrystalline silicon) as resist process and etching gas in photolithography technology By applying the method, the insulating film 9
0, a fifth polycrystalline silicon film, an insulating film 81, a fourth polycrystalline silicon film, an insulating film 79, a third polycrystalline silicon film,
The insulating film 62, the second polycrystalline silicon film, and the insulating film 59 are selectively etched to form an interconnect contact hole 90A extending from the surface to the gate electrode of the driving transistor, which is the first polycrystalline silicon film. .

FIG. 31 31- (1) The thickness is, for example, 500 by applying the CVD method.
[6] A sixth polycrystalline silicon film is formed. 31- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film.

Referring to FIG. 32, 32- (1) RIE using CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for SiO ₂ ) as a resist process and an etching gas in photolithography technology By applying the method, the sixth polycrystalline silicon film, the insulating film 90, the fifth polycrystalline silicon film, the insulating film 81, and the fourth polycrystalline silicon film are patterned to form the storage electrode of the memory capacitor. 80, fin 8 of the memory capacitor
9. Form the fin 90 of the memory capacitor also serving as the upper gate electrode of the double gate structure TFT load. 32- (2) The insulating films 90 and 81 made of SiO ₂ are removed by immersion in an aqueous HF solution. 32- (3) Thereafter, steps such as formation of a dielectric film for a memory capacitor, which are the same as steps 21- (1) in the third embodiment described with reference to FIGS. good.

The embodiment described with reference to FIGS. 30 to 32 is different from the embodiment described with reference to FIGS. 13 to 22 in that the fin integrated with the storage electrode of the memory capacitor is formed without increasing the number of mask steps. Are substantially three, so that the capacity of the memory capacitor is greatly increased. As described above, the number of fins which directly affects the capacitance value of the memory capacitor can be arbitrarily increased without requiring an extra masking step.

FIG. 33 to FIG. 36 are cutaway side views of a main part of a double gate structure TFT load type SRAM at a process point for explaining a fifth embodiment of the present invention.
The details will be described with reference to these figures. It should be noted that, from the beginning of the steps in the third embodiment described with reference to FIGS. 13 to 22 to step 15- (1), that is, by patterning the third polycrystalline silicon film, the contact portion and each TF
This is the same in this embodiment until the drain region, source region, channel region, _Vcc supply line, and the like of T are formed.

33- (1) Here, in the double gate structure TFT load type SRAM, a field insulating film 52, a gate insulating film 53, an n ⁺ -impurity region 54, a first multiple Gate electrode 5 of driver transistor made of crystalline silicon film
5, n ⁺ -source region 57, n ⁺ -drain region 58,
An insulating film 59, a gate electrode 61 of the TFT made of a second polycrystalline silicon film, a gate insulating film 62 of the TFT, a source region and a drain region, a channel region, and a _Vcc supply line of the TFT made of a third polycrystalline silicon film; And the like are formed. 33- (2) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 92 made of SiO ₂ is formed. 33- (3) By applying the CVD method, a thickness of, for example, 500
[4] A fourth polycrystalline silicon film is formed. 33- (4) By applying the gas phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ] and the fourth polycrystalline silicon film
Introduce. 33- (5) By applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ (for polycrystalline silicon) as an etching gas, a fourth polycrystalline silicon film is formed. Patterning is performed to form fins 93 also serving as upper gate electrodes of the double gate structure TFT load.

See FIG. 34. 34- (1) By applying the CVD method, a thickness of, for example, 500
[Å] An insulating film 94 made of Si ₃ N ₄ and an insulating film 95 made of SiO _{2 having a} thickness of, for example, 500 [Å] are sequentially formed. 34- (2) CHF ₃ / He (for SiO ₂ and Si ₃ N ₄ ) and CCl ₄ / O ₂ (for polycrystalline silicon)
, The insulating films 95 and 94, the fourth polycrystalline silicon film, the insulating film 92, the third polycrystalline silicon film, the insulating film 62, the second polycrystalline silicon film, The film 59 is selectively etched to form an interconnect contact hole 95A reaching the gate electrode of the driving transistor, which is the first polycrystalline silicon film, from the surface.

See FIG. 35. 35- (1) By applying the CVD method, a thickness of, for example, 500
[5] A fifth polycrystalline silicon film is formed. 35- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 35- (3) RIE using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
By applying the fifth method, the fifth polycrystalline silicon film is patterned to form the storage electrode 96 of the memory capacitor.
To form

Referring to FIG. 36, 36- (1) The insulating film 95 made of SiO ₂ is removed by immersion in an aqueous HF solution. 36- (2) Thereafter, steps such as formation of a dielectric film for a memory capacitor, which are the same as steps 21- (1) in the third embodiment described with reference to FIGS. good.

The fifth embodiment described with reference to FIGS. 33 to 36 is different from the fifth embodiment described with reference to FIGS. 13 to 22 in that the fin and memory capacitor of the gate electrode and memory capacitor on the upper side of the double gate structure TFT load are used. -The configuration of the storage electrode of the capacitor has been modified. Usually, when etching a polycrystalline silicon film, it is advantageous to use SiO ₂ as a base as an etching stopper because the underlayer is made of SiO ₃ rather than Si ₃ N _4, which is advantageous as an etching stopper. There is an advantage that the storage electrode can be easily formed. However, since the upper gate electrode of the double gate structure TFT load and the storage electrode of the memory capacitor are separately patterned, the number of mask steps is increased once. Therefore, it can be realized by the same unchanged mask process.

FIGS. 37 and 38 show a double gate structure TFT at a key point in the process for explaining the sixth embodiment of the present invention.
The cut-away side view of the main part of the load type SRAM is shown, respectively, and the details will be described below with reference to these figures. FIG.
3 to FIG. 22, the same applies to the present embodiment from the beginning of the process in the third embodiment described above with reference to FIG. 22 to the process 20- (1), that is, until the insulating film 81 is removed. It will be described from the stage.

[0092] Figure 37 Referring 37- (1), where the double gate structure TFT load type SRAM, the field insulating film 52 on the silicon semiconductor substrate 51, a gate insulating film 53, n ⁺ - doped region 54, the first multi Gate electrode 5 of driver transistor made of crystalline silicon film
5, n ⁺ -source region 57, n ⁺ -drain region 58,
An insulating film 59, a lower gate electrode 61 of a TFT load made of a second polycrystalline silicon film, and a gate insulating film 6 of the TFT load
2. The source, drain and channel regions of the TFT load composed of the third polycrystalline silicon film, the _Vcc power supply level supply line, the insulating film 79 acting as an etching stopper composed of Si ₃ N _4, and the upper side of the TFT load. Fin 80 of the memory capacitor also serving as the gate electrode,
It is assumed that the storage electrode 82 and the like of the capacitor have been formed, and the insulating film 81 has been removed. 37- (2) depending on applying a CVD method, consisting of Si ₃ N ₄ to a memory capacitor surface of the storage electrode 82 and the double-gate structure TFT load memory capacitor of the fin 80 which also serves as an upper gate electrode of the A memory capacitor dielectric film 83 having a thickness of, for example, 100 [１００] is formed. 37- (3) Thickness, for example, 1000 by applying the CVD method
[6] A sixth polycrystalline silicon film is formed. 37- (4) P of, for example, 1 × 10 ²¹ [cm ⁻³ ] is diffused into the sixth polycrystalline silicon film by applying the thermal diffusion method. 37- (5) RIE using CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for Si ₃ N ₄ ) as resist process and etching gas in photolithography technology
By applying the method, the sixth polycrystalline silicon film is patterned to form the counter electrode 84 of the memory capacitor.
Then, the insulating film 79 serving as an etching stopper made of Si ₃ N ₄ is selectively removed using the same mask.

38- (1) Thickness of, for example, 1000 by applying the CVD method
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. Note that, also in this figure, as in FIGS. 6 and 11, two layers of the insulating film are integrally shown, and this is referred to as an insulating film 85. 38- (2) A heat treatment for reflowing and planarizing the insulating film 85 is performed. 38- (3) Selective etching of the insulating film 85 and the like is performed by applying a resist process in photolithography technology and an RIE method using CHF ₃ / He as an etching gas to perform ground line contact. Form a hole. 38- (4) Thickness, for example, 1000 by applying the CVD method
[7] A seventh polycrystalline silicon film is formed. 38- (5) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the seventh polycrystalline silicon film. 38- (6) RIE Using Resist Process and Etching Gas as CCl ₄ / O _{2 in} Photolithography Technology
Depending on applying the law, to form a V _SS power level supply line 86 by patterning of the seventh polycrystalline silicon film. 38- (7) By applying the CVD method, a thickness of, for example, 5000
[Å] BPSG (borophosphosilic)
An insulating film 87 made of a glass material is formed. 38- (8) A heat treatment for reflowing and planarizing the insulating film 87 is performed. 38- (9) RI in which resist process and etching gas in photolithography technology are CCl ₄ / O ₂ or the like
By applying the E method, a bit line contact hole (not visible in the figure) is formed by selectively etching the insulating film 87 and the like. 38- (10) Thickness, for example, 1 by applying a sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 88.

In the sixth embodiment described with reference to FIGS. 37 and 38, the source region (not shown) of the transfer transistor has A
Very good results are obtained when the bit line 88 made of 1 is brought into contact. That is, the step 38-
As described in (9), a bit line contact hole is formed in a place that cannot be seen in the figure. In this case, a PSG film is formed above the insulating film 79 made of Si ₃ N _4. However, it is necessary to etch the portion where the SiO ₂ film is laminated on the lower side, and remove the resist mask with oxygen plasma or the like. However, at this time, since a natural oxide film is formed at the bottom of the bit line contact hole, it must be removed by hydrofluoric acid treatment before forming the Al bit line 88. In such a case, the insulating film 79 made of Si ₃ N ₄ is not affected much, but the PSG film and the SiO ₂ film are etched, and the hole diameter at that portion is increased. Therefore, Si ₃ N ₄
Only the insulating film 79 made of GaN protrudes into the bit line contact hole, and if an Al film is formed there, disconnection will occur. However, in the sixth embodiment, since the insulating film 79 made of Si ₃ N ₄ is patterned at the stage of forming the counter electrode 84 of the memory capacitor, the above-described problem does not occur. Since the insulating film 79 made of Si ₃ N ₄ is removed by using the same mask as that of the counter electrode 84, the number of mask steps does not increase.

[0095]

In the semiconductor memory device and the method of manufacturing the same according to the present invention, a pair of transfer transistors, a pair of driver transistors, and a pair of double gate structures TF are provided.
Double gate structure TFT including T load
The storage electrode and the drain of the memory capacitor also serving as the upper gate electrode of the load, and the connection area where the lower gate electrode and the gate electrode or the drain of the driver transistor are mutually connected, and the upper side of the double gate structure TFT load A memory cell having a counter electrode laminated via a memory capacitor dielectric film covering a storage electrode of the memory capacitor also serving as a gate electrode is provided.

As is apparent from the above description, according to the present invention, the same contact hole is formed at the same place by interconnecting the gate electrode of the driver transistor, the gate electrode of the double gate structure TFT load, and the drain. Because the configuration allows connection by using the driver,
The contact hole for interconnecting the transistor and the double-gate TFT load only needs to be formed once, and the upper gate electrode of the double-gate TFT load is used to build the memory capacitor. In this way, a double gate structure TFT load type SRAM having a large radiation resistance and having a memory capacitor intentionally provided in addition to a parasitic capacitance can be easily and easily manufactured with a high yield with a small number of manufacturing steps. You can now.

[Brief description of the drawings]

FIG. 1 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a first embodiment of the present invention.

FIG. 2 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a first embodiment of the present invention.

FIG. 3 is a cutaway side view of a main part of a double-gate-structure TFT-load type SRAM at an important part of a process for explaining a first embodiment of the present invention;

FIG. 4 is a cutaway side view of a main part of the double gate structure TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 5 is a cutaway side view of a main part of a double-gate-structure TFT-loaded SRAM at an important point in the process for explaining the first embodiment of the present invention;

FIG. 6 is a cutaway side view of a main portion of a double gate structure TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 7 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part of a double-gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 9 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a second embodiment of the present invention.

FIG. 10 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a second embodiment of the present invention.

FIG. 11 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a second embodiment of the present invention.

FIG. 12 shows a TFT load type SRA realized by the present inventors.
It is a principal part top view of M.

FIG. 13 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 14 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 15 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 16 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 17 is a fragmentary side view of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 18 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a third embodiment of the present invention.

FIG. 19 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 20 is a fragmentary side elevational view of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 21 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 22 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention.

FIG. 23 is a plan view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a third embodiment of the present invention.

FIG. 24 is a plan view of a main portion of a double gate structure TFT load type SRAM at a main point of a process for explaining a third embodiment of the present invention.

FIG. 25 is a plan view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 26 is a plan view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 27 is a plan view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 28 is a plan view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 29 is a plan view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 30 is a fragmentary side elevational view of a double gate structure TFT load type SRAM at an important part of a process for explaining a fourth embodiment of the present invention;

FIG. 31 is a side sectional view of a main part of a double gate structure TFT load type SRAM at an important part of a process for explaining a fourth embodiment of the present invention;

FIG. 32 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 33 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a fifth embodiment of the present invention;

FIG. 34 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a fifth embodiment of the present invention;

FIG. 35 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a fifth embodiment of the present invention;

FIG. 36 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a fifth embodiment of the present invention;

FIG. 37 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in the process for explaining the sixth embodiment of the present invention;

FIG. 38 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a sixth embodiment of the present invention;

FIG. 39 is a fragmentary sectional side view at a key step of the process for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 40 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 41 is a sectional side view of a relevant part in a process key for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 42 is a cross-sectional side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 43 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM;

FIG. 44 is a cross-sectional side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 45 is a cross-sectional side view of a main part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 46 is a cutaway side view of a relevant part at a process key point for describing a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 47 is a fragmentary side elevational view at a key step in the process for explaining a conventional example of a method of manufacturing a high resistance load type SRAM;

FIG. 48 is a cross-sectional side view of a relevant part at a process key point for describing a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 49 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM in a process key point;

FIG. 50 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a key point in a process;

FIG. 51 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a process essential point;

FIG. 52 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a key step;

FIG. 53 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a key point in a process;

FIG. 54 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high-resistance load type SRAM;

FIG. 55 is a main part equivalent circuit diagram of a high resistance load type SRAM.

FIG. 56 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 57 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 58 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 59 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 60 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM in a relevant part of a process;

FIG. 61 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM at an important point in a process;

FIG. 62 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM in a relevant part of a process;

FIG. 63 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM in a process key point;

FIG. 64 is a main part equivalent circuit diagram of a TFT load type SRAM.

FIG. 65 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a double gate structure TFT load type SRAM.

FIG. 66 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a double gate structure TFT load type SRAM.

FIG. 67 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a double gate structure TFT load type SRAM.

[Explanation of symbols]

Reference Signs List 1 silicon semiconductor substrate 2 field insulating film 3 gate insulating film 3A contact hole 4 gate electrode 5 source region 5 'impurity region 6 drain region 7 insulating film 8 ground line 9 insulating film 15 lower gate electrode 16 lower gate insulating film 16A Contact hole 17 Source region 18 Drain region 19 Channel region 23 Insulating film 23A Interconnecting contact hole 24 Upper gate electrode of double gate structure TFT and storage electrode of memory capacitor 25 Insulating film 26 Bit line 27 For memory capacitor Dielectric film 28 Counter electrode of memory capacitor

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/8244 H01L 21/822 H01L 27/04 H01L 27/11 H01L 29/786

Claims (11)

(57) [Claims] 1. A storage capacitor comprising a pair of transfer transistors, a pair of driver transistors, and a pair of double gate structure TFT loads, and also serving as an upper gate electrode of the double gate structure TFT load. Single contact between electrode and drain, lower gate electrode and driver transistor gate electrode or drain
A counter electrode laminated with a dielectric film for a memory capacitor covering a storage electrode of a memory capacitor having a connection region interconnected by holes and also serving as an upper gate electrode of a TFT load having a double gate structure. A semiconductor memory device comprising a memory cell having the same. 2. In the connection region, at least a lower gate electrode, a drain and a storage electrode of a memory capacitor serving also as an upper gate electrode of a double gate structure TFT load are insulated above a gate electrode or a drain of a driver transistor. 2. The storage electrode of a memory capacitor which is stacked via a film and which is in an upper layer is connected to an intermediate electrode on a side surface thereof and is connected to a lowermost layer on a surface thereof. The semiconductor memory device according to claim 1. 3. The semiconductor device according to claim 1, wherein the storage electrode of the memory capacitor has at least one fin, and the lowermost fin also functions as the upper gate electrode of the double gate structure TFT load. Storage device. 4. The semiconductor memory device according to claim 1, further comprising a counter electrode to which a substantially intermediate potential between two voltage values corresponding to a storage state of the memory cell is applied. 5. The semiconductor memory device according to claim 3, wherein the pattern as viewed in the plane of the fin which also serves as the storage electrode of the memory capacitor and the upper gate electrode of the double gate structure TFT load is substantially the same. . 6. A pattern extending between a fin also serving as an upper gate electrode of a double gate structure TFT load and a storage electrode of a memory capacitor and extending outside the pattern of the electrodes and viewed in a plane. 6. The semiconductor memory device according to claim 3, wherein an insulating film substantially the same as the counter electrode is interposed. 7. A step of forming a field insulating film on a surface of a semiconductor substrate and then forming a gate insulating film, and then patterning after growing a first conductive film to form a gate electrode of the driver transistor. Forming a first insulating film after forming an impurity region by introducing an impurity using a gate electrode of a driver transistor as a field insulating film and a first conductive film as a mask, and then forming a first insulating film; Next, a step of growing and patterning a second conductive film to form a lower gate electrode of a double gate structure TFT load, and then forming a lower gate insulating film as a second insulating film; A third conductive film is grown and selectively doped with impurities and patterned to form a source region, a drain region and a channel region of a double-gate TFT load. Forming an upper gate insulating film, which is a third insulating film, and then forming a third insulating film, an upper gate insulating film and a drain region composed of a third conductive film, and a second insulating film And selectively removing the lower gate electrode and the first insulating film made of the lower gate insulating film and the second conductive film, and removing the side surface of the drain region made of the third conductive film and the second conductive film. A driver comprising a side surface of a lower gate electrode and a first conductive film.
Forming an interconnect contact hole exposing the surface of the gate electrode of the transistor; then, forming a side surface of the driver region made of the third conductive film, a side surface of the lower gate electrode made of the second conductive film, Forming a fourth conductive film in contact with the surface of the gate electrode of the driver transistor made of one conductive film, and then patterning it to form a storage electrode of the memory capacitor; and then covering the storage electrode of the memory capacitor memory·
And a process of forming a dielectric film and a memory capacitor counter electrode consisting of a fifth conductive film capacitor in order
A method for manufacturing a semiconductor memory device, comprising forming an SRAM . 8. An upper gate electrode of a double-gate TFT and a storage electrode of a memory capacitor after an insulating film acting as an etching stopper is formed in place of the upper gate insulating film as the third insulating film. Forming a conductive film serving as a fin and an insulating film serving as a spacer in this order, and then forming an interconnect contact hole, and then forming a side surface of the conductive film serving as a fin and a drain region formed of a third conductive film The side surface of the lower gate electrode made of the second conductive film and the side surface of the first conductive film
Forming a fourth conductive film in contact with the surface of the gate electrode of the transistor, and then patterning the fourth conductive film to serve as a storage electrode of the memory capacitor and a conductive film serving as an insulating film and a fin serving as a spacer; A step of patterning the film, and then isotropically removing the insulating film acting as a spacer using the insulating film acting as an etching stopper as a stopper, and then forming a conductive film serving as a storage electrode and a fin of a memory capacitor. Forming a dielectric film for the memory capacitor covering the surface, and then forming the storage electrode of the memory capacitor and the memory capacitor;
8. The method of manufacturing a semiconductor memory device according to claim 7, further comprising the step of: forming a counter electrode of a memory capacitor facing the capacitor dielectric film. 9. A method of manufacturing a memory capacitor, comprising the steps of: growing a plurality of conductive films serving as fins of a memory capacitor by interposing insulating films acting as spacers; 9. The method according to claim 8 , further comprising the step of patterning. 10. The semiconductor memory device according to claim 8, further comprising a step of simultaneously patterning the insulating film serving as an etching stopper when forming the counter electrode of the memory capacitor. Production method. 11. A fin of a memory capacitor also serving as an upper gate electrode of a double gate structure TFT load on an upper gate insulating film of a double gate structure TFT load, and then an insulating film acting as an etching stopper And an insulating film acting as a spacer are formed in order, and then an interconnect contact hole is formed. Thereafter, the memory gate serving also as the upper gate electrode of the double gate structure TFT load is formed.
Side and double gate structure TF in capacitor fin
Forming a storage electrode of a memory capacitor in contact with the side surface of the drain region of the T load, the side surface of the lower gate electrode of the double gate structure TFT load, and the surface of the gate electrode of the driver transistor. The method of manufacturing a semiconductor memory device according to claim 8, wherein the method comprises: