JP2887623B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a TFT (thin f
ilm transformer) load type SRAM (st
atic random access memory
The present invention relates to an improvement in a semiconductor memory device called y) and a method of manufacturing the same.

[0002] Until recently, SRAMs having a high resistance load have been widely used. However,
As the degree of integration increases and the number of memory cells increases, the current consumption increases and various problems occur.
An SRAM with a load of T has been realized. However, another new problem is caused by using the TFT as a load, and it is necessary to solve it.

[0003]

2. Description of the Related Art FIGS. 33 to 42 show a high resistance load type SRA.
FIGS. 43 to 48 are views for explaining a conventional example of a method of manufacturing a high-resistance load type SRAM. FIG. 43 to FIG. 48 are views for explaining a conventional example of a method of manufacturing a high resistance load type SRAM. The main part plan view at the important points of the process is shown respectively,
Hereinafter, description will be made with reference to these figures. Note that the main part cut-away side views of FIGS. 33 to 42 are cut planes along the line YY shown in FIG. 48 which is a main part plan view.

See FIGS. 33 and 43. 33- (1) For example, a silicon dioxide (SiO ₂ ) film is used as a pad film,
Selective thermal oxidation (eg, local) using a silicon nitride (Si ₃ N ₄ ) film laminated thereon as an oxidation resistant mask film
oxidation of silicon: LOC
By applying the (OS) method, the silicon semiconductor substrate 1
A field insulating film 2 made of SiO ₂ and having a thickness of, for example, 4000 [Å] is formed thereon. 33- (2) Si ₃ N ₄ film or SiO ₂ used for performing selective thermal oxidation
The active region in the silicon semiconductor substrate 1 is exposed by removing the film.

See FIGS. 34 and 43. 34- (1) A gate insulating film 3 made of SiO ₂ and having a thickness of, for example, 100 [例 え ば] is formed by applying a thermal oxidation method. 34- (2) Forming contact hole 3A by performing selective etching of gate insulating film 3 by applying a resist process in photolithography technology and a wet etching method using an etchant as hydrofluoric acid I do.

See FIGS. 35 and 43. 35- (1) Chemical vapor deposition
A first polycrystalline silicon film having a thickness of, for example, 1500 [Å] is formed by applying the position (CVD) method. 35- (2) By applying the gas phase diffusion method, for example, 1 × 10
²¹ [cm ^-3 ] of phosphorus (P) is introduced to form an n ⁺ -impurity region 5 '. In FIG. 43, the first polycrystalline silicon film is omitted for simplicity.

See FIGS. 36 and 44. 36- (1) Reactive ion etching (reactive ion etc) using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
In this case, the gate electrode 4 is formed by patterning the first polycrystalline silicon film by applying the Hing (RIE) method. The gate electrode 4 is a word line and a gate electrode of a driver transistor. 36- (2) A dose amount of 3 × 1 is obtained by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ], acceleration energy 40 [keV], A
The source region 5 and the drain region 6 are formed by implanting s ions.

FIG. 37 and FIG. 44 37- (1) A thickness of, for example, 1000 by applying the CVD method.
[Å] The insulating film 7 made of SiO ₂ is formed. 37- (2) Resist Process in Photolithography Technology and RIE Using CHF ₃ / He as Etching Gas
Ground line contact hole 7 by applying the
Form A. The ground line contact hole 7A is not visible in FIG.

38- (1) 38- (1) The thickness is, for example, 1500 by applying the CVD method.
[2] A second polycrystalline silicon film is formed. 38- (2) By applying a resist process in photolithography technology and an RIE method in which an etching gas is CCl ₄ / O ₂ , a second polycrystalline silicon film is patterned and a ground line is formed. 8 is formed.

See FIGS. 39 and 45. 39- (1) A thickness of, for example, 1000 by applying the CVD method.
[Å] The insulating film 9 made of SiO ₂ is formed. 39- (2) The resist process in the photolithography technique and the application of the RIE method using CHF ₃ / He as an etching gas are performed to selectively etch the insulating film 9 and to provide a load resistance contact hole. 9A is formed.

See FIGS. 40 and 46. 40- (1) The thickness is, for example, 1500 by applying the CVD method.
[3] A third polycrystalline silicon film is formed. 40- (2) Applying a resist process and an ion implantation method in the photolithography technology to reduce the dose to 1
× 10 ¹⁵ [cm ^-2 ] and acceleration energy of 30 [ke]
V], As ions are implanted into a portion to be a supply line of the positive power supply voltage V _CC and a portion where the high resistance load contacts the gate electrode 4. 40- (3) A third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method in which an etching gas is CCl ₄ / O _2, and a contact portion is formed. 10. High resistance load 1
1. _Vcc supply line 12 is formed.

See FIGS. 41 and 46. 41- (1) A thickness of, for example, 1000 by applying the CVD method.
[Å] an insulating film made of SiO ₂ and a thickness of, for example, 500
0 [Å] phospho-silicate glass (phospho-silicic glass)
a) (insulating glass: PS glass). In the drawing, the two layers of the insulating film are integrally shown, and this is referred to as an insulating film 13. 41- (2) A heat treatment for reflowing and planarizing the insulating film 13 is performed. 41- (3) Selective etching of the insulating film 13 and the like is performed by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, and A hole 13A is formed.

See FIGS. 42 and 47. 42- (1) By applying the sputtering method, a thickness of, for example, 1
An [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 14. Note that those not described with reference to the symbols described in FIGS. 33 to 47, such as BL, will be apparent from comparison with FIG. 49 described later.

FIG. 48 is a plan view of a main part of a high resistance load type SRAM completed through the above-described steps. The same symbols as those used in FIGS. It has meaning. However, for simplicity, the bit lines made of Al shown in FIGS. 42 and 47 are removed in FIG.

FIG. 49 is an equivalent circuit diagram of a main part of the high resistance load type SRAM described with reference to FIGS. In the figure, Q1 and Q2 are driving transistors,
Q3 and Q4 are transfer gate transistors,
R1 and R2 are high resistance loads, WL is a word line, BL and / BL are bit lines, S1 and S2 are nodes, V _CC is a positive power supply voltage, and V _SS is a negative power supply voltage.

The operation in the high resistance load type SRAM,
In particular, storage is performed as follows.
Now, the positive power supply voltage V _CC = 5 [V], the negative power supply voltage V _SS =
0 [V], the node S1 = 5 [V],
Assuming that the node S2 = 0 [V], the transistor Q
2 is on, and transistor Q1 is off. At the node S1, the potential is maintained at 5 [V] when the transistor Q1 is off and the resistance value in that case is sufficiently higher than the high resistance load R1. At the node S2, when the transistor Q2 is on,
If the resistance value in this case is sufficiently lower than the high resistance load R2, the potential is maintained at 0 [V].

However, under the above conditions, the negative power supply voltage V _{SS is} supplied from the positive power supply voltage V _CC supply line side through the node S2.
A direct current flows on the supply line side, and its value is inversely proportional to the value of the high resistance load R2.

As the degree of integration of such a high resistance load type SRAM increases, the number of memory cells per chip increases. Therefore, unless the current consumption per memory cell is reduced, the current consumption of the entire chip increases. Would. Therefore, the DC current has to be reduced, and this requires increasing the values of the high resistance loads R2 and R1. However, when the resistance value is increased, it becomes difficult to stably maintain the potential at the node on the side where the driving transistor is turned off, in the example described above.

With the background described above, a TFT load type SRAM using a TFT instead of a high resistance has appeared.

Here, the TFT load type SRAM will be described. As in the case of the high resistance load type SRAM, first, the case of manufacturing the TFT load type SRAM will be described.

FIGS. 50 to 53 show a TFT load type SRAM.
FIGS. 54 to 57 are cut-away side views of essential parts in important process steps for explaining a conventional example of a method of manufacturing a TFT.
Principal plan views at key process steps for explaining a conventional example of a method of manufacturing a load type SRAM are respectively shown. Hereinafter, description will be made with reference to these drawings. Note that the main part cut-away side views of FIGS. 50 to 53 are taken along a line YY shown in FIG. 57 which is a main part plan view. The steps from 33- (1) to 39- (2), which are the steps for manufacturing the above-described high resistance load type SRAM, that is, the steps up to forming the load resistance contact hole 9A are as follows.
This is almost the same in the process of manufacturing this TFT load type SRAM. Only the ground line 8 made of the second polycrystalline silicon film is connected to the TFT made of the third polycrystalline silicon film. The only difference is that the gate electrode is formed with an opening 8A (see FIG. 54) necessary for making contact with the active region and the gate electrode 4 made of the first polycrystalline silicon film. It will be described from a later stage. Needless to say, the same symbols as those used in FIGS. 33 to 49 represent the same parts or have the same meanings.

See FIGS. 50 and 54. 50- (1) The thickness is, for example, 1500 by applying the CVD method.
[3] A third polycrystalline silicon film is formed. 50- (2) By applying the ion implantation method, the dose amount is set to 1 × 1
0 ¹⁵ [cm ^-2 ] and acceleration energy 20 [keV]
And implant P ions. 50- (3) The third polycrystalline silicon film is patterned by applying a resist process in the photolithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas. The gate electrode 15 is formed.

Referring to FIGS. 51 and 54, 51- (1) A gate insulating film 16 of TFT having a thickness of, for example, 300 [Å] made of SiO ₂ is formed by applying the CVD method. 51- (2) Selective etching of the gate insulating film 16 is performed by applying a resist process in photolithography technology and a wet etching method using hydrofluoric acid as an etchant to form a drain contact hole. 16
Form A.

See FIGS. 52 and 55. 52- (1) The thickness is, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 52- (2) Applying a resist process and an ion implantation method in the photolithography technology to reduce the dose to 1
× 10 ¹⁴ [cm ^-2 ] and acceleration energy of 5 [keV]
Then, B ions are implanted into a portion to be a source region and a drain region of the TFT and a portion to be a _Vcc supply line. 52- (3) By applying a resist process in photolithography technology and an RIE method in which an etching gas is CCl ₄ / O ₂ , a fourth polycrystalline silicon film is patterned to form a TFT. A source region 17, a drain region 18, a channel region 19, and a V _CC supply line 20 are formed.

See FIGS. 53 and 56. 53- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. In this figure, as in FIGS. 41 and 42, two layers of the insulating film are integrally shown, and this is referred to as an insulating film 21. 53- (2) A heat treatment for reflowing and planarizing the insulating film 21 is performed. 53- (3) Selective etching of the insulating film 21 and the like is performed by applying a resist process in photolithography technology and an RIE method using CHF ₃ / He as an etching gas to perform bit line contact. Form a hole. 53- (4) The thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed and is patterned by applying a normal photolithography technique to form a bit line 22. Those not described with reference to the symbols shown in FIGS. 50 to 56, such as BL, will be apparent from comparison with FIG. 58 described later.

FIG. 57 is a plan view of a principal part of the TFT load type SRAM completed through the above-described steps. The same symbols as used in FIGS. 33 to 56 represent the same parts or have the same meanings. Have However, for simplicity, the bit lines made of Al shown in FIGS. 53 and 56 are removed in FIG.

FIG. 58 is a main part equivalent circuit diagram of the TFT load type SRAM described with reference to FIGS. It is to be noted that the same symbols as those used in FIGS. 50 to 57 and FIG. 49 represent the same portions or have the same meanings. In the figure, Q5 and Q6 indicate transistors which are load TFTs, respectively.

The operation in this TFT load type SRAM,
In particular, storage is performed as follows.

Now, the positive power supply voltage V _CC = 5 [V] and the negative power supply voltage V _SS = 0 [V] are set, respectively, and the node S1
= 5 [V] and the node S2 = 0 [V], the transistor Q2 is on and the transistor Q6 is off, and the transistor Q1 is off and the transistor Q5 is on. At the node S1, the potential is maintained at 5 [V] when the transistor Q1 is off and the resistance value in that case is sufficiently higher than the on state of the transistor Q5. At the node S2, the transistor Q2 is in the ON state, and the resistance value in that case is the transistor Q2.
If the potential is sufficiently low compared to the off state of No. 6, the potential becomes 0
[V] is maintained.

As described above, under the above conditions, the resistance value of the transistor Q5 or the transistor Q6, which is a load, changes according to the stored information.
The problem in M is solved, and stable information storage can be performed. The transistors Q5 and Q6 used here
The channel of the load TFT, that is, the channel in the load TFT is made of polycrystalline silicon, and its crystal state is much worse than that of a single crystal. Since the leakage current is the current consumption of the chip as it is, it is desirable to make it as small as possible.

By the way, as is apparent from FIG. 53, in this TFT load type SRAM, A
A bit line 22 made of an l film is provided, and a channel of a load TFT exists immediately below the bit line 22 via an insulating film 21 made of PSG or the like.

Such a structure can be regarded as a transistor having the bit line 22 made of an Al film as a gate electrode and the insulating film 21 thereunder as a gate insulating film. The potential of the line 22 is 0 [V]
(V _ss ) to 5 [V] (V _cc ), so that the TFT which should be in the off state, ie, the transistor Q6, is close to the on state, the leakage current increases, and the parasitic effect is remarkable. Become. In order to solve such a problem, a TFT with a double gate structure, which is an improved type of the TFT with load, has been developed.

This double gate structure TFT load type SRAM
Now, the third polycrystalline silicon film in the TFT load type SRAM described with reference to FIGS. 50 to 58, specifically, the fifth gate electrode having the same pattern as the gate electrode 15 of the TFT is formed. Of the polycrystalline silicon film of source region 17, drain region 18, channel region 19,
The above problem is solved by interposing between the fourth polycrystalline silicon film constituting the V _CC supply line 20 and the like and the bit line 22 made of Al.

FIGS. 59 to 61 show TFTs having a double gate structure.
FIGS. 2A and 2B are cut-away side views of essential parts at important steps in a process for explaining a conventional example of a method of manufacturing a load type SRAM, and will be described below with reference to these figures. The steps from 50- (1) to 52- (3), which are the steps for manufacturing the above-described TFT load type SRAM,
Source region 17, drain region 18, channel region 1
9. Since the steps up to the formation of the V _CC supply line 20 are almost the same in the steps of manufacturing this double gate structure TFT load type SRAM, they will be described from the subsequent steps. Needless to say, the same symbols as those used in FIGS. 33 to 58 represent the same parts or have the same meanings.

59- (1) An insulating film 23 made of SiO ₂ and having a thickness of, for example, 500 [Å] is formed by applying the CVD method. 59- (2) The fourth polycrystal is formed by selectively etching the insulating film 23 by applying a resist process in photolithography and an RIE method using CHF ₃ + He as an etching gas. A contact hole 23A for the silicon film is formed.

Referring to FIG. 60, 60- (1) The thickness is, for example, 1000 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 60- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 60- (3) The fifth polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method in which an etching gas is CCl ₄ / O ₂ . The second gate electrode 24 is formed.

Referring to FIG. 61, a thickness of, for example, 1000 is obtained by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. In this figure, as in FIG. 53, two insulating films are integrally shown, and this is referred to as an insulating film 25. 61- (2) A heat treatment for reflowing and flattening the insulating film 25 is performed. 61- (3) Selective etching of the insulating film 25 and the like is performed by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, and Form a hole. 61- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 26.

[0038]

As described above,
SRAM starts with a high resistance load type, a TFT load type,
It has progressed to a double gate structure TFT load type. However, first, FIGS. 33 to 42 (particularly, FIG. 42) and FIG.
61 (especially, FIG. 61), it should be clear that the high resistance load type SRAM can be replaced with the double gate structure TF.
In the transition to the T-load type SRAM, the number of polycrystalline silicon films has increased by two layers, and the number of mask steps has actually increased four times.

By the way, not only the SRAM as described above, but also "miniaturization" is the most important proposition in semiconductor memory devices. In recent years, the size of the SRAM has been remarkably reduced. Is causing problems.

It is well known that a memory capacitor is necessary even for an SRAM. Generally, the memory capacitor includes a parasitic capacitance near a node between a driver transistor and a load. We are using. Therefore, the capacity of the memory capacitor is
High resistance load type SRAM is the smallest and TFT load type SR
AM slightly increased, double gate structure TFT load type SR
AM is the largest.

However, even with the double gate structure TFT load type SRAM, as described above, as the miniaturization progresses, the capacity of the memory capacitor becomes insufficient.

Therefore, instead of relying on the parasitic capacitance as described above, it is necessary to intentionally provide a separate memory capacitor. However, as described above, the number of mask steps is increased. Therefore, it is necessary to minimize the increase in the number of steps when fabricating a memory capacitor.

The present invention provides a structure in which the interconnection of the double gate structure TFT load and the driver transistor can be performed by the same contact hole, and the common electrode of the memory capacitor and the ground line ( _VSS power supply line). Double gate structure TFT load type SRA having not only parasitic capacitance but also separately provided memory capacitor
An attempt is made to suppress an increase in the number of steps when manufacturing M.

[0044]

In a semiconductor memory device according to the present invention, (1) a pair of driver transistors and a pair of driver transistors formed on a semiconductor substrate (for example, a silicon semiconductor substrate 1) to constitute a flip-flop circuit; A pair of double gate structure TFT loads formed on a semiconductor layer (for example, a third polycrystalline silicon film: FIG. 2) on the semiconductor substrate and a memory capacitor formed above the double gate structure TFT load And a drain (for example, drain region 18) of a double gate structure TFT load and upper and lower gate electrodes (for example, upper gate electrode 30, lower gate electrode 1).
5) a memory cell having a connection region where a gate (for example, a gate electrode 4) or a drain (for example, an n ⁺ -drain region 6) of a driver transistor is connected to each other; The TFT load includes a lower gate electrode connected to the drain of the driver transistor, a channel formed on the lower gate electrode via a lower gate insulating film (for example, a lower gate insulating film 16), and a TFT on the channel. An upper gate electrode formed via an upper gate insulating film (eg, upper gate insulating film 29), and the memory capacitor is a storage electrode (eg, storage electrode 24 of the memory capacitor) and a memory covering the storage electrode. A capacitor dielectric film (for example, a memory capacitor dielectric film 27) and the memory
A counter electrode facing the storage electrode via a capacitor dielectric film and also serving as a ground line connected to the source of the driver transistor (for example, a counter electrode serving also as a ground line). Or,

(2) In the above (1), in the connection region, at least the drain and upper and lower gate electrodes of the double gate structure TFT load and the gate electrode or the drain of the driver transistor are each an insulating film (for example, the insulating film 2).
9, 16, 7, etc.) and a memory
The storage electrode of the capacitor is connected on the side surface of the intermediate electrode and is connected on the surface to the gate or drain of the driver transistor constituting the flip-flop circuit, or

(3) In the above (1) or (2),
(4) The upper gate electrode in the double gate structure TFT load is covered with a dielectric film for a memory capacitor and also serves as a fin of the memory capacitor. In (2), at least one fin of the memory capacitor (for example, fin 89: FIG. 28) is provided between the upper gate electrode of the double gate structure TFT load also serving as the fin of the memory capacitor and the storage electrode of the memory capacitor. ) Is interposed and connected to the storage electrode of the memory capacitor, or

(5) In the above (1) or (2),
Double gate structure T also serving as fin of memory capacitor
An upper gate insulating film, which is a base of the upper gate electrode of the FT load, is formed thicker than a dielectric film for a memory capacitor; or

(6) In the above (1) or (2),
An upper gate insulating film (for example, an upper gate insulating film 29) between a channel of a double gate structure TFT load and an upper gate electrode is made of a silicon nitride film acting as an etching stopper; or

(7) A step of forming a field insulating film (for example, field insulating film 2) on the surface of a semiconductor substrate (for example, silicon semiconductor substrate 1) and then forming a gate insulating film (for example, gate insulating film 3), Growing a first conductive film (eg, a first polycrystalline silicon film) and then patterning to form a gate electrode (eg, gate electrode 4) of the driver transistor;
Impurity is introduced by using the field insulating film and the gate electrode of the driver transistor as the first conductive film as a mask to form impurity regions (for example, n ⁺ -source region 5 and n ⁺ -drain region 6). To form a first insulating film (for example, insulating film 7), and then grow and pattern a second conductive film (for example, second polycrystalline silicon film: FIG. 1) to obtain a double gate TFT. Forming a lower gate electrode (for example, lower gate electrode 15) of the load, and then forming a lower gate insulating film (for example, lower gate insulating film 16) as a second insulating film; A conductive film (eg, a third polycrystalline silicon film: FIG. 2) is grown and selectively doped with impurities and patterned to form a source region (eg, source region 17) and a drain of a TFT load having a double gate structure. Down area (for example, the drain region 18)
A step of forming an upper gate insulating film (eg, upper gate insulating film 29) as a third insulating film after forming a channel region (eg, channel region 19), and then forming a fourth conductive film (eg, fourth Growing the fourth insulating film after growing the polycrystalline silicon film of FIG. 3), and then forming the fourth insulating film, the fourth conductive film, and the third insulating film on the upper side. A drain region composed of a gate insulating film and the third conductive film, and a lower gate insulating film that is the second insulating film and a lower gate electrode composed of the second conductive film and the first insulating film are selected. The fourth conductive film, the side surface of the drain region made of the third conductive film, the side surface of the lower gate electrode made of the second conductive film, and the first conductive film. Driver transistor gate electrode Interconnect contact hole exposing a surface (e.g., interconnection contact holes 31
Forming step (A), and then, the side surface of the fourth conductive film, the side surface of the drain region formed of the third conductive film, the side surface of the lower gate electrode formed of the second conductive film, and the first conductive film. Forming a fifth conductive film (for example, a fifth polycrystalline silicon film: FIG. 5) in contact with the surface of the gate electrode of the driver transistor composed of the fifth conductive film and the fourth insulating film Patterning the film and the fourth conductive film to form a storage electrode of a memory capacitor (for example, a memory
A step of forming an upper gate electrode (for example, an upper gate electrode 30) of a double gate structure TFT load which also serves as a storage electrode 24 of a capacitor and a fin of a memory capacitor and an insulating film acting as a spacer; Forming a memory capacitor dielectric film (for example, a memory capacitor dielectric film 27) covering the storage electrode and the upper gate electrode of the double gate structure TFT load, and then corresponding to the source of the driver transistor. After forming a ground line contact hole, a counter electrode of a memory capacitor (for example, a memory that also serves as a ground line) also serving as a ground line composed of a sixth conductive film (for example, a sixth polycrystalline silicon film: FIG. 7) Forming a counter electrode 28) of the capacitor.

(8) In the above (7), at least one layer serving as a fin of a memory capacitor is formed by interposing an insulating film serving as the spacer on the upper gate electrode of the double gate structure TFT load. A conductive film (for example, a conductive film serving as a fin 89 of a memory capacitor: FIG. 2)
And 8) simultaneously forming a storage electrode of a memory capacitor made of the fifth conductive film after the growth of the fifth conductive film.

(9) In the above (7), the upper gate insulating film (for example, the upper gate insulating film 29 made of a silicon nitride film) of the double gate structure TFT load made of a silicon nitride film is used as an etching stopper. Patterning a storage electrode of a memory capacitor, an insulating film acting as the spacer, and an upper gate electrode of the double gate structure TFT load, or

(10) In the above (7), the conductive film is patterned to form the upper gate electrode of the double gate structure TFT load, and then the storage electrode of the memory capacitor (for example, the storage electrode of the memory capacitor) 96), a step of sequentially forming a silicon nitride film (for example, insulating film 94: FIG. 30) serving as an etching stopper and an insulating film (for example, insulating film 95: FIG. 30) serving as a spacer are included. It is characterized by the following.

[0053]

As is apparent from the above description, according to the present invention, the same contact hole is formed at the same place by interconnecting the gate electrode of the driver transistor, the gate electrode of the double gate structure TFT load, and the drain. In order to improve the radiation resistance, the contact hole for interconnection between the driver transistor and the double-gate structure TFT load needs to be formed only once. Although a memory capacitor is provided separately, the configuration is such that the common electrode and the ground line of the memory capacitor can be shared, so that a double-gate TFT having a memory capacitor in addition to the parasitic capacitance is provided. A load type SRAM can be manufactured easily and easily with a small number of manufacturing steps with a high yield.

[0054]

1 to 8 show a first embodiment of the present invention.
9 to 14 show main part cutaway side views of the SRAM, and FIGS. 9 to 14 show main part plan views of the SRAM shown in FIGS. 1 to 8, respectively, and will be described below with reference to these drawings. still,
1 to 8 are plan views of main parts.
4 is taken along a line Y-Y,
Further, from the beginning of the process of manufacturing the conventional high resistance load type SRAM described with reference to FIGS.
The process up to (2), that is, the process up to the formation of the source region 5 and the drain region 6 is the same in the present embodiment, so that the description will be omitted and the following steps will be described.

1 and FIG. 9 1- (1) Here, the double gate structure TFT load type SRAM comprises a silicon semiconductor substrate 1 having a field insulating film 2, a gate insulating film 3, and a first polycrystalline silicon film. Gate electrode 4, n ⁺ -impurity region 5 ', n ⁺ -
It is assumed that the source region 5 and the n ⁺ -drain region 6 are formed. 1- (2) Thickness, for example, 1000 by applying the CVD method
[Å] The insulating film 7 made of SiO ₂ is formed. 1- (3) The thickness is, for example, 500 by applying the CVD method.
[2] A second polycrystalline silicon film is formed. 1- (4) The dose amount is 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 10 [keV]
And implant P ions. 1- (5) By applying a resist process in photolithography technology and an RIE method in which an etching gas is CCl ₄ / O ₂ , a second polycrystalline silicon film is patterned to form a TFT. The lower gate electrode 15 is formed.

2- (1) 2- (1) Lower gate insulating film 1 made of SiO ₂ and having a thickness of, for example, 200 [２００] TFT by applying the CVD method.
6 is formed. 2- (2) The thickness is, for example, 200 by applying the CVD method.
[3] A third polycrystalline silicon film is formed. 2- (3) By applying a resist process and an ion implantation method in photolithography technology, the dose amount is reduced to 1
× 10 ¹⁴ [cm ^-2 ] and acceleration energy of 5 [keV]
Then, B ions are implanted into portions to be the source and drain regions of the TFT. 2- (4) The third polycrystalline silicon film is patterned by applying a resist process in the photolithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas. A source region 17, a drain region 18, a channel region 19, and a _VCC power level supply line (see FIG. 10) are formed.

FIG. 3 3- (2) The thickness is, for example, 500 by applying the CVD method.
[Å] An upper gate insulating film 29 of the TFT which also functions as an etching stopper made of Si ₃ N ₄ is formed on the entire surface. 3- (3) The thickness is, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 3- (4) The dose is 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ^-2 ] and acceleration energy 10 [keV]
And implant P ions. 3- (5) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 31 serving as a spacer made of SiO ₂ is formed on the entire surface. 4- (1) The resist process and the etching gas in the photolithography technique are CHF ₃ / He (for SiO ₂ and Si ₃ N ₄ ) and CCl ₄ / O ₂ (polycrystalline). By applying the RIE method (for silicon), an insulating film 31 acting as a spacer, a fourth polycrystalline silicon film, an upper gate insulating film 29 of a TFT also acting as an etching stopper, and a third polycrystalline film TFT made of silicon film
Drain region 18, lower gate insulating film 16, lower gate electrode 15 made of second polycrystalline silicon film, insulating film 7
Are selectively etched to form an interconnect contact hole 31A reaching the gate electrode 4 of the driving transistor made of the first polycrystalline silicon film from the surface.

See FIGS. 5 and 11. 5- (1) The thickness is, for example, 500 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 5- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 5- (3) Applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for SiO ₂ ) as an etching gas. Accordingly, the fifth polycrystalline silicon film, the insulating film 31 acting as a spacer, and the fourth polycrystalline silicon film are patterned to form the storage electrode 24 of the memory capacitor and the upper gate of the TFT also serving as the fin of the memory capacitor. An electrode 30 is formed.

6- (1) The insulating film 31 made of SiO ₂ is removed by immersion in an aqueous HF solution.

7 and 11 and 12 7- (1) By applying the CVD method, the storage electrode 24 of the memory capacitor and the upper gate electrode 30 of the TFT also serving as the fin of the memory capacitor are formed. Si ₃ N on the surface
_A dielectric film 27 for a memory capacitor having a thickness of, for example, 200 [２００] made of ₄ is formed. 7- (2) The resist process in photolithography and the RIE method using CHF ₃ / He (for Si ₃ N ₄ and SiO ₂ ) as an etching gas are applied to the upper side of the TFT. The gate insulating film 29, the lower gate insulating film 16, the insulating film 7, and the gate insulating film 3 of the driver transistor are selectively etched to form a ground line contact hole 27A (see FIG. 11). 7- (3) Thickness, for example, 1000 by applying the CVD method
[6] A sixth polycrystalline silicon film is formed. 7- (4) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film. 7- (5) RIE using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
By applying the method, the sixth polycrystalline silicon film is patterned to form the counter electrode 28 of the memory capacitor also serving as the ground line.

8 and FIG. 13 8- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. In this figure, as in FIG. 61, two layers of insulating films are integrally shown, and this is referred to as an insulating film 25. 8- (2) A heat treatment for reflowing and planarizing the insulating film 25 is performed. 8- (3) Selective etching of the insulating film 25 and the like is performed by applying a resist process in photolithography technology and an RIE method using CHF ₃ / He as an etching gas to perform bit line contact. Form a hole. 8- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 26.

FIG. 14 is a plan view of a main part of a double gate structure TFT load type SRAM completed through the above-described steps. The same symbols as those used in FIGS. 1 to 13 denote the same parts. Or have the same meaning, except that
For simplicity, the bit line 26 made of Al shown in FIGS. 8 and 13 is removed in FIG. According to the figure, the correlation between the pattern of the counter electrode 28 in the memory capacitor also serving as the ground line and the pattern in other regions in the SRAM can be clearly understood. Generally, if a memory capacitor is separately provided in a double gate structure TFT load type SRAM, a mask step should be added once to form a counter electrode. However, in the first embodiment described above, Since the configuration is such that the counter electrode and the ground line are also used, there is no increase in the number of mask steps by subtraction, and separately from this, as described in the above step 4- (1), the TFT load and the driver Since the interconnect contact holes 31A for connecting the transistors are formed in one mask process, the number of mask processes is reduced by two times as compared with the conventional example described with reference to FIGS.

FIG. 15 shows the TF realized in the study of the present inventors.
FIG. 2 is a plan view of a principal part of a T-load type SRAM. In the figure, 41 is the gate of the TFT, 42 is the channel of the TFT,
43 indicates a word line, and V _CC indicates a positive power supply level. This SRAM has an advantage that the layout is extremely easy because the symmetry of the driver transistor, TFT, and the like is good, as is apparent from the figure. If the present invention is applied to this TFT load type SRAM, A very preferred embodiment is obtained and will now be described.

FIGS. 16 to 25 are cutaway side views of a principal part of a double gate structure TFT load type SRAM at a process point for explaining a second embodiment of the present invention.
The details will be described with reference to these figures. The cutaway side view of the main part in FIGS. 16 to 25 is a line X shown in FIG.
A cut surface along -X is taken.

16- (1) A pad film made of SiO ₂ covering the active region of the silicon semiconductor substrate 51 and Si ₃ laminated on the pad film
By applying a selective thermal oxidation method using an oxidation-resistant mask film made of N _4, a field insulating film 52 made of SiO ₂ and having a thickness of, for example, 4000 [Å] is formed. 16- (2) By removing the oxidation-resistant mask film and the pad film to expose the active region, and then applying the thermal oxidation method, SiO ₂
The gate insulating film 53 having a thickness of, for example, 100 [Å] is formed. 16- (3) Selective etching of the gate insulating film 53 is also performed for impurity diffusion by applying a resist process in photolithography technology and a wet etching method using hydrofluoric acid as an etchant. contact·
A hole 53A is formed. 16- (4) Thickness, for example, 1000 by applying the CVD method
[Å] First polycrystalline silicon film is formed. 16- (5) An n ⁺ -impurity region 54 is formed by introducing P at an impurity concentration of, for example, 1 × 10 ²⁰ [cm ⁻³ ] by applying the vapor phase diffusion method. 16- (6) The first polycrystalline silicon film is patterned by applying a resist process in photolithography and an RIE method using an etching gas of CCl ₄ + O ₂ to form a gate electrode 55. And 56 are formed. 16- (7) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ], and the acceleration energy is set to 30.
[KeV] is implanted with As ions to obtain n ⁺ −
A source region 57 and an n ⁺ -drain region 58 are formed.

Referring to FIG. 17, 17- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] An insulating film 59 made of SiO ₂ is formed. 17- (2) Thickness, for example, 1000 by applying the CVD method
[Å] A second polycrystalline silicon film is formed. 17- (3) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ] and the second polycrystalline silicon film
Introduce. 17- (3) The second polycrystalline silicon film is patterned by applying a resist process in the photolithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas. The lower gate electrode 61 and the like are formed.

FIG. 18 18- (1) The thickness is, for example, 200 by applying the CVD method.
[Å] Lower gate insulating film 6 of TFT made of SiO ₂
Form 2 18- (2) By applying the CVD method, a thickness of, for example, 200
[3] A third polycrystalline silicon film is formed. 18- (3) depending on the applying in resist process and an ion implantation method in the photo-lithography technique, a source region and a drain region of the in TFT in the third polycrystalline silicon film, a V _CC supply line 1 × 10 ¹⁴ dose for power
[Cm ⁻² ], and B is implanted with an acceleration energy of 5 [keV]. 18- (4) A third polycrystalline silicon film is patterned by applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ as an etching gas. Then, a drain region, a source region, a channel region, and a _Vcc supply line of each TFT are formed. Incidentally, since it is impossible to express the whole volume in a side cross section, the contact portion 6 connected to the source region of a certain TFT is shown in FIG.
4 and the channel region 67 of the adjacent TFT are shown.

Referring to FIG. 19, 19- (1) The thickness is, for example, 500 by applying the CVD method.
[Å] The upper gate insulating film 79 of the TFT acting as an etching stopper made of Si ₃ N ₄ is formed.

20- (1) The thickness is, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 20- (2) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ] and the fourth polycrystalline silicon film
Introduce. 20- (3) A thickness of, for example, 500
[Å] An insulating film 81 acting as a spacer made of SiO ₂ is formed. 20- (4) RIE using CHF ₃ / He (for SiO ₂ and Si ₃ N ₄ ) and CCl ₄ / O ₂ (for polycrystalline silicon) as resist process and etching gas in photolithography technology By applying the method, an insulating film 81 acting as a spacer, a fourth polycrystalline silicon film, an upper gate insulating film 79 of a TFT acting as an etching stopper, and a contact portion 64 made of a third polycrystalline silicon film A lower gate insulating film 62 of the TFT, a lower gate electrode 61 of the TFT made of a second polycrystalline silicon film,
Each of the insulating films 59 is selectively etched to form an interconnect contact hole 81A reaching the gate electrode 56 (or 55) of the driving transistor made of the first polycrystalline silicon film from the surface.

FIG. 21 21- (1) The thickness is, for example, 500 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 8- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film.

See FIG. 22 22- (1) RIE using CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for SiO ₂ ) as the resist process and etching gas in the photolithography technique By applying the method, the fifth polycrystalline silicon film, the insulating film 81, and the fourth polycrystalline silicon film are patterned to form the storage electrode 82 of the memory capacitor and the TFT of the TFT also serving as the fin of the memory capacitor. An upper gate electrode 80 is formed.

Referring to FIG. 23, 23- (1) The insulating film 81 made of SiO ₂ is removed by dipping in an aqueous HF solution.

Referring to FIG. 24, 24- (1) the surface of the storage electrode 82 of the memory capacitor and the surface of the upper gate electrode 80 of the TFT also serving as the fin of the memory capacitor are formed from Si ₃ N ₄ by applying the CVD method. A memory capacitor dielectric film 83 having a thickness of, for example, 200 [２００] is formed. 24-(2) Dielectric film by applying RIE method using CHF ₃ / He (for Si ₃ N ₄ and SiO ₂ ) as a resist process and etching gas in photolithography technology 83, TFT upper gate insulating film 79, T
FT lower gate insulating film 62, insulating film 59, driver
The gate insulating film 53 of the transistor is selectively etched to form a ground line contact hole. 24- (3) Thickness, for example, 1000 by applying the CVD method
[6] A sixth polycrystalline silicon film is formed. 24- (3) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film. 24- (4) RIE using CCl ₄ / O ₂ as a resist process and etching gas in photolithography technology
By applying the method, the sixth polycrystalline silicon film is patterned to form the counter electrode 84 of the memory capacitor also serving as the ground line.

See FIG. 25. 25- (1) The thickness is, for example, 1000 by applying the CVD method.
[Å] SiO ₂ insulating film and thickness of, for example, 50
An insulating film made of 00 [Å] PSG is formed. Note that, also in this figure, as in FIG. 8, two layers of the insulating film are integrally shown, and this is referred to as an insulating film 85. 25- (2) A heat treatment is performed to reflow and planarize the insulating film 85. 25- (3) Selective etching of the insulating film 85 and the like is performed by applying a resist process in photolithography technology and an RIE method in which an etching gas is CHF ₃ / He, and Hall (see Fig. 15)
To form 25- (4) Thickness, for example, 1 by applying the sputtering method
A [μm] Al film is formed, and is patterned by applying a normal photolithography technique to form a bit line 88.

In the embodiment described with reference to FIGS. 16 to 25, not only the number of mask steps is reduced as in the embodiment described with reference to FIGS. 1 to 8, but also the TFT load type SRAM shown in FIG. The advantages of the driver
Since the transistors and TFTs have good symmetry, the layout is extremely easy.

FIGS. 26 to 28 are cutaway side views of a main part of a double gate structure TFT load type SRAM at a key point of a process for explaining a third embodiment of the present invention.
The details will be described with reference to these figures. Note that the same applies to the present embodiment from the beginning of the process in the second embodiment described with reference to FIGS. 16 to 25 to the process 19- (1), that is, until the formation of the insulating film 79 made of Si ₃ N _4. Therefore, the description will be omitted, and description will be made from the next stage.

[0077] Figure 26 Referring 26- (1), where the double gate structure TFT load type SRAM is the silicon semiconductor substrate 51, field insulating film 52, the gate insulating film 53, n ⁺ - doped region 54, the first Gate electrodes 55 and 56 of a driver transistor made of a polycrystalline silicon film, an n ⁺ -source region 57, an n ⁺ -drain region 58, an insulating film 59, and a lower gate electrode of a TFT made of a second polycrystalline silicon film 61, a lower gate insulating film 62 of the TFT, a source region and a drain region and a channel region of the TFT composed of a third polycrystalline silicon film, Si ₃
TF acting as an etching stopper made of N ₄
It is assumed that the upper gate insulating film 79 of T is formed. 26- (2) The thickness is, for example, 500 by applying the CVD method.
[4] A fourth polycrystalline silicon film is formed. 26- (3) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ] and the fourth polycrystalline silicon film
Introduce. 26- (4) A thickness of, for example, 500 by applying the CVD method.
[Å] An insulating film 81 acting as a spacer made of SiO ₂ is formed. 26- (5) The thickness is, for example, 500 by applying the CVD method.
The fifth polycrystalline silicon film of [Å] is formed. 26- (6) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ], and the fifth polycrystalline silicon film is doped with P.
Introduce. 26- (7) The thickness is, for example, 500 by applying the CVD method.
[Å] An insulating film 90 serving as a spacer made of SiO ₂ is formed. 26- (8) RIE using CHF ₃ / He (for SiO _{2 and} for Si ₃ N ₄ ) and CCl ₄ / O ₂ (for polycrystalline silicon) as resist process and etching gas in photolithography technology By applying the method, the insulating film 90 acting as a spacer, the fifth polycrystalline silicon film,
An insulating film 81 acting as a spacer, a fourth polycrystalline silicon film, an upper gate insulating film 79 of a TFT acting as an etching stopper, a third polycrystalline silicon film, TF
The lower gate insulating film 62 of T, the lower gate electrode 61 of the TFT made of the second polycrystalline silicon film, and the insulating film 59 are selectively etched to form the first polycrystalline silicon film as the driving transistor An interconnect contact hole 90A reaching the gate electrode of FIG.

See FIG. 27. 27- (1) The thickness is, for example, 500 by applying the CVD method.
[6] A sixth polycrystalline silicon film is formed. 27- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the sixth polycrystalline silicon film.

See FIG. 28 28- (1) RIE using resist process and etching gas in photolithography technology as CCl ₄ / O ₂ (for polycrystalline silicon) and CHF ₃ / He (for SiO ₂ ) By applying the method, each of the sixth polycrystalline silicon film, the insulating film 90 acting as a spacer, the fifth polycrystalline silicon film, the insulating film 81 acting as a spacer, and the fourth polycrystalline silicon film is formed. Patterned, storage capacitor storage electrode 91, memory capacitor fin 8
9. The upper gate electrode 80 of the TFT which also serves as the fin of the memory capacitor is formed. 28- (2) The insulating films 90 and 81 made of SiO ₂ are removed by dipping in an aqueous HF solution. 28- (3) Thereafter, steps such as the formation of a dielectric film for a memory capacitor, which are the same as the steps 24- (1) and subsequent steps in the second embodiment described with reference to FIGS. good.

The embodiment described with reference to FIGS. 26 to 28 differs from the embodiment described with reference to FIGS. 16 to 25 in that the number of fins integrated with the storage electrode 91 of the memory capacitor is substantially three times. Because of the number of sheets, the capacity of the memory capacitor increases.

FIG. 29 to FIG. 32 are cutaway side views of a main portion of a double gate structure TFT load type SRAM at a process point for explaining a fourth embodiment of the present invention.
The details will be described with reference to these figures. Incidentally, from the beginning of the process in the second embodiment described with reference to FIGS. 16 to 25 to the process 18- (1), that is, by patterning the third polycrystalline silicon film, the contact portion, each TF
This is the same in this embodiment until the drain region, source region, channel region, _Vcc supply line, and the like of T are formed.

[0082] Figure 29 Referring 29- (1), where the double gate structure TFT load type SRAM, the field insulating film 52 on the silicon semiconductor substrate 51, a gate insulating film 53, n ⁺ - doped region 54, the first multi Gate electrode 55 of driver transistor made of crystalline silicon film
And 56, n ⁺ -source region 57, n ⁺ -drain region 5
8, TF comprising insulating film 59 and second polycrystalline silicon film
T lower gate electrode 61, TFT lower gate insulating film 6
2. It is assumed that the source region, the drain region, the channel region, the _Vcc supply line, and the like of the TFT made of the third polycrystalline silicon film are formed. 29- (2) A thickness of, for example, 500
[Å] Upper gate insulating film 9 of TFT made of SiO ₂
Form 2 29- (3) The thickness is, for example, 500 by applying the CVD method.
The fifth polycrystalline silicon film of [Å] is formed. 29- (4) By applying the vapor phase diffusion method, the impurity concentration is set to, for example, 1 × 10 ²⁰ [cm ⁻³ ] and the fifth polycrystalline silicon film
Introduce. 29- (5) By applying a resist process in photolithography technology and an RIE method using CCl ₄ / O ₂ (for polycrystalline silicon) as an etching gas, a fifth polycrystalline silicon film is formed. The upper gate electrode 93 of the TFT is formed by patterning.

Referring to FIG. 30 30- (1) The thickness is, for example, 500 by applying the CVD method.
An insulating film 94 acting as an etching stopper made of Si ₃ N ₄ ([絶 縁]) and an insulating film 95 acting as a spacer made of SiO _{2 having a} thickness of, for example, 500 [Å] are formed in this order. 30- (2) CHF ₃ / He (for SiO ₂ and Si ₃ N ₄ ) and CCl ₄ / O ₂ (for polycrystalline silicon) resist and etching gas in photolithography technology
Is applied, the insulating film 95 acting as a spacer, the insulating film 94 acting as an etching stopper, the upper gate electrode 93 of the TFT, the TF
T upper gate insulating film 92, third polycrystalline silicon film in which a source region and a drain region of the TFT are formed, lower gate insulating film 62 of the TFT, lower gate electrode 61 of the TFT, insulating film 59 Contact hole 9 from the surface to the gate electrode of the driving transistor which is the first polycrystalline silicon film by selectively etching
Form 5A.

See FIG. 31. 31- (1) The thickness is, for example, 500 by applying the CVD method.
[5] A fifth polycrystalline silicon film is formed. 31- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 31- (3) RIE using resist process and etching gas of CCl ₄ / O _{2 in} photolithography technology
By applying the fifth method, the fifth polycrystalline silicon film is patterned to form the storage electrode 96 of the memory capacitor.
To form

Referring to FIG. 32, 32- (1) the insulating film 95 made of SiO ₂ is removed by immersion in an aqueous HF solution. 32- (2) Thereafter, steps such as the formation of a dielectric film for a memory capacitor, which are the same as the steps 24- (1) and subsequent steps in the second embodiment described with reference to FIGS. good.

The fourth embodiment described with reference to FIGS. 29 to 32 differs from the second embodiment described with reference to FIGS. 16 to 25 in that the configuration for forming the storage electrode of the memory capacitor is modified. . Usually, when etching the polycrystalline silicon film, than the base is a Si ₃ N ₄ S
Since iO ₂ can secure the selectivity and the Si ₃ N ₄ film acting as an etching stopper in the hydrofluoric acid solution is not exposed to RIE when etching the polycrystalline silicon film, the Si ₃ N ₄ film is used. Is not damaged. Therefore, the fourth embodiment has an advantage that the storage electrode of the memory capacitor can be formed stably. However, although the number of mask steps increases once compared to the second embodiment, it is still smaller once compared to the conventional technique.

[0087]

In a semiconductor memory device and a method of manufacturing the same according to the present invention, a pair of driver transistors formed on a semiconductor substrate and a pair of double-gate TFTs formed on a semiconductor layer on the semiconductor substrate are provided. A load and a memory capacitor formed on an upper portion of the double gate structure TFT load, and the drain and upper and lower gate electrodes of the double gate structure TFT load are connected to the gate or drain of the driver transistor. Comprising a memory cell having a connection region, wherein said double gate structure TF
The T load is formed through a lower gate electrode connected to the drain of the driver transistor, a channel formed on the lower gate electrode via a lower gate insulating film, and an upper gate insulating film on the channel. An upper gate electrode, the memory capacitor facing the storage electrode via a storage electrode, a memory capacitor dielectric film covering the storage electrode, and the driver capacitor. A counter electrode that also serves as a ground line connected to the source of the transistor; and in the connection region, at least the drain and upper and lower gate electrodes of the double gate structure TFT load and the gate electrode or the drain of the driver transistor are interposed via an insulating film. And the storage electrode of the memory capacitor is in contact with the side of the intermediate electrode. It is connected by a gate and drain and its surface of the driver transistors constituting the flip-flop circuit together with the.

As is apparent from the above description, in the present invention, the same contact hole is formed at the same place by interconnecting the gate electrode of the driver transistor, the gate electrode of the double gate structure TFT load, and the drain. Because the configuration allows connection by using the driver,
A contact hole for interconnection between the transistor and the double gate structure TFT load needs to be formed only once, and a memory capacitor is separately provided to improve radiation resistance.・ Since the counter electrode of the capacitor and the ground line can be shared, a double gate structure TFT load type SRAM having a memory capacitor in addition to a parasitic capacitance can be easily and easily produced with a small number of manufacturing steps. It can be manufactured well.

[Brief description of the drawings]

FIG. 1 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a first embodiment of the present invention.

FIG. 2 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a first embodiment of the present invention.

FIG. 3 is a cutaway side view of a main part of a double-gate-structure TFT-load type SRAM at an important part of a process for explaining a first embodiment of the present invention;

FIG. 4 is a cutaway side view of a main part of the double gate structure TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 5 is a cutaway side view of a main part of a double-gate-structure TFT-loaded SRAM at an important point in the process for explaining the first embodiment of the present invention;

FIG. 6 is a cutaway side view of a main portion of a double gate structure TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 7 is a cutaway side view of a main part of the double gate structure TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 9 is a plan view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a first embodiment of the present invention.

FIG. 10 is a plan view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining the first embodiment of the present invention.

FIG. 11 is a plan view of a main part of a double-gate-structure TFT-loaded SRAM at a key point in the process for explaining the first embodiment of the present invention;

FIG. 12 is a plan view of a main part of a double gate structure TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention.

FIG. 13 is a plan view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining the first embodiment of the present invention.

FIG. 14 is a plan view of a main part of a double gate structure TFT load type SRAM at a key point in the process for explaining the first embodiment of the present invention;

FIG. 15 shows a TFT load type SRA realized by the present inventors.
It is a principal part top view of M.

FIG. 16 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention;

FIG. 17 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 18 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 19 is a cutaway side view of a main part of a double-gate-structure TFT-loaded SRAM at an important part of a process for explaining a second embodiment of the present invention;

FIG. 20 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention;

FIG. 21 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention.

FIG. 22 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention;

FIG. 23 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention;

FIG. 24 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a second embodiment of the present invention;

FIG. 25 is a fragmentary side view of a double gate structure TFT load type SRAM at a key step for explaining a second embodiment of the present invention;

FIG. 26 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 27 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a main point of a process for explaining a third embodiment of the present invention.

FIG. 28 is a side sectional view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a third embodiment of the present invention;

FIG. 29 is a cutaway side view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 30 is a fragmentary side elevational view of a double gate structure TFT load type SRAM at an important part of a process for explaining a fourth embodiment of the present invention;

FIG. 31 is a side sectional view of a main part of a double gate structure TFT load type SRAM at an important part of a process for explaining a fourth embodiment of the present invention;

FIG. 32 is a side cutaway view of a main part of a double gate structure TFT load type SRAM at a key point in a process for explaining a fourth embodiment of the present invention;

FIG. 33 is a side sectional view of a relevant part in a process key for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 34 is a cross-sectional side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 35 is a cutaway side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 36 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 37 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 38 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM;

FIG. 39 is a fragmentary sectional side view at a key step of the process for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 40 is a fragmentary side elevational view at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 41 is a sectional side view of a relevant part in a process key for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 42 is a cross-sectional side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 43 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high-resistance load type SRAM in a process essential point;

FIG. 44 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a key point in a process;

FIG. 45 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high resistance load type SRAM at a key point in a process.

FIG. 46 is a fragmentary plan view for explaining a conventional example of a method for manufacturing a high resistance load type SRAM at a key point in a process.

FIG. 47 is a plan view of a main portion in a process key point for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 48 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a high-resistance load type SRAM in a process key point;

FIG. 49 is an equivalent circuit diagram of a main part of a high resistance load type SRAM.

FIG. 50 is a cross-sectional side view of a relevant part at a key point in a process for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 51 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 52 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 53 is a cross-sectional side view of a relevant part at a key step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 54 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM in a process essential point;

FIG. 55 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM at a key point in a process.

FIG. 56 is a fragmentary plan view for explaining a conventional example of a method of manufacturing a TFT load type SRAM in a relevant part of a process;

FIG. 57 is a plan view of a main portion in a process step for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 58 is a main part equivalent circuit diagram of a TFT load type SRAM.

FIG. 59 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a double gate structure TFT load type SRAM.

FIG. 60 is a fragmentary side elevational view at a key step for explaining a conventional example of a method for manufacturing a double gate structure TFT load type SRAM.

FIG. 61 is a fragmentary side elevation view at a key step for explaining a conventional example of a method of manufacturing a double gate structure TFT load type SRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Field insulating film 3 Gate insulating film 3A Contact hole 4 Gate electrode 5 Source region 5 'Impurity region 6 Drain region 7 Insulating film 15 Lower gate electrode 16 Lower gate insulating film 17 Source region 18 Drain region 19 Channel region 24 Storage capacitor storage electrode 25 Insulating film 26 Bit line 27 Dielectric film for memory capacitor 28 Counter electrode of memory capacitor 29 Insulating film 31 Insulating film

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/8244 H01L 21/822 H01L 27/04 H01L 27/11 H01L 29/786

Claims (10)

(57) [Claims] 1. A pair of driver transistors formed on a semiconductor substrate to form a flip-flop circuit, a pair of double-gate TFTs formed on a semiconductor layer on the semiconductor substrate, and the double-gate TFT. It is configured to include a memory capacitor formed above the load, and has a connection region where the drain and upper and lower gate electrodes of the double gate structure TFT load and the gate or drain of the driver transistor are mutually connected. Wherein the double gate structure TFT load is formed on the lower gate electrode connected to the drain of the driver transistor via the lower gate insulating film on the lower gate electrode. Comprising a channel and an upper gate electrode formed on the channel via an upper gate insulating film; The memory capacitor has a storage electrode, a dielectric film for the memory capacitor covering the storage electrode, and a ground line opposed to the storage electrode via the dielectric film for the memory capacitor and connected to a source of the driver transistor. A semiconductor memory device comprising a counter electrode serving also as a semiconductor device. 2. The connection region, wherein at least the drain and upper and lower gate electrodes of a double gate structure TFT load and a driver
The gate electrode or the drain of the transistor is stacked with an insulating film interposed therebetween, and the storage electrode of the memory capacitor is connected to the side surface of the intermediate electrode, and the gate of the driver transistor forming a flip-flop circuit 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to the drain at a surface thereof. 3. The memory capacitor according to claim 1, wherein an upper gate electrode in the double gate structure TFT load is covered with a dielectric film for a memory capacitor and also serves as a fin of the memory capacitor. Semiconductor storage device. 4. At least one memory capacitor fin is interposed between an upper gate electrode of a double gate structure TFT load also serving as a memory capacitor fin and a storage electrode of the memory capacitor. 3. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is connected to said storage electrode. 5. An upper gate insulating film which is a base of an upper gate electrode of a double gate structure TFT load also serving as a fin of a memory capacitor is formed to be thicker than a dielectric film for a memory capacitor. 3. The semiconductor memory device according to claim 1, wherein: 6. The semiconductor device according to claim 1, wherein the upper gate insulating film between the channel of the double gate structure TFT load and the upper gate electrode comprises a silicon nitride film acting as an etching stopper. Semiconductor storage device. 7. A step of forming a field insulating film on the surface of a semiconductor substrate and then forming a gate insulating film, and then patterning after growing a first conductive film to form a gate electrode of the driver transistor. Forming and then forming an impurity region by introducing impurities using the field insulating film and the gate electrode of the driver transistor as the first conductive film as a mask, and then forming a first insulating film. And then forming a lower gate electrode of a double gate structure TFT load by growing and patterning a second conductive film to form a lower gate insulating film as a second insulating film; and Next, a third conductive film is grown, and selective impurity introduction and patterning are performed to form a source region, a drain region, and a channel region of the double gate structure TFT load. Forming an upper gate insulating film of a double gate structure TFT load, which is a third insulating film after forming, and then growing a fourth conductive film and then growing a fourth insulating film. Next, an upper gate insulating film which is the fourth insulating film, the fourth conductive film, and the third insulating film, a drain region formed of the third conductive film, and a lower region which is the second insulating film. A side gate insulating film, a lower gate electrode made of the second conductive film, and the first insulating film are selectively removed to remove a side surface of the fourth conductive film and a drain region made of the third conductive film; Forming an interconnect contact hole exposing the side surface of the lower gate electrode made of the second conductive film and the surface of the gate electrode of the driver transistor made of the first conductive film, and Of the fourth conductive film And a side surface of a drain region formed of the third conductive film, a side surface of a lower gate electrode formed of the second conductive film, and a surface of a gate electrode of a driver transistor formed of the first conductive film. After the fifth conductive film is formed, the fifth conductive film, the fourth insulating film, and the fourth conductive film are patterned to serve also as an insulating film acting as a storage electrode and a spacer of the memory capacitor and a fin of the memory capacitor. Forming the upper gate electrode of the double-gate structure TFT load, and then removing the insulating film serving as a spacer between the storage electrode and the upper gate electrode of the memory capacitor. Forming a dielectric film for the memory capacitor covering the storage electrode and the upper gate electrode of the memory capacitor; Forming a ground line contact hole corresponding to the source, and then forming a counter electrode of the memory capacitor also serving as a ground line made of the sixth conductive film. Manufacturing method. 8. The method according to claim 8, wherein at least one conductive film serving as a fin of a memory capacitor is grown by interposing an insulating film serving as said spacer on said upper gate electrode of said double gate structure TFT load. 8. The method of manufacturing a semiconductor memory device according to claim 7, further comprising the step of patterning simultaneously when forming the storage electrode of the memory capacitor made of the five conductive films. 9. An insulating film acting as a storage electrode and a spacer of a memory capacitor using the upper gate insulating film of the double gate structure TFT load formed of a silicon nitride film as an etching stopper, and the double gate structure TF.
8. The method according to claim 7, further comprising the step of patterning an upper gate electrode of the T load. 10. A silicon nitride film serving as an etching stopper and a spacer serving as an etching stopper when patterning a storage electrode of a memory capacitor after patterning a conductive film to form an upper gate electrode of the double gate structure TFT load. 8. The method according to claim 7, further comprising the step of sequentially forming insulating films to be formed.