JPH01270344A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase remarkably a storage capacitance to contrive an increasing in the integration of a DRAM without forming a through hole for increasing the lamination of a storage electrode by a method wherein the overhang-shaped storage electrode supported on the source and drain region on one side is formed. CONSTITUTION:A gate insulating film 3 and a gate 4 are formed in order on a semiconductor substrate 1 and an impurity having a conductivity type opposited to that of the substrate is introduced in the substrate on both sides of the gate to form source and drain regions 5. Then, an interlayer insulating film 6 and a film 6A are adhered in order on the whole surface of the substrate and an aperture is formed on the films 6 and 6A to expose the source and drain region on one side. Then, the aperture is covered with a storage electrode 7 to form the electrode 7 on the film 6A and the film 6A is etched away by an etching method, in which the etching speed of the film 6A is larger than those of the substrate, the film 6 and the electrode 7, to form a dielectric film 8A on the surface of the electrode 7. The film 8A is formed continuously up to the lower sides of the overhangs of the electrode 7. Moreover, an opposed electrode 9A is formed in contact to the film 8A.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a semiconductor device, particularly a stacked capacitor type DRAM cell.

The purpose is to significantly increase the storage capacity of stacked capacitor type DRAM cells without forming through holes for stacking electrodes, and to achieve higher integration of DRAMs.

DRAM by making it possible to significantly increase the storage capacity without forming through holes for stacking electrodes.
The purpose is to achieve high integration.

A gate insulating film (3) and a gate (4) are sequentially formed on a semiconductor substrate (1), impurities opposite to the substrate are introduced into the substrate on both sides of the gate, and a source/drain region (5) is formed. An interlayer insulating film (6) and a film (6A) are sequentially deposited on the entire surface of the substrate, and the core interlayer insulating film and the film are opened to expose one source/drain region, and the opening is opened. A storage electrode (7) is formed on the film, and the film (6^) is etched away using an etching method in which the etching rate of the film is higher than that of the substrate, the core interlayer insulating film, and the storage electrode.

A dielectric film (8A) is formed on the surface of the storage electrode, and a counter electrode (9A) is formed in contact with the dielectric film.

[Industrial application field]

The present invention relates to semiconductor devices, particularly stacked capacitor type DR.
The present invention relates to a method of manufacturing an AM cell.

Stacked capacitor type DRA? The cell is a highly integrated DR
It is widely used as a cell for ArI.

[Conventional technology]

As the cell area becomes smaller as DRAM becomes more highly integrated,
Various attempts have been made to increase the ratio of cell storage capacity to cell area.

FIG. 2 is a sectional view of a conventional stacked capacitor type DRAM cell.

A cell is composed of one storage capacitor that stores information charge and one transfer transistor that transfers information.

A super insulating film, 3 a gate insulating film, and 4 a word line made of poly-Si and the gate of a transistor.

There are two numerals 5, each representing a source/drain region of a transistor, 6 an interlayer insulating film, 7 a storage electrode of a capacitor made of poly-Si, 8 a dielectric film of the capacitor, and 9 a poly-S
The opposing electrode of the capacitor consisting of i.

10 is an interlayer insulating film, and 11 is a bit line made of an A1 layer.

Since the storage electrode 7 in this cell is formed in a three-dimensional shape, a capacity increased by 30 to 40% compared to the case of a flat electrode can be obtained, making it possible to obtain a highly integrated DRA. This is an effective cell structure for realizing I.

[The challenge that the invention attempts to solve]

However, even in the above-mentioned conventional structure, as the number of integrated bits of the memory increases and the absolute size of the storage capacitor portion becomes smaller, a decrease in the storage capacitance is unavoidable.

In order to further increase the storage capacity, many structures have been proposed in which capacitor electrodes are stacked.

It is necessary to form a through hole to connect between the electrodes, and there are drawbacks such as the fact that the cell cannot be miniaturized in order to provide alignment margin for forming the through hole.

An object of the present invention is to significantly increase the storage capacity of a stacked capacitor type DRAM cell without forming through holes for stacking electrodes.

[Means to solve the problem]

To solve the above problem, a gate insulating film (3) and a gate (4) are sequentially formed on a semiconductor substrate (1), and impurities opposite to the substrate are introduced into the substrate on both sides of the gate. A drain region (5) is formed, an interlayer insulating film (6) and a film (6A) are sequentially deposited on the entire surface of the substrate, and the interlayer insulating film and the film are opened to expose one source/drain region. Then, a storage electrode (7) is formed on the film covering the opening, and the film (7) is etched by an etching method in which the etching rate of the film is higher than that of the substrate, the core interlayer insulating film, and the storage electrode.
6A) is removed by etching, a dielectric film (8A) is formed on the surface of the storage electrode, and a counter electrode (9A) is formed in contact with the dielectric film.
This is achieved by a method for manufacturing a semiconductor device including the step of forming A).

[Effect]

The present invention increases the storage capacitance by providing a method of forming a capacitor that wraps around the storage electrode by forming an eave-like storage electrode supported on one of the source and drain openings.

〔Example〕

FIGS. 1(1) to 1(5) are cross-sectional views illustrating a method of manufacturing a stacked capacitor type DRAM cell according to an embodiment of the present invention.

In Figure 1 (1), p-5i is
An insulating film 2 is formed on the isolation region of the substrate 1, and a gate insulating film 3 is formed on the element formation region of the substrate using a conventional method. A gate 4 made of poly-Si is formed.

Next, using the gate 4 as a mask, arsenic ions (As") or phosphorus ions (P") are implanted to form n-type source/drain regions 5.

Next, a silicon dioxide film (SiO film) 6 is formed on the entire surface of the substrate as an insulating film 11 by a vapor phase growth (CVD) method.

A silicon nitride film (sisN) is used as a film for forming the bottom of the storage electrode.
4 films) 6A are grown, contact holes for storage electrodes are opened in these films, and the surface of one source/drain region 5 is exposed.

In FIG. 1(2), a doped poly-Si layer 7' having a thickness of 2500 nm is grown over the entire surface of the substrate by the CVD method, covering the contact hole.

In FIG. 1(3), the storage electrode 7 is formed by patterning the poly-Si layer 7' on the 5iJ4 film 6A to a predetermined size. This pattern is formed as large as possible so as to cover up to the gate 4.

In FIG. 1 (4), 5iJ4 film 6A was prepared using hot phosphoric acid.
When removed, an eave-shaped storage electrode 7 supported by the contact portion remains.

For example, about 20 people are thermally oxidized and then CVD S is applied on top of this.
i: A thin layer of +N4 is deposited, for example, about 100 layers, and then thermally oxidized in an oxygen atmosphere to form a dielectric film 8 with a total thickness of 200 layers.
form eight.

In this way, the dielectric film 8A is formed continuously to the underside of the eaves of the storage electrode 7.

Furthermore, a 2,500-layer doped poly-Si layer is grown on the entire surface of the substrate by CVD to form a counter electrode 9^.

Thereafter, an interlayer insulating film 10 is grown over the entire surface of the substrate, and contact holes are made in the other source/drain region.

An Al film is deposited on the entire surface of the substrate to cover this contact hole,
Bit lines 11 are formed by patterning.

〔Effect of the invention〕

As explained above, according to the present invention, a manufacturing method can be obtained which can significantly increase the storage capacity of a stacked capacitor type DRAM cell without forming through holes for stacking electrodes, and it is possible to obtain a manufacturing method that can significantly increase the storage capacity of a stacked capacitor type DRAM cell. can contribute to the development of

[Brief explanation of the drawing]

FIG. 1 (11 to (5)) is a cross-sectional view illustrating a method of manufacturing a stacked capacitor type DRAM cell according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional stacked capacitor type DRAM cell. In the figure: 1 is a p-5t substrate. 2 is an isolation insulating film. 3 is a gate insulating film. 4 is a gate. 5 is a source/drain region. 6 is an interlayer insulating film, which is a 5iOz film. 6A is an S:sNa film. 7 is a storage electrode. 7' is a poly-Si layer. 8A is a dielectric film. 9A is a counter electrode. 10 is an interlayer insulating film. 11 is a bit line

Claims (1)

[Claims] A gate insulating film (3) and a gate (4) are sequentially formed on a semiconductor substrate (1), and impurities opposite to the substrate are introduced into the substrate on both sides of the gate to form a source. Drain region (
5), depositing an interlayer insulating film (6) and a coating (6A) sequentially over the entire surface of the substrate, opening the interlayer insulating film and the coating to expose one source/drain region, and A storage electrode (7) is formed on the film covering the opening, and the film (7) is etched by an etching method in which the etching rate of the film is higher than that of the substrate, the interlayer insulating film, and the storage electrode.
6A), a dielectric film (8A) is formed on the surface of the storage electrode, and a counter electrode (9A) is formed in contact with the dielectric film.
A method for manufacturing a semiconductor device, comprising the step of forming A).