JPS63133565A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the capacitance of a cell sharply by a method wherein the capacitance between a first conductive layer and a second conductive layer is connected in parallel with the capacitance between the second conductive layer and a third conductive layer. CONSTITUTION:A polycrystalline silicon film is grown on a diffused layer 3, which, on a semiconductor layer 1, forms a source region, on an interlayer insulating film and on an element isolation region; it is transformed into a first conductive layer 7 after an impurity has been diffused. After the assembly has been oxidized, an insulating film 8a is formed. Then, after the polycrystalline silicon film has been grown, it is transformed into a second conductive layer 9; after diffusion of the impurity and after oxidation, an insulating film 8b is formed. Then, the insulating film at the edge part of the first conductive layer 7 is removed selectively by a photolithographic technique; in addition, the polycrystalline silicon film which is connected electrically to the first conductive layer 7 is grown on the insulating film 8b; this film is transformed into a third electric-conductive layer 12 after the impurity has been diffused. As a result, the capacitance of a cell becomes about twice the capacitance between the first conductive layer 7 and the second conductive layer 9.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory devices, particularly to memory cells of dynamic random access memories (DRAMs).

2. Description of the Related Art In recent years, as DRAMs have become more highly integrated and have larger capacities, it has become essential to increase the density of memory cells, which account for about half of the chip size. Therefore, these memory cells are required to be miniaturized and also required to have sufficient cell capacity (50 fF or more) to ensure reliability as a memory. In order to meet these demands, the structure of the cell capacitor element has been proposed as an alternative to the conventional flat plate capacitor, such as a trench type capacitor and a stacked capacitor having a three-dimensional structure.

FIG. 2 is a cross-sectional view of a memory cell having a three-dimensional stacked structure. A first conductive layer 7 is formed on the diffusion layer region 3 in the surface portion separated by the element isolation insulating film 2 on the semiconductor substrate 1, which is the source region of the access transistor of the memory cell. After forming an insulating thin film 8, a second conductive layer 9 serving as a cell plate is formed on top of this insulating thin film to constitute a capacitive element. In the capacitive element of this structure, a large capacitance is ensured also on the isolation insulating film 2 and the gate electrode 5 of the access transistor, and since the conductive layer serving as the electrode constituting the capacitive element has undulations, a large capacitance can be ensured.

Note that in this figure, the drain region diffusion layer 4 of the access transistor. The word line conductive layer 62, interlayer insulating film 10, and bit line conductive layer 111 are each formed in the process of forming a memory cell.

Problems to be Solved by the Invention Memory cell capacitors with a three-dimensional stacked structure have a small area at the PN junction between the source region diffusion layer of the access transistor and the substrate, and are resistant to soft errors caused by alpha rays (and , it is possible to configure a capacitive element on the element isolation region and the access transistor, making it easy to secure a relatively large memory cell capacity even in a small area.However, the conductive layer that serves as the electrode is a stack of two layers, and its structure There is a limit to the increase in cell capacity, and the demand for further miniaturization of memory cells inevitably results in a shortage of cell capacity.

The present invention aims to solve the above-mentioned shortage of cell capacity, and has a structure that significantly increases cell capacity while having the low soft error rate and low leakage current characteristics that are the features of three-dimensional laminated structure capacitor elements. To realize a semiconductor memory device with
).

Means for Solving the Problems The semiconductor memory device of the present invention includes a first conductive layer formed on a predetermined semiconductor substrate diffusion layer of a semiconductor memory cell portion, and a first conductive layer formed on the first conductive layer with an insulating film interposed therebetween. forming a third conductive layer electrically connected to the first conductive layer through an insulating film on the formed second conductive layer; The capacitance between the conductive layer and the second conductive layer and the capacitance between the second conductive layer and the third conductive layer are coupled in parallel.

Function According to a memory cell with this structure, the cell capacitance is the parallel connection capacitance of the capacitance between the first conductive layer and the second conductive layer and the capacitance between the third conductive layer and the second conductive layer. The shape and three-dimensional laminated structure capacity increases in comparison. In addition, by reducing the area of the source region diffusion layer of the access transistor as small as possible in terms of design or process technology, the PN junction region between the source region diffusion layer and the semiconductor substrate can be reduced, and the memory cell Leakage current can be made extremely small. Furthermore, since the PN junction region is small, the associated depletion layer region also becomes very small, making it possible to reduce α-ray soft errors.

EXAMPLE Hereinafter, an example of the present invention in which a polycrystalline silicon film is used as a conductive layer will be described in detail with reference to the cross-sectional view shown in FIG.

In FIG. 1, a polycrystalline silicon film is grown to a thickness of 200 nm on the diffusion layer 3 on the semiconductor substrate 1 forming the source region of the access transistor, the interlayer insulating film on the access transistor, and the element isolation region, and impurity diffusion is performed. One conductive layer 7 is used.

Next, the surface of the polycrystalline silicon film is oxidized at 1050° C. in an oxidizing atmosphere to form an insulating film 8a having a thickness of LonI.

Next, a 200nm polycrystalline silicon film is deposited on the insulating film 8.
m to form the second conductive layer 9. Further, impurities are diffused into the second conductive layer and oxidized in an oxidizing atmosphere at 1050° C. to form an insulating film 8b having a thickness of 10 nm. Next, the insulating film at the end of the first conductive layer 7 is selectively removed by photolithography, and a polycrystalline silicon film electrically connected to the first conductive layer 7 is placed on the insulating film 8b. 20
The third conductive layer 12 is grown to a thickness of 0 nm and subjected to impurity diffusion. As a result, the cell capacitance is increased between the first conductive layer 7 and the second conductive layer I? This is approximately twice the capacitance between R9 and cell capacitance, making it extremely easy to secure cell capacity even in a small area. To explain other parts in FIG. 1, 3 is a diffusion layer forming the drain region of the access transistor, 10 is an interlayer insulating film for electrical isolation between conductive layers, and 6 is a word line. 11 is a conductive layer forming a bit line.

In the above embodiment, the first conductive layer and the third conductive layer are electrically connected, and the capacitance between the first conductive layer and the second conductive layer is increased as if the first conductive layer had a folded structure. Furthermore, by forming a fourth conductive layer on the third conductive layer via an insulating film and electrically connecting it to the second conductive layer, the second conductive layer also has a folded structure. Cell capacity can be increased. That is, a large cell capacity can be obtained by stacking electrically connected odd-numbered conductive layers and electrically connected even-numbered conductive layers in multiple layers with an insulating film interposed therebetween.

Below, titanium silicide (TiSi2) is used as the conductive layer.

An embodiment of the present invention in which a CVDSiO2 film formed at high temperature is used as the insulating thin film will be described in detail with reference to the cross-sectional view of FIG.

As the first conductive layer 7, TiSi2 was deposited to a thickness of 2000 Å by sputtering, and 900 Å thick was deposited in an Ar atmosphere.
Heat treatment is performed at ℃ for 30 minutes. Next, by CVD method, 85
After growing a 5i02 film to a thickness of 10 nm+ at 0°C to form an insulating thin film 8a, a TiSi2 film of 200 OA was deposited as a second conductive layer 9 by sputtering, and heat-treated at 900°C for 30 minutes in an Ar atmosphere. conduct. Subsequently, as the insulating thin film 8b, an oxide film is formed at 850° C. by CVD to a thickness of Io.
After the ns growth, the oxide film at the end of the second conductive layer is removed using a photolithography technique, and a TiSi2 film 2 is formed as a third conductive layer 12 electrically connected to the second conductive layer.
00OA was deposited by sputtering, and 9% was deposited in an Ar atmosphere.
Heat treatment is performed at 00°C for 30 minutes. This makes it possible to increase cell capacity.

Effects of the Invention As described above, the semiconductor memory device according to the present invention allows the memory cell capacity to be extremely large, and α
It is also effective in reducing soft errors caused by wires and leakage current, making it possible to further increase the integration and capacity of semiconductor memory devices.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a memory cell of a semiconductor memory device according to the present invention, and FIG. 2 is a sectional view of a conventional device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Element isolation insulating film, 3... Source region diffusion layer, 4...
- Drain region diffusion layer, 5... Access transistor gate electrode, 6... Word line conductive layer, 7... First conductive layer, 8a, 8b...・
- Insulating thin film, 9... Second conductive layer, 10...
. . . Interlayer insulating film, 11 . . . Bit line conductive layer, 12 . . . Third conductive layer. Name of agent Patent attorney Toshio Nakao and 1 other person

Claims (1)

[Claims] A first conductive layer formed on a predetermined semiconductor substrate diffusion layer of the semiconductor memory cell section, a second conductive layer formed on the first conductive layer with an insulating film interposed therebetween, and on the second conductive layer. A third conductive layer is formed which is electrically connected to the first conductive layer through an insulating film, and the capacitance between the first conductive layer and the second conductive layer is increased. A semiconductor memory device characterized in that capacitances between the second conductive layer and the third conductive layer are coupled in parallel.