JPH0221653A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a device of a high integration degree like a 16MDRAM capable of operation by application of external power supply voltage, by making two or more kinds of gate insulating films with different thicknesses exist, and making the total area of the thinnest insulating films among the gate insulating films of a MOS transistor larger than the total area of the thickest insulating films. CONSTITUTION:A first gate insulating film for the capacitor of a DRAM memory cell formed by a transistor and a capacitor is formed, and a first gate electrode for the capacitor is formed on the insulating film. A second gate insulating film of a first MOS transistor performing ON-OFF operation except the switching transistor of a DRAM memory cell is formed, and a second gate electrode is formed on the insulating film. After that, a third gate insulating film of a second MOS transistor performing ON-OFF operation except the switching transistor of the DRAM memory cell is formed more thickly than the second insulating gate film, and a third gate electrode is formed on the insulating film.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a dynamic random access memory, and in particular to a semiconductor including a DRAM structure having a design rule of about 0.5 μm, such as a 16M DRAM. The present invention relates to a device and a method for manufacturing the same.

(Prior technology) The integration of dynamic random access memory has progressed at a rate of four times every three years, and now IMbit's D R
AM is now in mass production.

If we continue at this pace, in 6 years we will have 16 MDRA.
M will be mass produced. Therefore, basic studies on 16MDRAM are currently underway in various places.

In order to realize a 16M DRAM, it is necessary to reduce the size of the memory cell to about 1/2 to 1/3 of that of the previous generation 4M DRAM.

A trench cell is an example of a 4 Mbit DRAM cell. FIG. 3 shows a sectional view of a cell as a conventional example.

As a means of preserving cell charge poison (product of capacitance and voltage) and reducing the cell area to 1/2 to 1/3, there is a method of deepening the trench groove and thinning the gate oxide film. The purpose of preserving the cell charge amount is to sufficiently compensate the operation margin, and even from 64 Kbit to IMbit, the charge amount of approximately 200 femtocoulombs is preserved.

However, if the capacitor oxide film is simply made thinner, the gate oxide film will be destroyed in a short time due to the write voltage applied to the cell. In other words, in a 4M DRAM, the capacitor insulating film has a voltage of 1 of the external voltage (Vcc).
/2 voltage is applied to the oxide film of 100 people, which ensures sufficient reliability, but the voltage of 16M
In a DRAM, when using, for example, a 50-layer oxide film as a capacitor insulating film, the external voltage (Vcc) is set to, for example, 4.
When stored at 5V for MDRAM, the electric field applied to the oxide film increases from 2.5MV/cm for 4MDRAM to 5M
V/cm, and the oxide film is destroyed in a short time as described above. Therefore, the cell has 5V
Studies are underway to apply a lower voltage. On the other hand, in order to speed up the access time of the MOS transistors that constitute the peripheral circuit, it is necessary to increase the conductance of the MOS transistors.
It is necessary to reduce the number of people from 00 to 120 people. In other words, from the point of view of the transistor, if the external voltage was set to 5V, the voltage would increase from 2.5MV/cm of 4MDRAM to 4.2M.
The electric field applied to the oxide film becomes strong as V/cm, and a low positive ratio of the external power supply voltage is desired.

On the other hand, there is a request from Usa, who actually uses DRAM as a component, to fix the voltage to 5V. However, this is in the opposite direction to the direction of lower voltage.
It is a very difficult problem to optimally set the oxide film thickness so as to ensure long-term reliability and have high transistor performance. In addition, in DC operation, since a high electric field is applied, hot carriers generated during the switching operation process may be trapped in the gate oxide film, reducing the life of the oxide film. The reliability of the gate oxide film of transistors that are used in semiconductor devices is of greater concern than ever before.

(Problems to be Solved by the Invention) This invention has been made in view of the above-mentioned points.
It is an object of the present invention to provide a highly integrated semiconductor device such as an AM and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor device having a DRAM cell according to the present invention includes a MOS transistor that performs an on/off operation and constitutes a peripheral circuit section other than a memory cell of the semiconductor device. By having two or more types of gate oxide films with different thicknesses and introducing a second gate oxide film that is thicker than the first gate oxide film, the MOS to which an external voltage is applied is
The transistor and the MOS transistor in the data input/output portion include a MOS transistor having the second gate oxide film.
Using an S transistor, the external voltage is stepped down by a voltage step-down means in the peripheral circuit section, and the voltage that operates the memory cell in the semiconductor device, the capacitor of the cell peripheral circuit component, and the MOS transistor is set to the voltage step down. By using such a voltage, the gate oxide film of the capacitor and MOS transistor can be made thinner and have a smaller area, thereby improving the degree of integration of the semiconductor device.

(Function) In the semiconductor device, the N10S transistor that performs on and off operations constituting the peripheral circuit section other than the memory cell has two or more types of gate oxide films with different thicknesses,
Among the gate oxide films of different thicknesses of the OS transistors, the MOS transistor having the thickest gate oxide film is used for the part to which an external voltage is applied and the data input/output part; A MOS transistor having the thinnest oxide film among gate oxide films of different thicknesses, a capacitor in the memory cell region, and a MOS transistor.
A transistor is used for a memory cell in the semiconductor device and a peripheral circuit component of the cell, and the majority of the area on a chip of the semiconductor device is composed of a MOS transistor having a thin gate oxide film and a capacitor. By doing so, the degree of integration of the semiconductor device is improved. Furthermore, in a memory using the MOS transistor,
Access time becomes faster by thinning the gate oxide film.

(Example) Hereinafter, a semiconductor device and a manufacturing method thereof according to an example of the present invention will be described with reference to FIG. 1 and FIG. 2.

FIG. 1(a) to FIG. 1(d) are cross-sectional views showing the method of manufacturing the device of the first embodiment in the order of steps.

First, in FIG. 1(a), an element isolation region 2, a first gate oxide film 3 for a capacitor, a gate electrode 4 for a capacitor, and a trench groove are formed on a P-type semiconductor substrate 1 by a known process. 13 is shown, and the film thickness TOX of the first gate oxide film 3 for the capacitor is shown.
I will have 50 people.

In FIG. 1(b), a first oxide film 3 for a capacitor
is etched to expose the surface of the silicon substrate 1 up to the edge of the gate electrode 4, and a gate oxide film 5 is formed in the formation region for the first MOS transistor in an oxidizing atmosphere at 800°C.
The film is grown to a thickness of about 120 TOx2. Next, polysilicon containing N-type impurities is deposited over the entire surface and then patterned to form a plurality of gate electrodes 6 for the first MOS transistor.

In FIG. 1(c), the gate oxide film 5 for the first MOS transistor in the formation region for the second MOS transistor is removed by etching to expose the surface of the silicon substrate 1, and the gate oxide film 5 for the second Mo5 transistor is removed by etching. 7 to 8
The film is grown in an oxidizing atmosphere at 00° C. to a thickness of Tox3 by about 200 people.

At the same time, using a photoresist (not shown),
An oxide film 7' is deposited on the top and side surfaces of the gate electrode 6 for the MOS transistor. Next, on the gate oxide film 7 of the second MOS transistor, a gate electrode 8 for the second Mo5 transistor is formed of polysilicon containing N-type impurities, for example.

After that, using the gate electrode 8 as a mask, arsenic ions are applied to the region to become the source/drain diffusion layer at 5×10
After implanting about 15 Cz-2, arsenic ions are activated in a nitrogen atmosphere at 900° C. to form source/drain diffusion layers 9.

In FIG. 1(d), approximately 5,000 silicon oxide films 10 are deposited by the CVD method, and then contact holes 11 are formed in the gate and source/drain portions of each transistor.
1 is opened, aluminum wiring 12 is formed, and DRAM
A semiconductor device having cells is formed.

According to such a configuration, the second MOS transistor having the thickest gate oxide film 7 is used in the portion to which an external type i voltage of, for example, 5V is applied and the data input/output portion, and the second MOS transistor has the thickest gate oxide film 7. A thinner gate oxide film 5 is applied to the memory cell region of the semiconductor device and the peripheral circuit elements of the semiconductor device by lowering the external power supply voltage to, for example, 3 cm by a voltage step-down means (not shown) in an internal circuit other than the memory cell. By using the first MOS transistor having a thin gate oxide film, the degree of integration of the memory cell region and the cell peripheral circuit components is improved, and on the chip of the semiconductor device, the region of the element having a thin gate oxide film is The semiconductor device, which occupies most of the area, is formed. In addition, since we are trying to improve the memory capacity on the chip of the semiconductor device even slightly, by maximizing the memory cell area, the peripheral circuit configuration area other than the memory cells will inevitably become smaller. In this peripheral circuit portion, the area occupied by the second MOS transistor having the thickest oxide film 7 is larger than the area occupied by the first MOS transistor.

In the embodiment of the present invention, the gate oxide film of the switching transistor of the memory cell formed in the first M03 transistor region is the same as the gate oxide film of the MO3I-transistor of the peripheral circuit, but the third gate oxide film may be assumed to be the same as In other words, it is possible to step down the external power supply voltage in several steps in the internal circuit and use the intermediate potential as the word line level.
It is possible to make the electric field applied to the gate oxide film smaller than that of the gate oxide film connected to an external power supply voltage. Furthermore, in the embodiment of the present invention, the second gate electrode 6 on the second gate oxide film and the third gate electrode 8 on the third gate oxide film are formed in different steps. Of course, both gate oxide films may be formed under the same electrode in steps such as second gate oxidation, third gate oxidation, and second gate electrode.

Next, FIG. 2 shows a sectional view of a semiconductor device according to a second embodiment of the present invention.

This embodiment relates to a semiconductor device configured by stacking several layers of semiconductor elements on a known semiconductor substrate, and in the semiconductor device, a MOS having two or more types of gate oxide films of different thicknesses according to the present invention is used. It introduces a transistor and a capacitor with the thinnest gate oxide film.

In FIG. 2, the lower layer includes a first MOS transistor having the thinnest gate oxide film 205 among MoS transistors having gate oxide films of two or more different thicknesses, and an even thinner gate oxide film (not shown). A memory cell region and a cell peripheral circuit are formed on the semiconductor substrate 201 by the capacitors. Further, an inter-element insulating layer 214 is provided to insulate the lower-layer semiconductor element from the upper-layer semiconductor element, and a region 215 serving as a substrate for the upper-layer semiconductor is deposited on the inter-element insulating layer 214.
A second MOS transistor is formed having a gate oxide film 207 thicker than the gate oxide film of the MOS transistor. The electrical connection between the upper layer and the lower layer is made using aluminum wiring 2.
A region 215 taken in step 17 and serving as the upper semiconductor substrate
When passing through, they are insulated from each other by an insulating film 216.

According to such a configuration, the part to which an external voltage is applied and the data input/output part are arranged in the region where the second MOS transistor is formed in the upper layer, and the memory cell region and the data input/output part are arranged in the lower layer. By arranging the cell peripheral circuit component region, it is possible to improve the degree of integration of the semiconductor region in the lower layer, and by arranging the peripheral circuit portion other than the memory cell peripheral region in the upper layer, it is possible to improve the degree of integration of the semiconductor region in the lower layer. A semiconductor device with a smaller chip area than a semiconductor device can be realized.

[Effects of the Invention] As described above, according to the present invention, the electric field applied to the oxide film of the semiconductor device can be reduced by lowering the external power supply voltage in the voltage step-down means of the internal circuit of the semiconductor device. By optimizing the oxide film thickness for the voltage applied to each oxide film, the oxide film thickness can be reduced, the area of the oxide film can also be miniaturized, and the degree of integration of semiconductor devices can be improved. I can do it. Furthermore, in a MOS transistor, the access time becomes faster as the gate oxide film becomes thinner. Furthermore, as the thickness of the oxide film becomes thinner, the reliability of the oxide film improves, and therefore, reliability problems of the semiconductor device decrease. In addition, due to the manufacturing process, there is a problem that the oxide film formed in the later process has a higher defect density and the defect rate increases under the same electric field, but it is necessary to make the oxide film formed in the later process as thick as possible. This makes it possible to reduce the electric field applied to the oxide film, thereby achieving high reliability.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing method of a semiconductor device according to a first embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. 5. Figure 3 is a cross-sectional view of a semiconductor device manufactured by a conventional technique. 1... Silicon semiconductor substrate, 2... Field oxide film, 3... First gate oxide film,
4...First gate electrode, 5...Second
gate oxide film, 5'... oxide film on the first gate electrode, 6... second gate electrode, 7...
...Third gate oxide film, 7'...Oxide film on the second gate electrode, 8...Third gate electrode,
9... Source/drain diffusion layer, 10...
...Interlayer CVD silicon oxide film, 11...Contact hole, 12...Aluminum wiring, 13.
...Silicon trench groove. 201...
Silicon semiconductor substrate, 205...first MO5
Gate oxide film of I-transistor, 206...Gate electrode of first MOS transistor, 207...
...Gate oxide film of second MOS transistor, 208
...gate electrode of second MOS transistor,
209... Source/drain diffusion layer, 210.
...Lower interlayer insulating film, 210-...Upper interlayer insulating film, 211...Contact hole, 2
12...Lower layer aluminum wiring, 212-...
...Upper layer aluminum wiring, 214...
・Interelement insulating layer that insulates the upper layer and lower layer, 215...
. . . A layer that becomes the upper semiconductor substrate, 216 . . . An insulating layer that insulates the above 215 and the aluminum wiring, 217
・・・・・・Aluminum wiring connecting the upper and lower layers,
301...Silicon semiconductor substrate, 302...
...Field oxide film, 303...First gate oxide film, 304...First gate electrode, 3
05...Second gate oxide film, 305'...
...Oxide film on the first gate' electrode, 306...
...Second gate electrode, 309...Source/drain diffusion layer, 310...Interlayer CVD silicon oxide film, 311...Contact hole, 312...
...Aluminum wiring, 313...Silicon trench groove. Ql: Switching transistor of memory cell, Q2: Peripheral circuit transistor with thin gate oxide film, Q3: Peripheral circuit transistor with thickest gate oxide film . Figure MIMOS transistor area diagram

Claims (8)

[Claims] (1) Dynamic random access memory formed by one transistor and one capacitor (
Hereinafter, it will be abbreviated as DRAM. ) In a semiconductor device having cells on the same substrate, the film thickness is different from the first gate insulating film forming the capacitor gate of the DRAM cell, and the switching of the memory cell of the DRAM, the turning on of other than the transistor, In a MOS transistor that operates off, there are two or more types of gate insulating films with different thicknesses, and the total area of the thinnest gate insulating film among the gate insulating films of the MOS transistor is greater than the total area of the thickest gate insulating film. A semiconductor device characterized by its large size. (2) The MOS transistor having the thickest gate insulating film among the gate insulating films of the MOS transistor is used in a data input/output circuit portion and a portion to which an external power supply voltage is applied. 1) The semiconductor device described. (3) The semiconductor device according to claim (1), wherein the thinnest gate insulating film among the gate insulating films of the semiconductor device is used in a DRAM memory cell region and a cell peripheral circuit element formation region. Device. (4) forming a first gate insulating film for a capacitor of a DRAM memory cell formed by one transistor and one capacitor, and forming a first gate insulating film for a capacitor on the first gate insulating film for a capacitor; The process of forming a gate electrode and the first M which performs on/off operations other than the switching transistor of the DRAM memory cell.
After the step of forming the second gate insulating film of the OS transistor and the step of forming the second gate electrode on the second gate insulating film, the switching of the memory cell of the DRAM and the on/off operation of devices other than the transistor are performed. Second MO to do
It is characterized by comprising the steps of forming a third gate insulating film of the S transistor to be thicker than the second gate insulating film, and forming a third gate electrode on the third gate insulating film. A method for manufacturing a semiconductor device. (5) The method for manufacturing a semiconductor device according to claim (4), wherein the total area of the second gate insulating film is larger than the total area of the third gate insulating film. (6) With one transistor and one capacitor,
A first gate insulating film forming a capacitor gate of the DRAM cell in a semiconductor device having a DRAM cell to be formed on the same substrate and in which the element formation region is formed by stacking at least two layers. An MO with a film thickness different from that of
In an S transistor, there are two or more types of gate insulating films with different thicknesses, an element having the thinnest gate insulating film is formed in the bottom layer, and an element having the thickest gate insulating film in the top layer. 1. A semiconductor device comprising: (7) The semiconductor according to claim (6), wherein the thickest gate insulating film among the gate insulating films of the MOS transistor is used for a data input/output circuit portion and a portion to which an external voltage is applied. Device. (8) The semiconductor device according to claim (7), wherein the thinnest gate insulating film among the gate insulating films of the semiconductor device is used in a DRAM memory cell region and a cell peripheral circuit element formation region. .