JPS6184052A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reinforce the static dielectric strength by a method wherein the thickness of gate insulating film of transistor in the peripheral circuit is made thicker than the thickness of gate insulating film of inner circuit. CONSTITUTION:Oxide films 21, 22 are formed in Tr regions A, B on a P type Si substrate 11 provided with a thick oxide film 14. In such a constitution, assuming the final thickness of oxide film formed in the regions A, B to be tA, tB, the thickness DELTAt of films 21, 22 is set up to be equivalent to the thickness difference between tA and tB i.e. DELTAt=tA-tB. Next the film 22 in the region B only is removed to form another oxide film 23 in the region B by thermal oxidation simultaneously increasing the thickness of film 21 to form another oxide film 21'. Assuming the regions A, B respectively to peripheral part and inner part, the gate insulating film 21' of Tr provided on the peripheral part may be made thicker than that of inner part by DELTAt to reinforce the dielectric strength against any outer static electricity.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Sedentary Use) The present invention relates to a semiconductor device, and particularly to a semiconductor device including an N-channel silicon gate type to 108 transistors.

(Prior Art) Conventionally, in semiconductor integrated circuits (hereinafter referred to as NMO8 LSI) including N-channel silicon gate type MOS transistors, the S density has significantly improved due to the value set of element dimensions. It has been applied to logic LS such as micro combinators, contributing to higher functionality and faster speeds.

However, the high integration of NMOS-L, 19I has created various problems that need to be solved in terms of reliability. One of them is the problem of edge breakdown of the gate insulating film of a MOS transistor due to external static electricity. This is the game that makes up the MOS transistor) &
Since the dielectric film is a very thin insulating film, the input impedance is high, and high voltage from the outside is directly applied to this insulating film.

The following countermeasures have traditionally been taken against this issue. That is, a protection circuit is provided between the manual electrode pad of the NMOS-LSI and the input gate directly connected to it, and the flow of static electricity from the outside is attenuated just before it reaches the input gate, bypassing it to the silicon substrate side. It's a method. The most widely used protection circuit is a combination of a resistor of an N-type diffusion layer and a MO8 structure diode or transistor having a gate electrode grounded to the substrate side.

FIGS. 3(a) and 3(fb) are circuit diagrams of examples of conventional protection circuits for semiconductor devices.

In Figs. 3 fa) and (b), l is an electrode pad, 2 is an N-type diffused resistor, 3 is a gate control diode, and 4 is a gate control diode.
5 is a protection transistor, and 5 is an input transistor.

In the above two example circuits, the N-type diffused resistor limits the electrostatic discharge IE current, and the diode 3 or transistor 4 limits the discharge current by breaking down the PN junction under their silicon gate insulator at a low voltage. It serves to release air to the board side. And these protection circuits are NMO8
@Diffusion layers and MOS diodes or transistors can be made according to the original process of LSI, so
It also had the advantage of not requiring any additional processes.

(Problem to be Solved by the Invention) However, as the integration of N~10S-L'8I progresses, the thickness of the gate insulating film tends to become thinner and thinner, and the thickness of the MOS diode and transistor forming the protection circuit tends to become thinner. It has become inevitable that the protective ability of This is because a strong electric field is also applied to the gate insulating film when the PN junction breaks down, and an electric field that increases the dielectric strength of a thin insulating film is likely to be applied thereto. For this reason, it has always been necessary to improve the circuit format and planar pattern of this protection circuit in order to increase the integration density of NMO8@LSI. Figures 4 fa) to (d) show the conventional MO8 semiconductor device. 0, which is a cross-sectional view for explaining a part of the manufacturing process.
As shown in Figure (a), a thin insulating film 12 is provided on a P-type silicon substrate 11, and a silicon nitride film 13 is selectively formed thereon. Selective oxidation is performed using this silicon/nitride film 13 as a mask. Then, a thick insulating film 14 for blurring is formed.

Next, as shown in FIG. 4(b), the silicon nitride film 13
, the thin insulating film 12 is removed.

Next, as shown in FIG. 4(C), the entire surface is oxidized to form a gate insulating film 15.

Next, as shown in FIG. 4(d), gate electrodes 16 and 16' are formed of polysilicon, and using this as a mask, ions are implanted or expanded (11!). Two transistors are manufactured by forming source/drain regions 18.18' and 19.19' from LK.

Here, for the sake of convenience, regarding the two transistor regions A and B, the transistor region A is directly coupled to the peripheral electrode pad of the NMO, 5-LSI.

If we assume that the area of the transistor in or near the area is susceptible to stress due to external static electricity, and area B is an internal transistor area that is almost unaffected by static electricity, then according to the conventional back-path process, area A and area B are Since the gate dielectric film of the transistor in the region is formed at the same time, with the increase in integration density, increasing the 11 dielectric film to 4 will reduce the static electricity of the input and output transistors including the protection circuit existing in the region. A problem arises in that the dielectric strength decreases.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, maintain strength, and achieve high integration. An object of the present invention is to provide a semiconductor device including an N-channel 7-reconstituted MOS transistor capable of increasing speed. In a semiconductor device having an internal circuit and a peripheral circuit including transistors, a MOS transistor directly connected to input and output electrode pads and htO of the peripheral circuit
The gate insulating film of the S transistor is made thicker than the gate insulating film of the MOS transistor of the internal circuit.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views for explaining the tearing process of the first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate is
After forming a thick insulating film 14 in step 1, the silicon and nitride films used thereon and the thin insulating film are removed.

This state of the lily is the same as that shown in Fig. 3(b).

For convenience, exposed transistor regions are shown separately as A and B.

Next, as shown in FIG. 1 fb), the insulating film 2 is thermally oxidized
1 and 22 are formed. If the thickness of the insulating film formed in areas A and BK is respectively tAefB, then the insulating film 21
．． The thickness of the insulating film 22 is set so as to obtain a film thickness difference equivalent to Δ1 = 1 person - tB (the thickness of the insulating film 21 and 22 is not set to Δt). As shown in Figure (C), only the oxidized film 22 in area B is selectively removed.

Next, as shown in FIG. 1+dl, an insulating film 23 is formed in region B by thermal oxidation. At this time, the area A is also oxidized and the oxidized film becomes thick, becoming an insulating film 21'. 4 to 2
When the thickness of the insulating film 23 is tA and the thickness of the insulating film 23 is tB, the above-mentioned thickness Δt=tA-tB is realized.

Next, as shown in FIG. 1(e) K, a gate electrode 16.16', drain regions 18.18', and 19.19' are formed using a method similar to the conventional method. Considering region B as the interior, it is possible to make the gate insulating film thickness of the transistors in the peripheral circuit and the transistors in the internal circuit different, thereby maintaining quietness and achieving high concentration and speed. By measuring this, a suitable semiconductor device can be obtained.

FIGS. 2(a) to 2(d) #'i are sectional views for explaining the manufacturing process of the second embodiment of the present invention.

First, as shown in FIG. 2(at), a thick insulating film 14 is formed on the surface of the substrate 11 in the same manner as in FIG. 1(a).

Next, as shown in FIG. 2(b), the insulating film 2 is thermally oxidized.
1' and 23' are formed. At this time, the insulating film 22'
, 23' are formed to have the same thickness as tA described above.

Next, as shown in Figure 2 (C)K, using the hot etching method, the oxidized 123' of Taisun B is etched until it becomes as shallow as the above-mentioned ty. .

Remove the toes p and △. In this way, the thickness of the insulating film is the same as that of the 1ζ shown in Fig. 1 (id). Next, as shown in Fig. 2 (d), using the conventional method, the foot LTh16.16', - Form drain regions 18.18' and 19.19'. Even in this way, it is possible to form something that is exactly the same as the first embodiment.

(1 Akinori J Wood) As stated above, the present invention (according to the invention) differs the gate strength and thickness of transistors in the peripheral circuit and transistors in the internal circuit to improve electrostatic resistance. It is possible to obtain a semiconductor device that maintains the same characteristics and is designed to reduce aging and speed up.

[Brief explanation of the drawing]

Fig. 1 (Ω) to (el are cross-sectional views for explaining the manufacturing process of the first flow side of the present invention, and Fig. 2 (a) to (d) are cross-sectional views of the second embodiment of the present invention. 3(at) and 3(b) are circuit diagrams of examples of protection circuits for conventional semiconductor devices, and FIGS. 4(a) to (d) are cross-sectional views for explaining the manufacturing process.
FIG. 8 is a cross-sectional view for explaining a part of the manufacturing process of the No. 8 semiconductor device. ■... Electrode pad, 2... N-type diffused resistor, 3... Gate control diode, 4
...Transistor for storage, 5... Kugata transistor, 11... P-type silicon is analyzed, 12
...Insulating film, 13...Silicon nitride film,
14. River insulating film, 15... Gate insulating film, 16.
+6'-=-gate insulating film, 18°18',
19. 19' Four-once-train Irp15.
21.21/, 22.23.23'...Yamahano laments. ㉟〇　　　　　　　　　　　　　　　

Claims (1)

[Claims] In a semiconductor device having an internal circuit and a peripheral circuit including MOS transistors on a semiconductor substrate, the thickness of the gate insulating film of the MOS transistor directly connected to the input and output electrode pads and the MOS transistor of the peripheral circuit is as described above. A semiconductor device characterized by being formed thicker than a gate insulating film of a MOS transistor in an internal circuit.