JPH04359473A - Insulation gate type field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a structure which is strong against electrostatic withstand voltage by providing a gate electrode which consists of a polysilicon with a narrower width than that of a field oxide film on the field oxide film. CONSTITUTION:A drain region 21 and a source region 22 are provided respectively at semiconductor regions of one side and the other side, of a field oxide film 20 which is formed on a semiconductor substrate 19. Then, a gate electrode 24 which consists of a polysilicon is provided on the field oxide film 20 with a semiconductor region 23 at a lower portion of the field oxide film 20 as a channel region. where the gate electrode 24 has a width W28 which is formed narrower than a width W29 of a field oxide film 29 and constant spacings LA and LB are provided between a side edge portion 28A and a drain region 26 and between a side edge portion 28B and the source region 22, thus enabling an electrostatic protection circuit which is strong against electrostatic breakdown to be constituted and an area which is occupied, by an internal circuit to be increased for highly integrating the internal circuit.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device (
The present invention relates to an insulated gate field effect transistor (hereinafter referred to as a MOS transistor) suitable for use in configuring an electrostatic protection circuit for an LSI (hereinafter referred to as an LSI).

0002

2. Description of the Related Art In general, an LSI is provided with an electrostatic protection circuit, the circuit diagram of which is shown in FIG. 8, for example. In the figure, 1 is a pad, 2 and 3 are nMOS transistors,
4 is a diffused resistance, and nMOS transistors 2 and 3 are
Conventionally, so-called Al (aluminum), which is resistant to electrostatic damage, has been used.
Field transistor (Al on field oxide film)
(MOS transistor) with a gate electrode of

For example, FIG. 9 shows Al field
10 is a plan view showing a part of the electrostatic protection circuit of FIG. 8 configured using transistors, and FIG. 10 is a cross-sectional view taken along line AA of FIG. 9. In FIG. 9, 5 is a P-type silicon substrate, 6 is a drain region of the nMOS transistor 2 made of an N+ diffusion layer, 7 is a source region of the nMOS transistor 2 made of an N+ diffusion layer, and 8 is an nMOS made of Al.
Gate electrode of transistor 2, 9 is GND made of Al
(ground) line, 10 is pad 1 and nMOS transistor 2
Contact holes 11 to 13 are for making contact with the drain region 6 of the nMOS transistor 2, and contact holes 11 to 13 are for making contact between the source region 7 of the nMOS transistor 2 and the GND line 9. Further, in FIG. 10, 14 is a field oxide film, and 15 is an interlayer insulating layer made of a SiN film.

0004

[Problems to be Solved by the Invention] In order to achieve high integration in LSIs, it is required to increase the area occupied by internal circuits, and in response to this, the area occupied by electrostatic protection circuits is increased. It is required to reduce the area as much as possible.

Conventionally, as a device to meet this requirement, for example, in the case of the electrostatic discharge protection circuit shown in FIG. A method using silicon field transistors has been proposed. In the figure, 16 is a gate electrode made of polysilicon, 17 and 18 are gate oxide films made of SiO2, and parts corresponding to those in FIG. 10 are given the same reference numerals. According to this method, as shown by the two-dot chain line in FIG.
Since the D line 9 can be wired, the area occupied by the internal circuit can be increased and the internal circuit can be highly integrated.

However, the nMOS transistor 2 constructed as shown in FIG. 11 has a problem in that the gate oxide films 17 and 18 are easily damaged by electrostatic discharge, and has not been used so far.

[0007] In view of this point, the present invention is an LSI
When applied to a transistor in an electrostatic protection circuit, it is possible to construct an electrostatic protection circuit that is resistant to electrostatic damage, and to increase the area occupied by the internal circuit, thereby achieving high integration of the internal circuit. An object of the present invention is to provide a MOS transistor that can perform the following functions.

[0008]

[Means for Solving the Problems] FIG. 1 is an explanatory diagram of the principle of the present invention, and an insulated gate field effect transistor according to the present invention has a field oxide film 20 formed on a semiconductor substrate 19 on one side and the other side. A drain region 21 and a source region 22 are provided in each semiconductor region, and a field oxide film 20 is formed on the field oxide film 20 with the semiconductor region 23 below the field oxide film 20 serving as a channel region.
Gate electrode 2 made of polysilicon with a width narrower than the width of
4.

[0009]

In the present invention, the gate electrode 24 made of polysilicon is provided, and its width is narrower than the width of the field oxide film 20, so that the structure is strong against electrostatic breakdown voltage. Furthermore, when the present invention is applied to a transistor in an LSI electrostatic protection circuit, a power supply line or a ground line made of Al can be wired above the gate electrode 24 via an interlayer insulating film. It is possible to increase the area occupied by the internal circuit and achieve high integration.

0010

Embodiment An embodiment of the present invention and its application examples will be described below with reference to FIGS. 2 to 4.

FIG. 2 is a sectional view showing one embodiment of the present invention, and this embodiment is a case where the present invention is applied to an nMOS transistor. In the figure, 25 is a P-type silicon substrate, 2
6 is a drain region made of an N+ diffusion layer, 27 is a source region made of an N+ diffusion layer, 28 is a gate electrode made of polysilicon, 29 is a field oxide film, and the gate electrode 28 made of polysilicon has a width W28. , are formed narrower than the width W29 of the field oxide film 29, and have constant intervals LA and LB between one side edge 28A and the drain region 26 and between the other side edge 28B and the source region, respectively. is configured so that it exists. That is, it has a structure that is resistant to electrostatic discharge voltage.

FIG. 3 is a plan view showing a part of the electrostatic protection circuit shown in FIG. 8 constructed using the nMOS transistor of this embodiment, and FIG. 4 is a cross-sectional view taken along line BB in FIG. In FIGS. 3 and 4, parts corresponding to those in FIGS. 9 and 10 are designated by the same reference numerals. Here, 30 is a gate electrode made of polysilicon, and 31 is a contact hole for making contact between the gate electrode 30 and the GND line 9. Note that in FIGS. 3 and 4, the symbols in parentheses indicate the corresponding parts in FIG.

In this way, when constructing the electrostatic protection circuit of FIG. 8 using this embodiment, the GND line 9 made of Al is connected above the gate electrode 30 as shown in FIGS. 3 and 4. can be placed through the interlayer insulating film 15,
Distance P from the end of the P-type silicon substrate 5 to the GND line 9
can be made shorter than the case shown in FIG. As a result, the area occupied by the internal circuit can be increased, and the internal circuit can be highly integrated.

The present invention can be applied not only to the electrostatic protection circuit shown in FIG. 8 but also to the construction of electrostatic protection circuits as shown in FIGS. 5 to 7. In the figure, 32, 3
3 is a pMOS transistor.

[0015]

According to the present invention, when the present invention is applied to a transistor of an electrostatic protection circuit of an LSI, an electrostatic protection circuit that is resistant to electrostatic damage can be constructed, and the internal circuit occupies less The area can be increased and the internal circuitry can be highly integrated.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a sectional view showing an embodiment of the present invention.

FIG. 3 is a plan view showing a portion of the electrostatic protection circuit of FIG. 8 constructed using an embodiment of the present invention.

FIG. 4 is a sectional view taken along line BB in FIG. 3;

FIG. 5 is a circuit diagram showing an electrostatic protection circuit.

FIG. 6 is a circuit diagram showing an electrostatic protection circuit.

FIG. 7 is a circuit diagram showing an electrostatic protection circuit.

FIG. 8 is a circuit diagram showing an electrostatic protection circuit.

9 is a plan view of a portion of the electrostatic protection circuit of FIG. 8 constructed using Al field transistors; FIG.

10 is a cross-sectional view taken along line AA in FIG. 9. FIG.

FIG. 11 is a cross-sectional view of a conventional poly field transistor.

[Explanation of symbols]

19 Semiconductor substrate 20 Field oxide film 21 Drain region 22 Source area

Claims (1)

[Claims] 1. A drain region (21) and a source region (22) are provided in the semiconductor regions on one side and the other side of a field oxide film (20) formed on a semiconductor substrate (19), respectively, and the field oxide film (20) is provided with a drain region (21) and a source region (22), respectively. A gate electrode (2) made of polysilicon and having a width narrower than the width of the field oxide film (20) is formed on the field oxide film (20) using the semiconductor region (23) under the film (20) as a channel region.
4) An insulated gate field effect transistor comprising: